projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| b303605e MK |
1 | /** @file\r |
| 2 | \r | |
| 3 | Copyright (c) 2013-2015 Intel Corporation.\r | |
| 4 | \r | |
| 0eb3de2e | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| b303605e MK |
6 | \r |
| 7 | \r | |
| 8 | **/\r | |
| 9 | \r | |
| 10 | #ifndef _SPI_FLASH_DEVICE_H_\r | |
| 11 | #define _SPI_FLASH_DEVICE_H_\r | |
| 12 | \r | |
| 13 | #include <PiDxe.h>\r | |
| 14 | #include <Protocol/Spi.h>\r | |
| 15 | #include <Protocol/FirmwareVolumeBlock.h>\r | |
| 16 | \r | |
| 17 | //\r | |
| 18 | // Supported SPI Flash Devices\r | |
| 19 | //\r | |
| 20 | typedef enum {\r | |
| 21 | EnumSpiFlash25L3205D, // Macronix 32Mbit part\r | |
| 22 | EnumSpiFlashW25Q32, // Winbond 32Mbit part\r | |
| 23 | EnumSpiFlashW25X32, // Winbond 32Mbit part\r | |
| 24 | EnumSpiFlashAT25DF321, // Atmel 32Mbit part\r | |
| 25 | EnumSpiFlashQH25F320, // Intel 32Mbit part\r | |
| 26 | EnumSpiFlash25VF064C, // SST 64Mbit part\r | |
| 27 | EnumSpiFlashM25PX64, // NUMONYX 64Mbit part\r | |
| 28 | EnumSpiFlashAT25DF641, // Atmel 64Mbit part\r | |
| 29 | EnumSpiFlashS25FL064K, // Spansion 64Mbit part\r | |
| 30 | EnumSpiFlash25L6405D, // Macronix 64Mbit part\r | |
| 31 | EnumSpiFlashW25Q64, // Winbond 64Mbit part\r | |
| 32 | EnumSpiFlashW25X64, // Winbond 64Mbit part\r | |
| 33 | EnumSpiFlashQH25F640, // Intel 64Mbit part\r | |
| 34 | EnumSpiFlashMax\r | |
| 35 | } SPI_FLASH_TYPES_SUPPORTED;\r | |
| 36 | \r | |
| 37 | //\r | |
| 38 | // Flash Device commands\r | |
| 39 | //\r | |
| 40 | // If a supported device uses a command different from the list below, a device specific command\r | |
| 41 | // will be defined just below it's JEDEC id section.\r | |
| 42 | //\r | |
| 43 | #define SPI_COMMAND_WRITE 0x02\r | |
| 44 | #define SPI_COMMAND_WRITE_AAI 0xAD\r | |
| 45 | #define SPI_COMMAND_READ 0x03\r | |
| 46 | #define SPI_COMMAND_ERASE 0x20\r | |
| 47 | #define SPI_COMMAND_WRITE_DISABLE 0x04\r | |
| 48 | #define SPI_COMMAND_READ_S 0x05\r | |
| 49 | #define SPI_COMMAND_WRITE_ENABLE 0x06\r | |
| 50 | #define SPI_COMMAND_READ_ID 0xAB\r | |
| 51 | #define SPI_COMMAND_JEDEC_ID 0x9F\r | |
| 52 | #define SPI_COMMAND_WRITE_S_EN 0x50\r | |
| 53 | #define SPI_COMMAND_WRITE_S 0x01\r | |
| 54 | #define SPI_COMMAND_CHIP_ERASE 0xC7\r | |
| 55 | #define SPI_COMMAND_BLOCK_ERASE 0xD8\r | |
| 56 | \r | |
| 57 | //\r | |
| 58 | // Flash JEDEC device ids\r | |
| 59 | //\r | |
| 60 | // SST 8Mbit part\r | |
| 61 | //\r | |
| 62 | #define SPI_SST25VF080B_ID1 0xBF\r | |
| 63 | #define SPI_SST25VF080B_ID2 0x25\r | |
| 64 | #define SPI_SST25VF080B_ID3 0x8E\r | |
| 65 | //\r | |
| 66 | // SST 16Mbit part\r | |
| 67 | //\r | |
| 68 | #define SPI_SST25VF016B_ID1 0xBF\r | |
| 69 | #define SPI_SST25VF016B_ID2 0x25\r | |
| 70 | #define SPI_SST25V016BF_ID3 0x41\r | |
| 71 | //\r | |
| 72 | // Macronix 32Mbit part\r | |
| 73 | //\r | |
| 74 | // MX25 part does not support WRITE_AAI comand (0xAD)\r | |
| 75 | //\r | |
| 76 | #define SPI_MX25L3205_ID1 0xC2\r | |
| 77 | #define SPI_MX25L3205_ID2 0x20\r | |
| 78 | #define SPI_MX25L3205_ID3 0x16\r | |
| 79 | //\r | |
| 80 | // Intel 32Mbit part bottom boot\r | |
| 81 | //\r | |
| 82 | #define SPI_QH25F320_ID1 0x89\r | |
| 83 | #define SPI_QH25F320_ID2 0x89\r | |
| 84 | #define SPI_QH25F320_ID3 0x12 // 32Mbit bottom boot\r | |
| 85 | //\r | |
| 86 | // Intel 64Mbit part bottom boot\r | |
| 87 | //\r | |
| 88 | #define SPI_QH25F640_ID1 0x89\r | |
| 89 | #define SPI_QH25F640_ID2 0x89\r | |
| 90 | #define SPI_QH25F640_ID3 0x13 // 64Mbit bottom boot\r | |
| 91 | //\r | |
| 92 | // QH part does not support command 0x20 for erase; only 0xD8 (sector erase)\r | |
| 93 | // QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part)\r | |
| 94 | // 0x40 command ignored if address outside of parameter block range\r | |
| 95 | //\r | |
| 96 | #define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40\r | |
| 97 | //\r | |
| 98 | // Winbond 32Mbit part\r | |
| 99 | //\r | |
| 100 | #define SPI_W25X32_ID1 0xEF\r | |
| 101 | #define SPI_W25X32_ID2 0x30 // Memory Type\r | |
| 102 | #define SPI_W25X32_ID3 0x16 // Capacity\r | |
| 103 | #define SF_DEVICE_ID1_W25Q32 0x16\r | |
| 104 | \r | |
| 105 | //\r | |
| 106 | // Winbond 64Mbit part\r | |
| 107 | //\r | |
| 108 | #define SPI_W25X64_ID1 0xEF\r | |
| 109 | #define SPI_W25X64_ID2 0x30 // Memory Type\r | |
| 110 | #define SPI_W25X64_ID3 0x17 // Capacity\r | |
| 111 | #define SF_DEVICE_ID0_W25QXX 0x40\r | |
| 112 | #define SF_DEVICE_ID1_W25Q64 0x17\r | |
| 113 | //\r | |
| 114 | // Winbond 128Mbit part\r | |
| 115 | //\r | |
| 116 | #define SF_DEVICE_ID0_W25Q128 0x40\r | |
| 117 | #define SF_DEVICE_ID1_W25Q128 0x18\r | |
| 118 | \r | |
| 119 | //\r | |
| 120 | // Atmel 32Mbit part\r | |
| 121 | //\r | |
| 122 | #define SPI_AT26DF321_ID1 0x1F\r | |
| 123 | #define SPI_AT26DF321_ID2 0x47 // [7:5]=Family, [4:0]=Density\r | |
| 124 | #define SPI_AT26DF321_ID3 0x00\r | |
| 125 | \r | |
| 126 | #define SF_VENDOR_ID_ATMEL 0x1F\r | |
| 127 | #define SF_DEVICE_ID0_AT25DF641 0x48\r | |
| 128 | #define SF_DEVICE_ID1_AT25DF641 0x00\r | |
| 129 | \r | |
| 130 | //\r | |
| 131 | // SST 8Mbit part\r | |
| 132 | //\r | |
| 133 | #define SPI_SST25VF080B_ID1 0xBF\r | |
| 134 | #define SPI_SST25VF080B_ID2 0x25\r | |
| 135 | #define SPI_SST25VF080B_ID3 0x8E\r | |
| 136 | #define SF_DEVICE_ID0_25VF064C 0x25\r | |
| 137 | #define SF_DEVICE_ID1_25VF064C 0x4B\r | |
| 138 | \r | |
| 139 | //\r | |
| 140 | // SST 16Mbit part\r | |
| 141 | //\r | |
| 142 | #define SPI_SST25VF016B_ID1 0xBF\r | |
| 143 | #define SPI_SST25VF016B_ID2 0x25\r | |
| 144 | #define SPI_SST25V016BF_ID3 0x41\r | |
| 145 | \r | |
| 146 | //\r | |
| 147 | // Winbond 32Mbit part\r | |
| 148 | //\r | |
| 149 | #define SPI_W25X32_ID1 0xEF\r | |
| 150 | #define SPI_W25X32_ID2 0x30 // Memory Type\r | |
| 151 | #define SPI_W25X32_ID3 0x16 // Capacity\r | |
| 152 | \r | |
| 153 | #define SF_VENDOR_ID_MX 0xC2\r | |
| 154 | #define SF_DEVICE_ID0_25L6405D 0x20\r | |
| 155 | #define SF_DEVICE_ID1_25L6405D 0x17\r | |
| 156 | \r | |
| 157 | #define SF_VENDOR_ID_NUMONYX 0x20\r | |
| 158 | #define SF_DEVICE_ID0_M25PX64 0x71\r | |
| 159 | #define SF_DEVICE_ID1_M25PX64 0x17\r | |
| 160 | \r | |
| 161 | //\r | |
| 162 | // Spansion 64Mbit part\r | |
| 163 | //\r | |
| 164 | #define SF_VENDOR_ID_SPANSION 0xEF\r | |
| 165 | #define SF_DEVICE_ID0_S25FL064K 0x40\r | |
| 166 | #define SF_DEVICE_ID1_S25FL064K 0x00\r | |
| 167 | \r | |
| 168 | //\r | |
| 169 | // index for prefix opcodes\r | |
| 170 | //\r | |
| 171 | #define SPI_WREN_INDEX 0 // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE\r | |
| 172 | #define SPI_EWSR_INDEX 1 // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN\r | |
| 173 | #define BIOS_CTRL 0xDC\r | |
| 174 | \r | |
| 175 | #define PFAB_CARD_DEVICE_ID 0x5150\r | |
| 176 | #define PFAB_CARD_VENDOR_ID 0x8086\r | |
| 177 | #define PFAB_CARD_SETUP_REGISTER 0x40\r | |
| 178 | #define PFAB_CARD_SETUP_BYTE 0x0d\r | |
| 179 | \r | |
| 180 | \r | |
| 181 | #endif\r |