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1 | /** @file\r |
2 | Library functions for Setting QNC internal network port\r | |
3 | \r | |
4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
5 | \r | |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __QNC_ACCESS_LIB_H__\r | |
17 | #define __QNC_ACCESS_LIB_H__\r | |
18 | \r | |
19 | #include <IntelQNCRegs.h>\r | |
20 | \r | |
21 | #define MESSAGE_READ_DW(Port, Reg) \\r | |
22 | (UINT32)((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r | |
23 | \r | |
24 | #define MESSAGE_WRITE_DW(Port, Reg) \\r | |
25 | (UINT32)((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r | |
26 | \r | |
27 | #define ALT_MESSAGE_READ_DW(Port, Reg) \\r | |
28 | (UINT32)((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r | |
29 | \r | |
30 | #define ALT_MESSAGE_WRITE_DW(Port, Reg) \\r | |
31 | (UINT32)((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r | |
32 | \r | |
33 | #define MESSAGE_IO_READ_DW(Port, Reg) \\r | |
34 | (UINT32)((QUARK_OPCODE_IO_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r | |
35 | \r | |
36 | #define MESSAGE_IO_WRITE_DW(Port, Reg) \\r | |
37 | (UINT32)((QUARK_OPCODE_IO_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r | |
38 | \r | |
39 | #define MESSAGE_SHADOW_DW(Port, Reg) \\r | |
40 | (UINT32)((QUARK_DRAM_BASE_ADDR_READY << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)\r | |
41 | \r | |
42 | \r | |
43 | /**\r | |
44 | Read required data from QNC internal message network\r | |
45 | **/\r | |
46 | UINT32\r | |
47 | EFIAPI\r | |
48 | QNCPortRead(\r | |
49 | UINT8 Port,\r | |
50 | UINT32 RegAddress\r | |
51 | );\r | |
52 | \r | |
53 | /**\r | |
54 | Write prepared data into QNC internal message network.\r | |
55 | \r | |
56 | **/\r | |
57 | VOID\r | |
58 | EFIAPI\r | |
59 | QNCPortWrite (\r | |
60 | UINT8 Port,\r | |
61 | UINT32 RegAddress,\r | |
62 | UINT32 WriteValue\r | |
63 | );\r | |
64 | \r | |
65 | /**\r | |
66 | Read required data from QNC internal message network\r | |
67 | **/\r | |
68 | UINT32\r | |
69 | EFIAPI\r | |
70 | QNCAltPortRead(\r | |
71 | UINT8 Port,\r | |
72 | UINT32 RegAddress\r | |
73 | );\r | |
74 | \r | |
75 | /**\r | |
76 | Write prepared data into QNC internal message network.\r | |
77 | \r | |
78 | **/\r | |
79 | VOID\r | |
80 | EFIAPI\r | |
81 | QNCAltPortWrite (\r | |
82 | UINT8 Port,\r | |
83 | UINT32 RegAddress,\r | |
84 | UINT32 WriteValue\r | |
85 | );\r | |
86 | \r | |
87 | /**\r | |
88 | Read required data from QNC internal message network\r | |
89 | **/\r | |
90 | UINT32\r | |
91 | EFIAPI\r | |
92 | QNCPortIORead(\r | |
93 | UINT8 Port,\r | |
94 | UINT32 RegAddress\r | |
95 | );\r | |
96 | \r | |
97 | /**\r | |
98 | Write prepared data into QNC internal message network.\r | |
99 | \r | |
100 | **/\r | |
101 | VOID\r | |
102 | EFIAPI\r | |
103 | QNCPortIOWrite (\r | |
104 | UINT8 Port,\r | |
105 | UINT32 RegAddress,\r | |
106 | UINT32 WriteValue\r | |
107 | );\r | |
108 | \r | |
109 | /**\r | |
110 | This is for the special consideration for QNC MMIO write, as required by FWG,\r | |
111 | a reading must be performed after MMIO writing to ensure the expected write\r | |
112 | is processed and data is flushed into chipset\r | |
113 | \r | |
114 | **/\r | |
115 | RETURN_STATUS\r | |
116 | EFIAPI\r | |
117 | QNCMmIoWrite (\r | |
118 | UINT32 MmIoAddress,\r | |
119 | QNC_MEM_IO_WIDTH Width,\r | |
120 | UINT32 DataNumber,\r | |
121 | VOID *pData\r | |
122 | );\r | |
123 | \r | |
124 | UINT32\r | |
125 | EFIAPI\r | |
126 | QncHsmmcRead (\r | |
127 | VOID\r | |
128 | );\r | |
129 | \r | |
130 | VOID\r | |
131 | EFIAPI\r | |
132 | QncHsmmcWrite (\r | |
133 | UINT32 WriteValue\r | |
134 | );\r | |
135 | \r | |
136 | VOID\r | |
137 | EFIAPI\r | |
138 | QncImrWrite (\r | |
139 | UINT32 ImrBaseOffset,\r | |
140 | UINT32 ImrLow,\r | |
141 | UINT32 ImrHigh,\r | |
142 | UINT32 ImrReadMask,\r | |
143 | UINT32 ImrWriteMask\r | |
144 | );\r | |
145 | \r | |
146 | VOID\r | |
147 | EFIAPI\r | |
148 | QncIClkAndThenOr (\r | |
149 | UINT32 RegAddress,\r | |
150 | UINT32 AndValue,\r | |
151 | UINT32 OrValue\r | |
152 | );\r | |
153 | \r | |
154 | VOID\r | |
155 | EFIAPI\r | |
156 | QncIClkOr (\r | |
157 | UINT32 RegAddress,\r | |
158 | UINT32 OrValue\r | |
159 | );\r | |
160 | \r | |
161 | UINTN\r | |
162 | EFIAPI\r | |
163 | QncGetPciExpressBaseAddress (\r | |
164 | VOID\r | |
165 | );\r | |
166 | \r | |
167 | #endif\r |