[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Include / Protocol / Spi.h

/** @file\r
This file defines the EFI SPI Protocol which implements the\r
Intel(R) ICH SPI Host Controller Compatibility Interface.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
\r
**/\r
#ifndef _SPI_H_\r
#define _SPI_H_\r
\r
//\r
// Define the SPI protocol GUID\r
//\r
// EDK and EDKII have different GUID formats\r
//\r
#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)\r
#define EFI_SPI_PROTOCOL_GUID \\r
  { \\r
    0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
  }\r
#define EFI_SMM_SPI_PROTOCOL_GUID \\r
  { \\r
    0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
  }\r
#else\r
#define EFI_SPI_PROTOCOL_GUID \\r
  { \\r
    0x1156efc6, 0xea32, 0x4396, \\r
    { \\r
      0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
    } \\r
  }\r
#define EFI_SMM_SPI_PROTOCOL_GUID \\r
  { \\r
    0xD9072C35, 0xEB8F, 0x43ad, \\r
    { \\r
      0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
    } \\r
  }\r
#endif\r
//\r
// Extern the GUID for protocol users.\r
//\r
extern EFI_GUID                   gEfiSpiProtocolGuid;\r
extern EFI_GUID                   gEfiSmmSpiProtocolGuid;\r
\r
//\r
// Forward reference for ANSI C compatibility\r
//\r
typedef struct _EFI_SPI_PROTOCOL  EFI_SPI_PROTOCOL;\r
\r
//\r
// SPI protocol data structures and definitions\r
//\r
//\r
// Number of Prefix Opcodes allowed on the SPI interface\r
//\r
#define SPI_NUM_PREFIX_OPCODE 2\r
\r
//\r
// Number of Opcodes in the Opcode Menu\r
//\r
#define SPI_NUM_OPCODE  8\r
\r
#ifdef SERVER_BIOS_FLAG\r
//\r
// SPI default opcode slots\r
//\r
#define SPI_OPCODE_JEDEC_ID_INDEX        0\r
#endif // SERVER_BIOS_FLAG\r
\r
//\r
// Opcode Type\r
//    EnumSpiOpcodeCommand: Command without address\r
//    EnumSpiOpcodeRead: Read with address\r
//    EnumSpiOpcodeWrite: Write with address\r
//\r
typedef enum {\r
  EnumSpiOpcodeReadNoAddr,\r
  EnumSpiOpcodeWriteNoAddr,\r
  EnumSpiOpcodeRead,\r
  EnumSpiOpcodeWrite,\r
  EnumSpiOpcodeMax\r
} SPI_OPCODE_TYPE;\r
\r
typedef enum {\r
  EnumSpiCycle20MHz,\r
  EnumSpiCycle33MHz,\r
  EnumSpiCycle66MHz,  // not supported by PCH\r
  EnumSpiCycle50MHz,\r
  EnumSpiCycleMax\r
} SPI_CYCLE_FREQUENCY;\r
\r
typedef enum {\r
  EnumSpiRegionAll,\r
  EnumSpiRegionBios,\r
  EnumSpiRegionMe,\r
  EnumSpiRegionGbE,\r
  EnumSpiRegionDescriptor,\r
  EnumSpiRegionPlatformData,\r
  EnumSpiRegionMax\r
} SPI_REGION_TYPE;\r
\r
//\r
// Hardware Sequencing required operations (as listed in CougarPoint EDS Table 5-55: "Hardware\r
// Sequencing Commands and Opcode Requirements"\r
//\r
typedef enum {\r
  EnumSpiOperationWriteStatus,\r
  EnumSpiOperationProgramData_1_Byte,\r
  EnumSpiOperationProgramData_64_Byte,\r
  EnumSpiOperationReadData,\r
  EnumSpiOperationWriteDisable,\r
  EnumSpiOperationReadStatus,\r
  EnumSpiOperationWriteEnable,\r
  EnumSpiOperationFastRead,\r
  EnumSpiOperationEnableWriteStatus,\r
  EnumSpiOperationErase_256_Byte,\r
  EnumSpiOperationErase_4K_Byte,\r
  EnumSpiOperationErase_8K_Byte,\r
  EnumSpiOperationErase_64K_Byte,\r
  EnumSpiOperationFullChipErase,\r
  EnumSpiOperationJedecId,\r
  EnumSpiOperationDualOutputFastRead,\r
  EnumSpiOperationDiscoveryParameters,\r
  EnumSpiOperationOther,\r
  EnumSpiOperationMax\r
} SPI_OPERATION;\r
\r
//\r
// Opcode menu entries\r
//   Type            Operation Type (value to be programmed to the OPTYPE register)\r
//   Code            The opcode (value to be programmed to the OPMENU register)\r
//   Frequency       The expected frequency to be used (value to be programmed to the SSFC\r
//                   Register)\r
//   Operation       Which Hardware Sequencing required operation this opcode respoinds to.\r
//                   The required operations are listed in EDS Table 5-55: "Hardware\r
//                   Sequencing Commands and Opcode Requirements"\r
//                   If the opcode does not corresponds to any operation listed, use\r
//                   EnumSpiOperationOther\r
//\r
typedef struct _SPI_OPCODE_MENU_ENTRY {\r
  SPI_OPCODE_TYPE     Type;\r
  UINT8               Code;\r
  SPI_CYCLE_FREQUENCY Frequency;\r
  SPI_OPERATION       Operation;\r
} SPI_OPCODE_MENU_ENTRY;\r
\r
//\r
// Initialization data table loaded to the SPI host controller\r
//    VendorId        Vendor ID of the SPI device\r
//    DeviceId0       Device ID0 of the SPI device\r
//    DeviceId1       Device ID1 of the SPI device\r
//    PrefixOpcode    Prefix opcodes which are loaded into the SPI host controller\r
//    OpcodeMenu      Opcodes which are loaded into the SPI host controller Opcode Menu\r
//    BiosStartOffset The offset of the start of the BIOS image relative to the flash device.\r
//                    Please note this is a Flash Linear Address, NOT a memory space address.\r
//                    This value is platform specific and depends on the system flash map.\r
//                    This value is only used on non Descriptor mode.\r
//    BiosSize        The the BIOS Image size in flash. This value is platform specific\r
//                    and depends on the system flash map. Please note BIOS Image size may\r
//                    be smaller than BIOS Region size (in Descriptor Mode) or the flash size\r
//                    (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be\r
//                    placed at the top end of the BIOS Region (in Descriptor Mode) or the flash\r
//                    (in Non Descriptor Mode)\r
//\r
typedef struct _SPI_INIT_TABLE {\r
  UINT8                 VendorId;\r
  UINT8                 DeviceId0;\r
  UINT8                 DeviceId1;\r
  UINT8                 PrefixOpcode[SPI_NUM_PREFIX_OPCODE];\r
  SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE];\r
  UINTN                 BiosStartOffset;\r
  UINTN                 BiosSize;\r
} SPI_INIT_TABLE;\r
\r
//\r
// Public Info struct to show current initialized state of the spi interface.\r
// OpcodeIndex must be less then SPI_NUM_OPCODE for operation to be supported.\r
//\r
typedef struct _SPI_INIT_INFO {\r
  SPI_INIT_TABLE        *InitTable;\r
  UINT8                 JedecIdOpcodeIndex;\r
  UINT8                 OtherOpcodeIndex;\r
  UINT8                 WriteStatusOpcodeIndex;\r
  UINT8                 ProgramOpcodeIndex;\r
  UINT8                 ReadOpcodeIndex;\r
  UINT8                 EraseOpcodeIndex;\r
  UINT8                 ReadStatusOpcodeIndex;\r
  UINT8                 FullChipEraseOpcodeIndex;\r
} SPI_INIT_INFO;\r
\r
//\r
// Protocol member functions\r
//\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SPI_INIT) (\r
  IN EFI_SPI_PROTOCOL     * This,\r
  IN SPI_INIT_TABLE       * InitTable\r
  );\r
/*++\r
\r
Routine Description:\r
\r
  Initializes the host controller to execute SPI commands.\r
\r
Arguments:\r
\r
  This                    Pointer to the EFI_SPI_PROTOCOL instance.\r
  InitTable               Pointer to caller-allocated buffer containing the SPI\r
                          interface initialization table.\r
\r
Returns:\r
\r
  EFI_SUCCESS             Opcode initialization on the SPI host controller completed.\r
  EFI_ACCESS_DENIED       The SPI configuration interface is locked.\r
  EFI_OUT_OF_RESOURCES    Not enough resource available to initialize the device.\r
  EFI_DEVICE_ERROR        Device error, operation failed.\r
\r
--*/\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SPI_LOCK) (\r
  IN EFI_SPI_PROTOCOL     * This\r
  );\r
/*++\r
\r
Routine Description:\r
\r
  Lock the SPI Static Configuration Interface.\r
  Once locked, the interface is no longer open for configuration changes.\r
  The lock state automatically clears on next system reset.\r
\r
Arguments:\r
\r
  This      Pointer to the EFI_SPI_PROTOCOL instance.\r
\r
Returns:\r
\r
  EFI_SUCCESS             Lock operation succeed.\r
  EFI_DEVICE_ERROR        Device error, operation failed.\r
  EFI_ACCESS_DENIED       The interface has already been locked.\r
\r
--*/\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SPI_EXECUTE) (\r
  IN     EFI_SPI_PROTOCOL   * This,\r
  IN     UINT8              OpcodeIndex,\r
  IN     UINT8              PrefixOpcodeIndex,\r
  IN     BOOLEAN            DataCycle,\r
  IN     BOOLEAN            Atomic,\r
  IN     BOOLEAN            ShiftOut,\r
  IN     UINTN              Address,\r
  IN     UINT32             DataByteCount,\r
  IN OUT UINT8              *Buffer,\r
  IN     SPI_REGION_TYPE    SpiRegionType\r
  );\r
/*++\r
\r
Routine Description:\r
\r
  Execute SPI commands from the host controller.\r
\r
Arguments:\r
\r
  This                    Pointer to the EFI_SPI_PROTOCOL instance.\r
  OpcodeIndex             Index of the command in the OpCode Menu.\r
  PrefixOpcodeIndex       Index of the first command to run when in an atomic cycle sequence.\r
  DataCycle               TRUE if the SPI cycle contains data\r
  Atomic                  TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
  ShiftOut                If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
  Address                 In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
                          Region, this value specifies the offset from the Region Base; for BIOS Region,\r
                          this value specifies the offset from the start of the BIOS Image. In Non\r
                          Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
                          Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
                          Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
                          supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
                          the flash (in Non Descriptor Mode)\r
  DataByteCount           Number of bytes in the data portion of the SPI cycle.\r
  Buffer                  Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.\r
  SpiRegionType           SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
                          EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
                          Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
                          and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
                          to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
\r
Returns:\r
\r
  EFI_SUCCESS             Command succeed.\r
  EFI_INVALID_PARAMETER   The parameters specified are not valid.\r
  EFI_UNSUPPORTED         Command not supported.\r
  EFI_DEVICE_ERROR        Device error, command aborts abnormally.\r
\r
--*/\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SPI_INFO) (\r
  IN EFI_SPI_PROTOCOL     *This,\r
  OUT SPI_INIT_INFO      **InitInfoPtr\r
  );\r
/*++\r
\r
Routine Description:\r
\r
  Return info about SPI host controller, to help callers usage of Execute\r
  service.\r
\r
  If 0xff is returned as an opcode index in init info struct\r
  then device does not support the operation.\r
\r
Arguments:\r
\r
  This                    Pointer to the EFI_SPI_PROTOCOL instance.\r
  InitInfoPtr             Pointer to init info written to this memory location.\r
\r
Returns:\r
\r
  EFI_SUCCESS             Information returned.\r
  EFI_INVALID_PARAMETER   Invalid parameter.\r
  EFI_NOT_READY           Required resources not setup.\r
  Others                  Unexpected error happened.\r
\r
--*/\r
\r
//\r
// Protocol definition\r
//\r
struct _EFI_SPI_PROTOCOL {\r
  EFI_SPI_INIT    Init;\r
  EFI_SPI_LOCK    Lock;\r
  EFI_SPI_EXECUTE Execute;\r
  EFI_SPI_INFO    Info;\r
};\r
\r
#endif\r
Commit	Line	Data
9b6bbcdb MK	1	/** @file\r
	2	This file defines the EFI SPI Protocol which implements the\r
	3	Intel(R) ICH SPI Host Controller Compatibility Interface.\r
	4	\r
	5	Copyright (c) 2013-2015 Intel Corporation.\r
	6	\r
c9f231d0	7	SPDX-License-Identifier: BSD-2-Clause-Patent\r
9b6bbcdb MK	8	\r
	9	\r
	10	**/\r
	11	#ifndef _SPI_H_\r
	12	#define _SPI_H_\r
	13	\r
	14	//\r
	15	// Define the SPI protocol GUID\r
	16	//\r
	17	// EDK and EDKII have different GUID formats\r
	18	//\r
	19	#if !defined(EDK_RELEASE_VERSION) \|\| (EDK_RELEASE_VERSION < 0x00020000)\r
	20	#define EFI_SPI_PROTOCOL_GUID \\r
	21	{ \\r
	22	0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
	23	}\r
	24	#define EFI_SMM_SPI_PROTOCOL_GUID \\r
	25	{ \\r
	26	0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
	27	}\r
	28	#else\r
	29	#define EFI_SPI_PROTOCOL_GUID \\r
	30	{ \\r
	31	0x1156efc6, 0xea32, 0x4396, \\r
	32	{ \\r
	33	0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
	34	} \\r
	35	}\r
	36	#define EFI_SMM_SPI_PROTOCOL_GUID \\r
	37	{ \\r
	38	0xD9072C35, 0xEB8F, 0x43ad, \\r
	39	{ \\r
	40	0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
	41	} \\r
	42	}\r
	43	#endif\r
	44	//\r
	45	// Extern the GUID for protocol users.\r
	46	//\r
	47	extern EFI_GUID gEfiSpiProtocolGuid;\r
	48	extern EFI_GUID gEfiSmmSpiProtocolGuid;\r
	49	\r
	50	//\r
	51	// Forward reference for ANSI C compatibility\r
	52	//\r
	53	typedef struct _EFI_SPI_PROTOCOL EFI_SPI_PROTOCOL;\r
	54	\r
	55	//\r
	56	// SPI protocol data structures and definitions\r
	57	//\r
	58	//\r
	59	// Number of Prefix Opcodes allowed on the SPI interface\r
	60	//\r
	61	#define SPI_NUM_PREFIX_OPCODE 2\r
	62	\r
	63	//\r
	64	// Number of Opcodes in the Opcode Menu\r
	65	//\r
	66	#define SPI_NUM_OPCODE 8\r
	67	\r
	68	#ifdef SERVER_BIOS_FLAG\r
	69	//\r
	70	// SPI default opcode slots\r
	71	//\r
72	#define SPI_OPCODE_JEDEC_ID_INDEX 0\r
73	#endif // SERVER_BIOS_FLAG\r
74	\r
75	//\r
76	// Opcode Type\r
77	// EnumSpiOpcodeCommand: Command without address\r
78	// EnumSpiOpcodeRead: Read with address\r
79	// EnumSpiOpcodeWrite: Write with address\r
80	//\r
81	typedef enum {\r
82	EnumSpiOpcodeReadNoAddr,\r
83	EnumSpiOpcodeWriteNoAddr,\r
84	EnumSpiOpcodeRead,\r
85	EnumSpiOpcodeWrite,\r
86	EnumSpiOpcodeMax\r
87	} SPI_OPCODE_TYPE;\r
88	\r
89	typedef enum {\r
90	EnumSpiCycle20MHz,\r
91	EnumSpiCycle33MHz,\r
92	EnumSpiCycle66MHz, // not supported by PCH\r
93	EnumSpiCycle50MHz,\r
94	EnumSpiCycleMax\r
95	} SPI_CYCLE_FREQUENCY;\r
96	\r
97	typedef enum {\r
98	EnumSpiRegionAll,\r
99	EnumSpiRegionBios,\r
100	EnumSpiRegionMe,\r
101	EnumSpiRegionGbE,\r
102	EnumSpiRegionDescriptor,\r
103	EnumSpiRegionPlatformData,\r
104	EnumSpiRegionMax\r
105	} SPI_REGION_TYPE;\r
106	\r
107	//\r
108	// Hardware Sequencing required operations (as listed in CougarPoint EDS Table 5-55: "Hardware\r
109	// Sequencing Commands and Opcode Requirements"\r
110	//\r
111	typedef enum {\r
112	EnumSpiOperationWriteStatus,\r
113	EnumSpiOperationProgramData_1_Byte,\r
114	EnumSpiOperationProgramData_64_Byte,\r
115	EnumSpiOperationReadData,\r
116	EnumSpiOperationWriteDisable,\r
117	EnumSpiOperationReadStatus,\r
118	EnumSpiOperationWriteEnable,\r
119	EnumSpiOperationFastRead,\r
120	EnumSpiOperationEnableWriteStatus,\r
121	EnumSpiOperationErase_256_Byte,\r
122	EnumSpiOperationErase_4K_Byte,\r
123	EnumSpiOperationErase_8K_Byte,\r
124	EnumSpiOperationErase_64K_Byte,\r
125	EnumSpiOperationFullChipErase,\r
126	EnumSpiOperationJedecId,\r
127	EnumSpiOperationDualOutputFastRead,\r
128	EnumSpiOperationDiscoveryParameters,\r
129	EnumSpiOperationOther,\r
130	EnumSpiOperationMax\r
131	} SPI_OPERATION;\r
132	\r
133	//\r
134	// Opcode menu entries\r
135	// Type Operation Type (value to be programmed to the OPTYPE register)\r
136	// Code The opcode (value to be programmed to the OPMENU register)\r
137	// Frequency The expected frequency to be used (value to be programmed to the SSFC\r
138	// Register)\r
139	// Operation Which Hardware Sequencing required operation this opcode respoinds to.\r
140	// The required operations are listed in EDS Table 5-55: "Hardware\r
141	// Sequencing Commands and Opcode Requirements"\r
142	// If the opcode does not corresponds to any operation listed, use\r
143	// EnumSpiOperationOther\r
144	//\r
145	typedef struct _SPI_OPCODE_MENU_ENTRY {\r
146	SPI_OPCODE_TYPE Type;\r
147	UINT8 Code;\r
148	SPI_CYCLE_FREQUENCY Frequency;\r
149	SPI_OPERATION Operation;\r
150	} SPI_OPCODE_MENU_ENTRY;\r
151	\r
152	//\r
153	// Initialization data table loaded to the SPI host controller\r
154	// VendorId Vendor ID of the SPI device\r
155	// DeviceId0 Device ID0 of the SPI device\r
156	// DeviceId1 Device ID1 of the SPI device\r
157	// PrefixOpcode Prefix opcodes which are loaded into the SPI host controller\r
158	// OpcodeMenu Opcodes which are loaded into the SPI host controller Opcode Menu\r
159	// BiosStartOffset The offset of the start of the BIOS image relative to the flash device.\r
160	// Please note this is a Flash Linear Address, NOT a memory space address.\r
161	// This value is platform specific and depends on the system flash map.\r
162	// This value is only used on non Descriptor mode.\r
163	// BiosSize The the BIOS Image size in flash. This value is platform specific\r
164	// and depends on the system flash map. Please note BIOS Image size may\r
165	// be smaller than BIOS Region size (in Descriptor Mode) or the flash size\r
166	// (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be\r
167	// placed at the top end of the BIOS Region (in Descriptor Mode) or the flash\r
168	// (in Non Descriptor Mode)\r
169	//\r
170	typedef struct _SPI_INIT_TABLE {\r
171	UINT8 VendorId;\r
172	UINT8 DeviceId0;\r
173	UINT8 DeviceId1;\r
174	UINT8 PrefixOpcode[SPI_NUM_PREFIX_OPCODE];\r
175	SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE];\r
176	UINTN BiosStartOffset;\r
177	UINTN BiosSize;\r
178	} SPI_INIT_TABLE;\r
179	\r
180	//\r
181	// Public Info struct to show current initialized state of the spi interface.\r
182	// OpcodeIndex must be less then SPI_NUM_OPCODE for operation to be supported.\r
183	//\r
184	typedef struct _SPI_INIT_INFO {\r
185	SPI_INIT_TABLE *InitTable;\r
186	UINT8 JedecIdOpcodeIndex;\r
187	UINT8 OtherOpcodeIndex;\r
188	UINT8 WriteStatusOpcodeIndex;\r
189	UINT8 ProgramOpcodeIndex;\r
190	UINT8 ReadOpcodeIndex;\r
191	UINT8 EraseOpcodeIndex;\r
192	UINT8 ReadStatusOpcodeIndex;\r
193	UINT8 FullChipEraseOpcodeIndex;\r
194	} SPI_INIT_INFO;\r
195	\r
196	//\r
197	// Protocol member functions\r
198	//\r
199	\r
200	typedef\r
201	EFI_STATUS\r
202	(EFIAPI *EFI_SPI_INIT) (\r
203	IN EFI_SPI_PROTOCOL * This,\r
204	IN SPI_INIT_TABLE * InitTable\r
205	);\r
206	/*++\r
207	\r
208	Routine Description:\r
209	\r
210	Initializes the host controller to execute SPI commands.\r
211	\r
212	Arguments:\r
213	\r
214	This Pointer to the EFI_SPI_PROTOCOL instance.\r
215	InitTable Pointer to caller-allocated buffer containing the SPI\r
216	interface initialization table.\r
217	\r
218	Returns:\r
219	\r
220	EFI_SUCCESS Opcode initialization on the SPI host controller completed.\r
221	EFI_ACCESS_DENIED The SPI configuration interface is locked.\r
222	EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device.\r
223	EFI_DEVICE_ERROR Device error, operation failed.\r
224	\r
225	--*/\r
226	\r
227	typedef\r
228	EFI_STATUS\r
229	(EFIAPI *EFI_SPI_LOCK) (\r
230	IN EFI_SPI_PROTOCOL * This\r
231	);\r
232	/*++\r
233	\r
234	Routine Description:\r
235	\r
236	Lock the SPI Static Configuration Interface.\r
237	Once locked, the interface is no longer open for configuration changes.\r
238	The lock state automatically clears on next system reset.\r
239	\r
240	Arguments:\r
241	\r
242	This Pointer to the EFI_SPI_PROTOCOL instance.\r
243	\r
244	Returns:\r
245	\r
246	EFI_SUCCESS Lock operation succeed.\r
247	EFI_DEVICE_ERROR Device error, operation failed.\r
248	EFI_ACCESS_DENIED The interface has already been locked.\r
249	\r
250	--*/\r
251	\r
252	typedef\r
253	EFI_STATUS\r
254	(EFIAPI *EFI_SPI_EXECUTE) (\r
255	IN EFI_SPI_PROTOCOL * This,\r
256	IN UINT8 OpcodeIndex,\r
257	IN UINT8 PrefixOpcodeIndex,\r
258	IN BOOLEAN DataCycle,\r
259	IN BOOLEAN Atomic,\r
260	IN BOOLEAN ShiftOut,\r
261	IN UINTN Address,\r
262	IN UINT32 DataByteCount,\r
263	IN OUT UINT8 *Buffer,\r
264	IN SPI_REGION_TYPE SpiRegionType\r
265	);\r
266	/*++\r
267	\r
268	Routine Description:\r
269	\r
270	Execute SPI commands from the host controller.\r
271	\r
272	Arguments:\r
273	\r
274	This Pointer to the EFI_SPI_PROTOCOL instance.\r
275	OpcodeIndex Index of the command in the OpCode Menu.\r
276	PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.\r
277	DataCycle TRUE if the SPI cycle contains data\r
278	Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
279	ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
280	Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
281	Region, this value specifies the offset from the Region Base; for BIOS Region,\r
282	this value specifies the offset from the start of the BIOS Image. In Non\r
283	Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
284	Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
285	Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
286	supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
287	the flash (in Non Descriptor Mode)\r
288	DataByteCount Number of bytes in the data portion of the SPI cycle.\r
289	Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.\r
290	SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
291	EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
292	Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
293	and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
294	to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
295	\r
296	Returns:\r
297	\r
298	EFI_SUCCESS Command succeed.\r
299	EFI_INVALID_PARAMETER The parameters specified are not valid.\r
300	EFI_UNSUPPORTED Command not supported.\r
301	EFI_DEVICE_ERROR Device error, command aborts abnormally.\r
302	\r
303	--*/\r
304	\r
305	typedef\r
306	EFI_STATUS\r
307	(EFIAPI *EFI_SPI_INFO) (\r
308	IN EFI_SPI_PROTOCOL *This,\r
309	OUT SPI_INIT_INFO **InitInfoPtr\r
310	);\r
311	/*++\r
312	\r
313	Routine Description:\r
314	\r
315	Return info about SPI host controller, to help callers usage of Execute\r
316	service.\r
317	\r
318	If 0xff is returned as an opcode index in init info struct\r
319	then device does not support the operation.\r
320	\r
321	Arguments:\r
322	\r
323	This Pointer to the EFI_SPI_PROTOCOL instance.\r
324	InitInfoPtr Pointer to init info written to this memory location.\r
325	\r
326	Returns:\r
327	\r
328	EFI_SUCCESS Information returned.\r
329	EFI_INVALID_PARAMETER Invalid parameter.\r
330	EFI_NOT_READY Required resources not setup.\r
331	Others Unexpected error happened.\r
332	\r
333	--*/\r
334	\r
335	//\r
336	// Protocol definition\r
337	//\r
338	struct _EFI_SPI_PROTOCOL {\r
339	EFI_SPI_INIT Init;\r
340	EFI_SPI_LOCK Lock;\r
341	EFI_SPI_EXECUTE Execute;\r
342	EFI_SPI_INFO Info;\r
343	};\r
344	\r
345	#endif\r