QuarkSocPkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Library / QNCAccessLib / QNCAccessLib.c

/** @file\r
Common Lib function for QNC internal network access.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <Uefi.h>\r
\r
#include <IntelQNCRegs.h>\r
#include <Library/QNCAccessLib.h>\r
#include <Library/DebugLib.h>\r
#include <IndustryStandard/Pci22.h>\r
\r
UINT32\r
EFIAPI\r
QNCPortRead(\r
  UINT8 Port,\r
  UINT32 RegAddress\r
  )\r
{\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MEA) = (RegAddress & 0xFFFFFF00);\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = MESSAGE_READ_DW (Port, RegAddress);\r
  return McD0PciCfg32 (QNC_ACCESS_PORT_MDR);\r
}\r
\r
VOID\r
EFIAPI\r
QNCPortWrite (\r
  UINT8 Port,\r
  UINT32 RegAddress,\r
  UINT32 WriteValue\r
  )\r
{\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MDR) = WriteValue;\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MEA) = (RegAddress & 0xFFFFFF00);\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = MESSAGE_WRITE_DW (Port, RegAddress);\r
}\r
\r
UINT32\r
EFIAPI\r
QNCAltPortRead (\r
  UINT8 Port,\r
  UINT32 RegAddress\r
  )\r
{\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MEA) = (RegAddress & 0xFFFFFF00);\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = ALT_MESSAGE_READ_DW (Port, RegAddress);\r
  return McD0PciCfg32 (QNC_ACCESS_PORT_MDR);\r
}\r
\r
VOID\r
EFIAPI\r
QNCAltPortWrite (\r
  UINT8 Port,\r
  UINT32 RegAddress,\r
  UINT32 WriteValue\r
  )\r
{\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MDR) = WriteValue;\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MEA) = (RegAddress & 0xFFFFFF00);\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = ALT_MESSAGE_WRITE_DW (Port, RegAddress);\r
}\r
\r
UINT32\r
EFIAPI\r
QNCPortIORead(\r
  UINT8 Port,\r
  UINT32 RegAddress\r
  )\r
{\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MEA) = (RegAddress & 0xFFFFFF00);\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = MESSAGE_IO_READ_DW (Port, RegAddress);\r
  return McD0PciCfg32 (QNC_ACCESS_PORT_MDR);\r
}\r
\r
VOID\r
EFIAPI\r
QNCPortIOWrite (\r
  UINT8 Port,\r
  UINT32 RegAddress,\r
  UINT32 WriteValue\r
  )\r
{\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MDR) = WriteValue;\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MEA) = (RegAddress & 0xFFFFFF00);\r
  McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = MESSAGE_IO_WRITE_DW (Port, RegAddress);\r
}\r
\r
RETURN_STATUS\r
EFIAPI\r
QNCMmIoWrite (\r
  UINT32             MmIoAddress,\r
  QNC_MEM_IO_WIDTH    Width,\r
  UINT32             DataNumber,\r
  VOID               *pData\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  This is for the special consideration for QNC MMIO write, as required by FWG, a reading must be performed after MMIO writing\r
to ensure the expected write is processed and data is flushed into chipset\r
\r
Arguments:\r
\r
  Row -- row number to be cleared ( start from 1 )\r
\r
Returns:\r
\r
  EFI_SUCCESS\r
\r
--*/\r
{\r
  RETURN_STATUS  Status;\r
  UINTN          Index;\r
\r
  Status = RETURN_SUCCESS;\r
\r
  for (Index =0; Index < DataNumber; Index++) {\r
    switch (Width) {\r
      case QNCMmioWidthUint8:\r
        QNCMmio8 (MmIoAddress, 0) = ((UINT8 *)pData)[Index];\r
        if (QNCMmio8 (MmIoAddress, 0) != ((UINT8*)pData)[Index]) {\r
          Status = RETURN_DEVICE_ERROR;\r
          break;\r
        }\r
        break;\r
\r
      case QNCMmioWidthUint16:\r
        QNCMmio16 (MmIoAddress, 0) = ((UINT16 *)pData)[Index];\r
        if (QNCMmio16 (MmIoAddress, 0) != ((UINT16 *)pData)[Index]) {\r
          Status = RETURN_DEVICE_ERROR;\r
          break;\r
        }\r
        break;\r
\r
      case QNCMmioWidthUint32:\r
        QNCMmio32 (MmIoAddress, 0) = ((UINT32 *)pData)[Index];\r
        if (QNCMmio32 (MmIoAddress, 0) != ((UINT32 *)pData)[Index]) {\r
          Status = RETURN_DEVICE_ERROR;\r
          break;\r
        }\r
        break;\r
\r
      case QNCMmioWidthUint64:\r
        QNCMmio64 (MmIoAddress, 0) = ((UINT64 *)pData)[Index];\r
        if (QNCMmio64 (MmIoAddress, 0) != ((UINT64 *)pData)[Index]) {\r
          Status = RETURN_DEVICE_ERROR;\r
          break;\r
        }\r
        break;\r
\r
      default:\r
        break;\r
    }\r
  }\r
\r
  return Status;\r
}\r
\r
UINT32\r
EFIAPI\r
QncHsmmcRead (\r
  VOID\r
  )\r
{\r
  return QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HSMMC);\r
}\r
\r
VOID\r
EFIAPI\r
QncHsmmcWrite (\r
  UINT32 WriteValue\r
  )\r
{\r
  UINT16  DeviceId;\r
  UINT32  Data32;\r
\r
  //\r
  // Check what Soc we are running on (read Host bridge DeviceId)\r
  //\r
  DeviceId = QNCMmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);\r
\r
  if (DeviceId == QUARK2_MC_DEVICE_ID) {\r
    //\r
    // Disable HSMMC configuration\r
    //\r
    Data32 = QncHsmmcRead ();\r
    Data32 &= ~SMM_CTL_EN;\r
    QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HSMMC, Data32);\r
\r
    //\r
    // Validate HSMMC configuration is disabled\r
    //\r
    Data32 = QncHsmmcRead ();\r
    ASSERT((Data32 & SMM_CTL_EN) == 0);\r
\r
    //\r
    // Enable HSMMC configuration\r
    //\r
    WriteValue |= SMM_CTL_EN;\r
  }\r
\r
  //\r
  // Write the register value\r
  //\r
  QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HSMMC, WriteValue);\r
\r
  if (DeviceId == QUARK2_MC_DEVICE_ID) {\r
    //\r
    // Validate HSMMC configuration is enabled\r
    //\r
    Data32 = QncHsmmcRead ();\r
    ASSERT((Data32 & SMM_CTL_EN) != 0);\r
  }\r
}\r
\r
VOID\r
EFIAPI\r
QncImrWrite (\r
  UINT32 ImrBaseOffset,\r
  UINT32 ImrLow,\r
  UINT32 ImrHigh,\r
  UINT32 ImrReadMask,\r
  UINT32 ImrWriteMask\r
  )\r
{\r
  UINT16  DeviceId;\r
  UINT32  Data32;\r
\r
  //\r
  // Check what Soc we are running on (read Host bridge DeviceId)\r
  //\r
  DeviceId = QNCMmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);\r
\r
  //\r
  // Disable IMR protection\r
  //\r
  if (DeviceId == QUARK2_MC_DEVICE_ID) {\r
    //\r
    // Disable IMR protection\r
    //\r
    Data32 = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXL);\r
    Data32 &= ~IMR_EN;\r
    QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXL, Data32);\r
\r
    //\r
    // Validate IMR protection is disabled\r
    //\r
    Data32 = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXL);\r
    ASSERT((Data32 & IMR_EN) == 0);\r
\r
    //\r
    // Update the IMR (IMRXL must be last as it may enable IMR violation checking)\r
    //\r
    QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXRM, ImrReadMask);\r
    QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXWM, ImrWriteMask);\r
    QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXH, ImrHigh);\r
    QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXL, ImrLow);\r
\r
    //\r
    // Validate IMR protection is enabled/disabled\r
    //\r
    Data32 = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXL);\r
    ASSERT((Data32 & IMR_EN) == (ImrLow & IMR_EN));\r
  } else {\r
    //\r
    // Disable IMR protection (allow all access)\r
    //\r
    QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXRM, (UINT32)IMRX_ALL_ACCESS);\r
    QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXWM, (UINT32)IMRX_ALL_ACCESS);\r
\r
    //\r
    // Update the IMR (IMRXRM/IMRXWM must be last as they restrict IMR access)\r
    //\r
    QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXL, (ImrLow & ~IMR_EN));\r
    QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXH, ImrHigh);\r
    QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXRM, ImrReadMask);\r
    QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXWM, ImrWriteMask);\r
  }\r
}\r
\r
VOID\r
EFIAPI\r
QncIClkAndThenOr (\r
  UINT32 RegAddress,\r
  UINT32 AndValue,\r
  UINT32 OrValue\r
  )\r
{\r
  UINT32 RegValue;\r
  //\r
  // Whenever an iCLK SB register (Endpoint 32h) is being programmed the access\r
  // should always consist of a READ from the address followed by 2 identical\r
  // WRITEs to that address.\r
  //\r
  RegValue = QNCAltPortRead (QUARK_ICLK_SB_PORT_ID, RegAddress);\r
  RegValue &= AndValue;\r
  RegValue |= OrValue;\r
  QNCAltPortWrite (QUARK_ICLK_SB_PORT_ID, RegAddress, RegValue);\r
  QNCAltPortWrite (QUARK_ICLK_SB_PORT_ID, RegAddress, RegValue);\r
}\r
\r
VOID\r
EFIAPI\r
QncIClkOr (\r
  UINT32 RegAddress,\r
  UINT32 OrValue\r
  )\r
{\r
  UINT32 RegValue;\r
  //\r
  // Whenever an iCLK SB register (Endpoint 32h) is being programmed the access\r
  // should always consist of a READ from the address followed by 2 identical\r
  // WRITEs to that address.\r
  //\r
  RegValue = QNCAltPortRead (QUARK_ICLK_SB_PORT_ID, RegAddress);\r
  RegValue |= OrValue;\r
  QNCAltPortWrite (QUARK_ICLK_SB_PORT_ID, RegAddress, RegValue);\r
  QNCAltPortWrite (QUARK_ICLK_SB_PORT_ID, RegAddress, RegValue);\r
}\r