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ArmPkg/CompilerIntrinsicsLib: Add uread, uwrite GCC assembly sources
[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / MemoryInit / Pei / gen5_iosf_sb_definitions.h
CommitLineData
9b6bbcdb
MK		 1/************************************************************************\r
2 *\r
3 * Copyright (c) 2013-2015 Intel Corporation.\r
4 *\r
c9f231d0 5* SPDX-License-Identifier: BSD-2-Clause-Patent\r
9b6bbcdb
MK		 6 *\r
7 * MCU register definition\r
8 *\r
9 ************************************************************************/\r
10#ifndef __IOSF_DEFINITIONS_H\r
11#define __IOSF_DEFINITIONS_H\r
12\r
13// Define each of the IOSF-SB register offsets used by MRC.\r
14\r
15\r
16// MCU registers (DUNIT):\r
17// ====\r
18#define DRP 0x0000\r
19#define DTR0 0x0001\r
20#define DTR1 0x0002\r
21#define DTR2 0x0003\r
22#define DTR3 0x0004\r
23#define DTR4 0x0005\r
24#define DPMC0 0x0006\r
25#define DPMC1 0x0007\r
26#define DRFC 0x0008\r
27#define DSCH 0x0009\r
28#define DCAL 0x000A\r
29#define DRMC 0x000B\r
30#define PMSTS 0x000C\r
31#define DCO 0x000F\r
32#define DSTAT 0x0020\r
33#define DECCCTRL 0x0060\r
34#define DFUSESTAT 0x0070\r
35#define SCRMSEED 0x0080\r
36#define SCRMLO 0x0081\r
37#define SCRMHI 0x0082\r
38\r
39#define MCU_CH_OFFSET 0x0040\r
40#define MCU_RK_OFFSET 0x0020\r
41\r
42////\r
43//\r
44// BEGIN DUnit register definition\r
45//\r
46#pragma pack(1)\r
47typedef union {\r
48 uint32_t raw;\r
49 struct {\r
50 uint32_t rank0Enabled :1; /**< BIT [0] Rank 0 Enable */\r
51 uint32_t rank1Enabled :1; /**< BIT [1] Rank 1 Enable */\r
52 uint32_t reserved0 :2;\r
53 uint32_t dimm0DevWidth :2; /**< BIT [5:4] DIMM 0 Device Width (Rank0&1) */\r
54 uint32_t dimm0DevDensity :2; /**< BIT [7:6] DIMM 0 Device Density */\r
55 uint32_t reserved1 :1;\r
56 uint32_t dimm1DevWidth :2; /**< BIT [10:9] DIMM 1 Device Width (Rank2&3) */\r
57 uint32_t dimm1DevDensity :2; /**< BIT [12:11] DIMM 1 Device Density */\r
58 uint32_t split64 :1; /**< BIT [13] split 64B transactions */\r
59 uint32_t addressMap :2; /**< BIT [15:14] Address Map select */\r
60 uint32_t reserved3 :14;\r
61 uint32_t mode32 :1; /**< BIT [30] Select 32bit data interface*/\r
62 uint32_t reserved4 :1;\r
63 } field;\r
64} RegDRP; /**< DRAM Rank Population and Interface Register */\r
65#pragma pack()\r
66\r
67\r
68#pragma pack(1)\r
69typedef union {\r
70 uint32_t raw;\r
71 struct {\r
72 uint32_t dramFrequency :2; /**< DRAM Frequency (000=800,001=1033,010=1333) */\r
73 uint32_t reserved1 :2;\r
74 uint32_t tRP :4; /**< bit [7:4] Precharge to Activate Delay */\r
75 uint32_t tRCD :4; /**< bit [11:8] Activate to CAS Delay */\r
76 uint32_t tCL :3; /**< bit [14:12] CAS Latency */\r
77 uint32_t reserved4 :1;\r
78 uint32_t tXS :1; /**< SRX Delay */\r
79 uint32_t reserved5 :1;\r
80 uint32_t tXSDLL :1; /**< SRX To DLL Delay */\r
81 uint32_t reserved6 :1;\r
82 uint32_t tZQCS :1; /**< bit [20] ZQTS recovery Latncy */\r
83 uint32_t reserved7 :1;\r
84 uint32_t tZQCL :1; /**< bit [22] ZQCL recovery Latncy */\r
85 uint32_t reserved8 :1;\r
86 uint32_t pmeDelay :2; /**< bit [25:24] Power mode entry delay */\r
87 uint32_t reserved9 :2;\r
88 uint32_t CKEDLY :4; /**< bit [31:28] */\r
89 } field;\r
90} RegDTR0; /**< DRAM Timing Register 0 */\r
91#pragma pack()\r
92\r
93#pragma pack(1)\r
94typedef union {\r
95 uint32_t raw;\r
96 struct {\r
97 uint32_t tWCL :3; /**< bit [2:0] CAS Write Latency */\r
98 uint32_t reserved1 :1;\r
99 uint32_t tCMD :2; /**< bit [5:4] Command transport duration */\r
100 uint32_t reserved2 :2;\r
101 uint32_t tWTP :4; /**< Write to Precharge */\r
102 uint32_t tCCD :2; /**< CAS to CAS delay */\r
103 uint32_t reserved4 :2;\r
104 uint32_t tFAW :4; /**< Four bank Activation Window*/\r
105 uint32_t tRAS :4; /**< Row Activation Period: */\r
106 uint32_t tRRD :2; /**<Row activation to Row activation Delay */\r
107 uint32_t reserved5 :2;\r
108 uint32_t tRTP :3; /**<Read to Precharge Delay */\r
109 uint32_t reserved6 :1;\r
110 } field;\r
111} RegDTR1; /**< DRAM Timing Register 1 */\r
112#pragma pack()\r
113\r
114#pragma pack(1)\r
115typedef union {\r
116 uint32_t raw;\r
117 struct {\r
118 uint32_t tRRDR :3; /**< RD to RD from different ranks, same DIMM */\r
119 uint32_t reserved1 :5;\r
120 uint32_t tWWDR :3; /**< WR to WR from different ranks, same DIMM. */\r
121 uint32_t reserved3 :5;\r
122 uint32_t tRWDR :4; /**< bit [19:16] RD to WR from different ranks, same DIMM. */\r
123 uint32_t reserved5 :12;\r
124 } field;\r
125} RegDTR2; /**< DRAM Timing Register 2 */\r
126#pragma pack()\r
127\r
128#pragma pack(1)\r
129typedef union {\r
130 uint32_t raw;\r
131 struct {\r
132 uint32_t tWRDR :3; /**< WR to RD from different ranks, same DIMM. */\r
133 uint32_t reserved1 :1;\r
134 uint32_t tWRDD :3; /**< WR to RD from different DIMM. */\r
135 uint32_t reserved2 :1;\r
136 uint32_t tRWSR :4; /**< RD to WR Same Rank. */\r
137 uint32_t reserved3 :1;\r
138 uint32_t tWRSR :4; /**< WR to RD Same Rank. */\r
139 uint32_t reserved4 :5;\r
140 uint32_t tXP :2; /**< Time from CKE set on to any command. */\r
141 uint32_t PWD_DLY :4; /**< Extended Power-Down Delay. */\r
142 uint32_t EnDeRate :1;\r
143 uint32_t DeRateOvr :1;\r
144 uint32_t DeRateStat :1;\r
145 uint32_t reserved5 :1;\r
146 } field;\r
147} RegDTR3; /**< DRAM Timing Register 3 */\r
148#pragma pack()\r
149\r
150\r
151#pragma pack(1)\r
152typedef union {\r
153 uint32_t raw;\r
154 struct {\r
155 uint32_t WRODTSTRT :2; /**< WR command to ODT assert delay */\r
156 uint32_t reserved1 :2;\r
157 uint32_t WRODTSTOP :3; /**< Write command to ODT de-assert delay. */\r
158 uint32_t reserved2 :1;\r
159 uint32_t RDODTSTRT :3; /**< Read command to ODT assert delay */\r
160 uint32_t reserved3 :1;\r
161 uint32_t RDODTSTOP :3; /**< Read command to ODT de-assert delay */\r
162 uint32_t ODTDIS :1; /**< ODT disable */\r
163 uint32_t TRGSTRDIS :1; /**< Write target rank is not stretched */\r
164 uint32_t RDODTDIS :1; /**< Disable Read ODT */\r
165 uint32_t WRBODTDIS :1; /**< Disable Write ODT */\r
166 uint32_t reserved5 :13;\r
167 } field;\r
168} RegDTR4; /**< DRAM Timing Register 3 */\r
169#pragma pack()\r
170\r
171#pragma pack(1)\r
172typedef union {\r
173 uint32_t raw;\r
174 struct {\r
175 uint32_t SREntryDelay :8; /**< Self-Refresh Entry Delay: */\r
176 uint32_t powerModeOpCode :5; /**< SPID Power Mode Opcode */\r
177 uint32_t reserved1 :3;\r
178 uint32_t PCLSTO :3; /**< Page Close Timeout Period */\r
179 uint32_t reserved2 :1;\r
180 uint32_t PCLSWKOK :1; /**< Wake Allowed For Page Close Timeout */\r
181 uint32_t PREAPWDEN :1; /**< Send Precharge All to rank before entering Power-Down mode. */\r
182 uint32_t reserved3 :1;\r
183 uint32_t DYNSREN :1; /**< Dynamic Self-Refresh */\r
184 uint32_t CLKGTDIS :1; /**< Clock Gating Disabled*/\r
185 uint32_t DISPWRDN :1; /**< Disable Power Down*/\r
186 uint32_t reserved4 :2;\r
187 uint32_t REUTCLKGTDIS :1;\r
188 uint32_t ENPHYCLKGATE :1;\r
189 uint32_t reserved5 :2;\r
190 } field;\r
191} RegDPMC0; /**< DRAM Power Management Control Register 0 */\r
192#pragma pack()\r
193\r
194#pragma pack(1)\r
195typedef union {\r
196 uint32_t raw;\r
197 struct {\r
198 uint32_t REFWMLO :4; /**< Refresh Opportunistic Watermark */\r
199 uint32_t REFWMHI :4; /**< Refresh High Watermark*/\r
200 uint32_t REFWMPNC :4; /**< Refresh Panic Watermark */\r
201 uint32_t tREFI :3; /**< bit [14:12] Refresh Period */\r
202 uint32_t reserved1 :1;\r
203 uint32_t REFCNTMAX :2; /**< Refresh Max tREFI Interval */\r
204 uint32_t reserved2 :2;\r
205 uint32_t REFSKEWDIS :1; /**< tREFI counters */\r
206 uint32_t REFDBTCLR :1;\r
207 uint32_t reserved3 :2;\r
208 uint32_t CuRefRate :3;\r
209 uint32_t DisRefBW :1;\r
210 uint32_t reserved4 :4;\r
211 } field;\r
212} RegDRCF; /**< DRAM Refresh Control Register*/\r
213#pragma pack()\r
214\r
215#pragma pack(1)\r
216typedef union {\r
217 uint32_t raw;\r
218 struct {\r
219 uint32_t reserved1 :8;\r
220 uint32_t ZQCINT :3; /**< ZQ Calibration Short Interval: */\r
221 uint32_t reserved2 :1;\r
222 uint32_t SRXZQCL :2; /** < ZQ Calibration Length */\r
223 uint32_t ZQCalType :1;\r
224 uint32_t ZQCalStart :1;\r
225 uint32_t TQPollStart :1;\r
226 uint32_t TQPollRS :2;\r
227 uint32_t reserved3 :5;\r
228 uint32_t MRRData :8; /**< bit[31:24] */\r
229 } field;\r
230} RegDCAL; /**< DRAM Calibration Control*/\r
231#pragma pack()\r
232\r
233#pragma pack(1)\r
234typedef union {\r
235 uint32_t raw;\r
236 struct {\r
237 uint32_t OOOAGETRH :5; /**< Out-of-Order Aging Threshold */\r
238 uint32_t reserved1 :3;\r
239 uint32_t OOODIS :1; /**< Out-of-Order Disable */\r
240 uint32_t OOOST3DIS :1; /**< Out-of-Order Disabled when RequestBD_Status is 3. */\r
241 uint32_t reserved2 :2;\r
242 uint32_t NEWBYPDIS :1;\r
243 uint32_t reserved3 :3;\r
244 uint32_t IPREQMAX :3; /** < Max In-Progress Requests stored in MC */\r
245 uint32_t reserved4 :13;\r
246 } field;\r
247} RegDSCH; /**< DRAM Scheduler Control Register */\r
248#pragma pack()\r
249\r
250#pragma pack(1)\r
251typedef union {\r
252 uint32_t raw;\r
253 struct {\r
254 uint32_t DRPLOCK :1; /**< DRP lock bit */\r
255 uint32_t reserved1 :7;\r
256 uint32_t REUTLOCK :1; /**< REUT lock bit */\r
257 uint32_t reserved2 :19;\r
258 uint32_t PMICTL :1; /**< PRI Control Select: 0-memory_manager, 1-hte */\r
259 uint32_t PMIDIS :1; /**< PMIDIS Should be set is using IOSF-SB RW */\r
260 uint32_t DIOIC :1; /**< DDRIO initialization is complete */\r
261 uint32_t IC :1; /**< D-unit Initialization Complete */\r
262 } field;\r
263} RegDCO; /**< DRAM Controller Operation Register*/\r
264#pragma pack()\r
265\r
266#pragma pack(1)\r
267typedef union {\r
268 uint32_t raw;\r
269 struct {\r
270 uint32_t SBEEN :1; /**< Enable Single Bit Error Detection and Correction */\r
271 uint32_t DBEEN :1; /**< Enable Double Bit Error Detection */\r
272 uint32_t CBOEN :3; /**< Enable ECC Check Bits Override */\r
273 uint32_t SYNSEL :2; /**< ECC Syndrome Bits Select for Observation */\r
274 uint32_t CLRSBECNT :1; /**< Clear ECC Single Bit Error Count */\r
275 uint32_t CBOV :8; /**< ECC Check Bits Override Value */\r
276 uint32_t reserved1 :1; /**< */\r
277 uint32_t ENCBGEN :1; /**< Enable Generation of ECC Check Bits */\r
278 uint32_t ENCBGESWIZ :1; /**< Enable Same Chip ECC Byte Lane Swizzle */\r
279\r
280 } field;\r
281} RegDECCCTRL; /**< DRAM ECC Control Register */\r
282#pragma pack()\r
283\r
284\r
285#pragma pack(1)\r
286typedef union {\r
287 uint32_t raw;\r
288 struct {\r
289 uint32_t FUS_DUN_ECC_DIS :1;\r
290 uint32_t FUS_DUN_MAX_SUPPORTED_MEMORY :3;\r
291 uint32_t FUS_DUN_MAX_DEVDEN :2;\r
292 uint32_t RESERVED1 :1;\r
293 uint32_t FUS_DUN_RANK2_DIS :1;\r
294 uint32_t FUS_DUN_OOO_DIS :1;\r
295 uint32_t FUS_DUN_MEMX8_DIS :1;\r
296 uint32_t FUS_DUN_MEMX16_DIS :1;\r
297 uint32_t RESERVED2 :1;\r
298 uint32_t FUS_DUN_1N_DIS :1;\r
299 uint32_t FUS_DUN_DQ_SCRAMBLER_DIS :1;\r
300 uint32_t RESERVED3 :1;\r
301 uint32_t FUS_DUN_32BIT_DRAM_IFC :1;\r
302 } field;\r
303} RegDFUSESTAT;\r
304#pragma pack()\r
305\r
306//\r
307// END DUnit register definition\r
308//\r
309////\r
310\r
311\r
312\r
313////\r
314//\r
315// DRAM Initialization Structures used in JEDEC Message Bus Commands\r
316//\r
317\r
318#pragma pack(1)\r
319typedef union {\r
320 uint32_t raw;\r
321 struct {\r
322 unsigned command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */\r
323 unsigned bankAddress :3; /**< Bank Address (BA[2:0]) */\r
324 unsigned BL :2; /**< Burst Length, CDV:1*/\r
325 unsigned CL :1; /**< CL Reserved CDV:0 */\r
326 unsigned RBT :1; /**< Read Burst Type */\r
327 unsigned casLatency :3; /**< cas Latency */\r
328 unsigned TM :1; /**< Test mode */\r
329 unsigned dllReset :1; /**< DLL Reset */\r
330 unsigned writeRecovery :3; /**< Write Recovery for Auto Pre-Charge: 001=2,010=3,011=4,100=5,101=6 */\r
331 unsigned PPD :1; /**< DLL Control for Precharge Power-Down CDV:1 */\r
332 unsigned reserved1 :3;\r
333 unsigned rankSelect :4; /**< Rank Select */\r
334 unsigned reserved2 :6;\r
335 } field;\r
336} DramInitDDR3MRS0; /**< DDR3 Mode Register Set (MRS) Command */\r
337#pragma pack()\r
338\r
339#pragma pack(1)\r
340typedef union {\r
341 uint32_t raw;\r
342 struct {\r
343 unsigned command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */\r
344 unsigned bankAddress :3; /**< Bank Address (BA[2:0]) */\r
345 unsigned dllEnabled :1; /**< CDV=0 */\r
346 unsigned DIC0 :1; /**< Output Driver Impedance Control */\r
347 unsigned rttNom0 :1; /**< RTT_nom[0] */\r
348 unsigned MRC_AL :2; /**< Additive Latency = 0 */\r
349 unsigned DIC1 :1; /**< Reserved */\r
350 unsigned rttNom1 :1; /**< RTT_nom[1] */\r
351 unsigned wlEnabled :1; /**< Write Leveling Enable */\r
352 unsigned reserved1 :1;\r
353 unsigned rttNom2 :1; /** < RTT_nom[2] */\r
354 unsigned reserved2 :1;\r
355 unsigned TDQS :1; /**< TDQS Enable */\r
356 unsigned Qoff :1; /**< Output Buffers Disabled */\r
357 unsigned reserved3 :3;\r
358 unsigned rankSelect :4; /**< Rank Select */\r
359 unsigned reserved4 :6;\r
360 } field;\r
361} DramInitDDR3EMR1; /**< DDR3 Extended Mode Register 1 Set (EMRS1) Command */\r
362#pragma pack()\r
363\r
364#pragma pack(1)\r
365typedef union {\r
366 uint32_t raw;\r
367 struct {\r
368 uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */\r
369 uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */\r
370 uint32_t PASR :3; /**< Partial Array Self-Refresh */\r
371 uint32_t CWL :3; /**< CAS Write Latency */\r
372 uint32_t ASR :1; /**< Auto Self-Refresh */\r
373 uint32_t SRT :1; /**< SR Temperature Range = 0*/\r
374 uint32_t reserved1 :1;\r
375 uint32_t rtt_WR :2; /**< Rtt_WR */\r
376 uint32_t reserved2 :5;\r
377 uint32_t rankSelect :4; /**< Rank Select */\r
378 uint32_t reserved3 :6;\r
379 } field;\r
380} DramInitDDR3EMR2; /**< DDR3 Extended Mode Register 2 Set (EMRS2) Command */\r
381#pragma pack()\r
382\r
383#pragma pack(1)\r
384typedef union {\r
385 uint32_t raw;\r
386 struct {\r
387 uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */\r
388 uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */\r
389 uint32_t MPR_Location :2; /**< MPR Location */\r
390 uint32_t MPR :1; /**< MPR: Multi Purpose Register */\r
391 uint32_t reserved1 :13;\r
392 uint32_t rankSelect :4; /**< Rank Select */\r
393 uint32_t reserved2 :6;\r
394 } field;\r
395} DramInitDDR3EMR3; /**< DDR3 Extended Mode Register 2 Set (EMRS2) Command */\r
396#pragma pack()\r
397\r
398#pragma pack(1)\r
399typedef union {\r
400 uint32_t raw;\r
401 struct {\r
402 uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110 - ZQ Calibration,111-NOP */\r
403 uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */\r
404 uint32_t multAddress :16; /**< Multiplexed Address (MA[14:0]) */\r
405 uint32_t rankSelect :2; /**< Rank Select */\r
406 uint32_t reserved3 :8;\r
407 } field;\r
408} DramInitMisc; /**< Miscellaneous DDRx Initialization Command */\r
409#pragma pack()\r
410\r
411//\r
412// Construct DRAM init command using DramInitXxxx pattern\r
413//\r
414#define DCMD_MRS1(rnk,dat) (0 | ((rnk)<<22) | (1<<3) | ((dat)<<6))\r
415#define DCMD_REF(rnk) (1 | ((rnk)<<22))\r
416#define DCMD_PRE(rnk) (2 | ((rnk)<<22))\r
417#define DCMD_PREA(rnk) (2 | ((rnk)<<22) | (BIT10<<6))\r
418#define DCMD_ACT(rnk,row) (3 | ((rnk)<<22) | ((row)<<6))\r
419#define DCMD_WR(rnk,col) (4 | ((rnk)<<22) | ((col)<<6))\r
420#define DCMD_RD(rnk,col) (5 | ((rnk)<<22) | ((col)<<6))\r
421#define DCMD_ZQCS(rnk) (6 | ((rnk)<<22))\r
422#define DCMD_ZQCL(rnk) (6 | ((rnk)<<22) | (BIT10<<6))\r
423#define DCMD_NOP(rnk) (7 | ((rnk)<<22))\r
424\r
425\r
426\r
427\r
428#define DDR3_EMRS1_DIC_40 (0)\r
429#define DDR3_EMRS1_DIC_34 (1)\r
430\r
431#define DDR3_EMRS2_RTTWR_60 (BIT9)\r
432#define DDR3_EMRS2_RTTWR_120 (BIT10)\r
433\r
434#define DDR3_EMRS1_RTTNOM_0 (0)\r
435#define DDR3_EMRS1_RTTNOM_60 (BIT2)\r
436#define DDR3_EMRS1_RTTNOM_120 (BIT6)\r
437#define DDR3_EMRS1_RTTNOM_40 (BIT6|BIT2)\r
438#define DDR3_EMRS1_RTTNOM_20 (BIT9)\r
439#define DDR3_EMRS1_RTTNOM_30 (BIT9|BIT2)\r
440\r
441\r
442//\r
443// END DRAM Init...\r
444//\r
445////\r
446\r
447\r
448// HOST_BRIDGE registers:\r
449#define HMBOUND 0x0020 //ok\r
450\r
451// MEMORY_MANAGER registers:\r
452#define BCTRL 0x0004\r
453#define BWFLUSH 0x0008\r
454#define BDEBUG1 0x00C4\r
455\r
456////\r
457//\r
458// BEGIN DDRIO registers\r
459//\r
460\r
461// DDR IOs & COMPs:\r
462#define DDRIODQ_BL_OFFSET 0x0800\r
463#define DDRIODQ_CH_OFFSET ((NUM_BYTE_LANES/2) * DDRIODQ_BL_OFFSET)\r
464#define DDRIOCCC_CH_OFFSET 0x0800\r
465#define DDRCOMP_CH_OFFSET 0x0100\r
466\r
467// CH0-BL01-DQ\r
468#define DQOBSCKEBBCTL 0x0000\r
469#define DQDLLTXCTL 0x0004\r
470#define DQDLLRXCTL 0x0008\r
471#define DQMDLLCTL 0x000C\r
472#define B0RXIOBUFCTL 0x0010\r
473#define B0VREFCTL 0x0014\r
474#define B0RXOFFSET1 0x0018\r
475#define B0RXOFFSET0 0x001C\r
476#define B1RXIOBUFCTL 0x0020\r
477#define B1VREFCTL 0x0024\r
478#define B1RXOFFSET1 0x0028\r
479#define B1RXOFFSET0 0x002C\r
480#define DQDFTCTL 0x0030\r
481#define DQTRAINSTS 0x0034\r
482#define B1DLLPICODER0 0x0038\r
483#define B0DLLPICODER0 0x003C\r
484#define B1DLLPICODER1 0x0040\r
485#define B0DLLPICODER1 0x0044\r
486#define B1DLLPICODER2 0x0048\r
487#define B0DLLPICODER2 0x004C\r
488#define B1DLLPICODER3 0x0050\r
489#define B0DLLPICODER3 0x0054\r
490#define B1RXDQSPICODE 0x0058\r
491#define B0RXDQSPICODE 0x005C\r
492#define B1RXDQPICODER32 0x0060\r
493#define B1RXDQPICODER10 0x0064\r
494#define B0RXDQPICODER32 0x0068\r
495#define B0RXDQPICODER10 0x006C\r
496#define B01PTRCTL0 0x0070\r
497#define B01PTRCTL1 0x0074\r
498#define B01DBCTL0 0x0078\r
499#define B01DBCTL1 0x007C\r
500#define B0LATCTL0 0x0080\r
501#define B1LATCTL0 0x0084\r
502#define B01LATCTL1 0x0088\r
503#define B0ONDURCTL 0x008C\r
504#define B1ONDURCTL 0x0090\r
505#define B0OVRCTL 0x0094\r
506#define B1OVRCTL 0x0098\r
507#define DQCTL 0x009C\r
508#define B0RK2RKCHGPTRCTRL 0x00A0\r
509#define B1RK2RKCHGPTRCTRL 0x00A4\r
510#define DQRK2RKCTL 0x00A8\r
511#define DQRK2RKPTRCTL 0x00AC\r
512#define B0RK2RKLAT 0x00B0\r
513#define B1RK2RKLAT 0x00B4\r
514#define DQCLKALIGNREG0 0x00B8\r
515#define DQCLKALIGNREG1 0x00BC\r
516#define DQCLKALIGNREG2 0x00C0\r
517#define DQCLKALIGNSTS0 0x00C4\r
518#define DQCLKALIGNSTS1 0x00C8\r
519#define DQCLKGATE 0x00CC\r
520#define B0COMPSLV1 0x00D0\r
521#define B1COMPSLV1 0x00D4\r
522#define B0COMPSLV2 0x00D8\r
523#define B1COMPSLV2 0x00DC\r
524#define B0COMPSLV3 0x00E0\r
525#define B1COMPSLV3 0x00E4\r
526#define DQVISALANECR0TOP 0x00E8\r
527#define DQVISALANECR1TOP 0x00EC\r
528#define DQVISACONTROLCRTOP 0x00F0\r
529#define DQVISALANECR0BL 0x00F4\r
530#define DQVISALANECR1BL 0x00F8\r
531#define DQVISACONTROLCRBL 0x00FC\r
532#define DQTIMINGCTRL 0x010C\r
533// CH0-ECC\r
534#define ECCDLLTXCTL 0x2004\r
535#define ECCDLLRXCTL 0x2008\r
536#define ECCMDLLCTL 0x200C\r
537#define ECCB1DLLPICODER0 0x2038\r
538#define ECCB1DLLPICODER1 0x2040\r
539#define ECCB1DLLPICODER2 0x2048\r
540#define ECCB1DLLPICODER3 0x2050\r
541#define ECCB01DBCTL0 0x2078\r
542#define ECCB01DBCTL1 0x207C\r
543#define ECCCLKALIGNREG0 0x20B8\r
544#define ECCCLKALIGNREG1 0x20BC\r
545#define ECCCLKALIGNREG2 0x20C0\r
546// CH0-CMD\r
547#define CMDOBSCKEBBCTL 0x4800\r
548#define CMDDLLTXCTL 0x4808\r
549#define CMDDLLRXCTL 0x480C\r
550#define CMDMDLLCTL 0x4810\r
551#define CMDRCOMPODT 0x4814\r
552#define CMDDLLPICODER0 0x4820\r
553#define CMDDLLPICODER1 0x4824\r
554#define CMDCFGREG0 0x4840\r
555#define CMDPTRREG 0x4844\r
556#define CMDCLKALIGNREG0 0x4850\r
557#define CMDCLKALIGNREG1 0x4854\r
558#define CMDCLKALIGNREG2 0x4858\r
559#define CMDPMCONFIG0 0x485C\r
560#define CMDPMDLYREG0 0x4860\r
561#define CMDPMDLYREG1 0x4864\r
562#define CMDPMDLYREG2 0x4868\r
563#define CMDPMDLYREG3 0x486C\r
564#define CMDPMDLYREG4 0x4870\r
565#define CMDCLKALIGNSTS0 0x4874\r
566#define CMDCLKALIGNSTS1 0x4878\r
567#define CMDPMSTS0 0x487C\r
568#define CMDPMSTS1 0x4880\r
569#define CMDCOMPSLV 0x4884\r
570#define CMDBONUS0 0x488C\r
571#define CMDBONUS1 0x4890\r
572#define CMDVISALANECR0 0x4894\r
573#define CMDVISALANECR1 0x4898\r
574#define CMDVISACONTROLCR 0x489C\r
575#define CMDCLKGATE 0x48A0\r
576#define CMDTIMINGCTRL 0x48A4\r
577// CH0-CLK-CTL\r
578#define CCOBSCKEBBCTL 0x5800\r
579#define CCRCOMPIO 0x5804\r
580#define CCDLLTXCTL 0x5808\r
581#define CCDLLRXCTL 0x580C\r
582#define CCMDLLCTL 0x5810\r
583#define CCRCOMPODT 0x5814\r
584#define CCDLLPICODER0 0x5820\r
585#define CCDLLPICODER1 0x5824\r
586#define CCDDR3RESETCTL 0x5830\r
587#define CCCFGREG0 0x5838\r
588#define CCCFGREG1 0x5840\r
589#define CCPTRREG 0x5844\r
590#define CCCLKALIGNREG0 0x5850\r
591#define CCCLKALIGNREG1 0x5854\r
592#define CCCLKALIGNREG2 0x5858\r
593#define CCPMCONFIG0 0x585C\r
594#define CCPMDLYREG0 0x5860\r
595#define CCPMDLYREG1 0x5864\r
596#define CCPMDLYREG2 0x5868\r
597#define CCPMDLYREG3 0x586C\r
598#define CCPMDLYREG4 0x5870\r
599#define CCCLKALIGNSTS0 0x5874\r
600#define CCCLKALIGNSTS1 0x5878\r
601#define CCPMSTS0 0x587C\r
602#define CCPMSTS1 0x5880\r
603#define CCCOMPSLV1 0x5884\r
604#define CCCOMPSLV2 0x5888\r
605#define CCCOMPSLV3 0x588C\r
606#define CCBONUS0 0x5894\r
607#define CCBONUS1 0x5898\r
608#define CCVISALANECR0 0x589C\r
609#define CCVISALANECR1 0x58A0\r
610#define CCVISACONTROLCR 0x58A4\r
611#define CCCLKGATE 0x58A8\r
612#define CCTIMINGCTL 0x58AC\r
613// COMP\r
614#define CMPCTRL 0x6800\r
615#define SOFTRSTCNTL 0x6804\r
616#define MSCNTR 0x6808\r
617#define NMSCNTRL 0x680C\r
618#define LATCH1CTL 0x6814\r
619#define COMPVISALANECR0 0x681C\r
620#define COMPVISALANECR1 0x6820\r
621#define COMPVISACONTROLCR 0x6824\r
622#define COMPBONUS0 0x6830\r
623#define TCOCNTCTRL 0x683C\r
624#define DQANAODTPUCTL 0x6840\r
625#define DQANAODTPDCTL 0x6844\r
626#define DQANADRVPUCTL 0x6848\r
627#define DQANADRVPDCTL 0x684C\r
628#define DQANADLYPUCTL 0x6850\r
629#define DQANADLYPDCTL 0x6854\r
630#define DQANATCOPUCTL 0x6858\r
631#define DQANATCOPDCTL 0x685C\r
632#define CMDANADRVPUCTL 0x6868\r
633#define CMDANADRVPDCTL 0x686C\r
634#define CMDANADLYPUCTL 0x6870\r
635#define CMDANADLYPDCTL 0x6874\r
636#define CLKANAODTPUCTL 0x6880\r
637#define CLKANAODTPDCTL 0x6884\r
638#define CLKANADRVPUCTL 0x6888\r
639#define CLKANADRVPDCTL 0x688C\r
640#define CLKANADLYPUCTL 0x6890\r
641#define CLKANADLYPDCTL 0x6894\r
642#define CLKANATCOPUCTL 0x6898\r
643#define CLKANATCOPDCTL 0x689C\r
644#define DQSANAODTPUCTL 0x68A0\r
645#define DQSANAODTPDCTL 0x68A4\r
646#define DQSANADRVPUCTL 0x68A8\r
647#define DQSANADRVPDCTL 0x68AC\r
648#define DQSANADLYPUCTL 0x68B0\r
649#define DQSANADLYPDCTL 0x68B4\r
650#define DQSANATCOPUCTL 0x68B8\r
651#define DQSANATCOPDCTL 0x68BC\r
652#define CTLANADRVPUCTL 0x68C8\r
653#define CTLANADRVPDCTL 0x68CC\r
654#define CTLANADLYPUCTL 0x68D0\r
655#define CTLANADLYPDCTL 0x68D4\r
656#define CHNLBUFSTATIC 0x68F0\r
657#define COMPOBSCNTRL 0x68F4\r
658#define COMPBUFFDBG0 0x68F8\r
659#define COMPBUFFDBG1 0x68FC\r
660#define CFGMISCCH0 0x6900\r
661#define COMPEN0CH0 0x6904\r
662#define COMPEN1CH0 0x6908\r
663#define COMPEN2CH0 0x690C\r
664#define STATLEGEN0CH0 0x6910\r
665#define STATLEGEN1CH0 0x6914\r
666#define DQVREFCH0 0x6918\r
667#define CMDVREFCH0 0x691C\r
668#define CLKVREFCH0 0x6920\r
669#define DQSVREFCH0 0x6924\r
670#define CTLVREFCH0 0x6928\r
671#define TCOVREFCH0 0x692C\r
672#define DLYSELCH0 0x6930\r
673#define TCODRAMBUFODTCH0 0x6934\r
674#define CCBUFODTCH0 0x6938\r
675#define RXOFFSETCH0 0x693C\r
676#define DQODTPUCTLCH0 0x6940\r
677#define DQODTPDCTLCH0 0x6944\r
678#define DQDRVPUCTLCH0 0x6948\r
679#define DQDRVPDCTLCH0 0x694C\r
680#define DQDLYPUCTLCH0 0x6950\r
681#define DQDLYPDCTLCH0 0x6954\r
682#define DQTCOPUCTLCH0 0x6958\r
683#define DQTCOPDCTLCH0 0x695C\r
684#define CMDDRVPUCTLCH0 0x6968\r
685#define CMDDRVPDCTLCH0 0x696C\r
686#define CMDDLYPUCTLCH0 0x6970\r
687#define CMDDLYPDCTLCH0 0x6974\r
688#define CLKODTPUCTLCH0 0x6980\r
689#define CLKODTPDCTLCH0 0x6984\r
690#define CLKDRVPUCTLCH0 0x6988\r
691#define CLKDRVPDCTLCH0 0x698C\r
692#define CLKDLYPUCTLCH0 0x6990\r
693#define CLKDLYPDCTLCH0 0x6994\r
694#define CLKTCOPUCTLCH0 0x6998\r
695#define CLKTCOPDCTLCH0 0x699C\r
696#define DQSODTPUCTLCH0 0x69A0\r
697#define DQSODTPDCTLCH0 0x69A4\r
698#define DQSDRVPUCTLCH0 0x69A8\r
699#define DQSDRVPDCTLCH0 0x69AC\r
700#define DQSDLYPUCTLCH0 0x69B0\r
701#define DQSDLYPDCTLCH0 0x69B4\r
702#define DQSTCOPUCTLCH0 0x69B8\r
703#define DQSTCOPDCTLCH0 0x69BC\r
704#define CTLDRVPUCTLCH0 0x69C8\r
705#define CTLDRVPDCTLCH0 0x69CC\r
706#define CTLDLYPUCTLCH0 0x69D0\r
707#define CTLDLYPDCTLCH0 0x69D4\r
708#define FNLUPDTCTLCH0 0x69F0\r
709// PLL\r
710#define MPLLCTRL0 0x7800\r
711#define MPLLCTRL1 0x7808\r
712#define MPLLCSR0 0x7810\r
713#define MPLLCSR1 0x7814\r
714#define MPLLCSR2 0x7820\r
715#define MPLLDFT 0x7828\r
716#define MPLLMON0CTL 0x7830\r
717#define MPLLMON1CTL 0x7838\r
718#define MPLLMON2CTL 0x783C\r
719#define SFRTRIM 0x7850\r
720#define MPLLDFTOUT0 0x7858\r
721#define MPLLDFTOUT1 0x785C\r
722#define MASTERRSTN 0x7880\r
723#define PLLLOCKDEL 0x7884\r
724#define SFRDEL 0x7888\r
725#define CRUVISALANECR0 0x78F0\r
726#define CRUVISALANECR1 0x78F4\r
727#define CRUVISACONTROLCR 0x78F8\r
728#define IOSFVISALANECR0 0x78FC\r
729#define IOSFVISALANECR1 0x7900\r
730#define IOSFVISACONTROLCR 0x7904\r
731\r
732//\r
733// END DDRIO registers\r
734//\r
735////\r
736\r
737\r
738#endif\r
EFI Development Kit II mirror for PVE