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9b6bbcdb MK |
1 | /** @file\r |
2 | HTE handling routines for MRC use.\r | |
3 | \r | |
4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
5 | \r | |
c9f231d0 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
9b6bbcdb MK |
7 | \r |
8 | **/\r | |
9 | #ifndef __HTE_H\r | |
10 | #define __HTE_H\r | |
11 | \r | |
12 | #define STATIC static\r | |
13 | #define VOID void\r | |
14 | \r | |
15 | #if !defined(__GNUC__) && (__STDC_VERSION__ < 199901L)\r | |
16 | typedef uint32_t UINT32;\r | |
17 | typedef uint16_t UINT16;\r | |
18 | typedef uint8_t UINT8;\r | |
19 | #endif\r | |
20 | \r | |
21 | typedef enum\r | |
22 | {\r | |
23 | MrcNoHaltSystemOnError,\r | |
24 | MrcHaltSystemOnError,\r | |
25 | MrcHaltHteEngineOnError,\r | |
26 | MrcNoHaltHteEngineOnError\r | |
27 | } HALT_TYPE;\r | |
28 | \r | |
29 | typedef enum\r | |
30 | {\r | |
31 | MrcMemInit, MrcMemTest\r | |
32 | } MEM_INIT_OR_TEST;\r | |
33 | \r | |
34 | #define READ_TRAIN 1\r | |
35 | #define WRITE_TRAIN 2\r | |
36 | \r | |
37 | #define HTE_MEMTEST_NUM 2\r | |
38 | #define HTE_LOOP_CNT 5 // EXP_LOOP_CNT field of HTE_CMD_CTL. This CANNOT be less than 4\r | |
39 | #define HTE_LFSR_VICTIM_SEED 0xF294BA21 // Random seed for victim.\r | |
40 | #define HTE_LFSR_AGRESSOR_SEED 0xEBA7492D // Random seed for aggressor.\r | |
41 | UINT32\r | |
42 | HteMemInit(\r | |
43 | MRC_PARAMS *CurrentMrcData,\r | |
44 | UINT8 MemInitFlag,\r | |
45 | UINT8 HaltHteEngineOnError);\r | |
46 | \r | |
47 | UINT16\r | |
48 | BasicWriteReadHTE(\r | |
49 | MRC_PARAMS *CurrentMrcData,\r | |
50 | UINT32 Address,\r | |
51 | UINT8 FirstRun,\r | |
52 | UINT8 Mode);\r | |
53 | \r | |
54 | UINT16\r | |
55 | WriteStressBitLanesHTE(\r | |
56 | MRC_PARAMS *CurrentMrcData,\r | |
57 | UINT32 Address,\r | |
58 | UINT8 FirstRun);\r | |
59 | \r | |
60 | VOID\r | |
61 | HteMemOp(\r | |
62 | UINT32 Address,\r | |
63 | UINT8 FirstRun,\r | |
64 | UINT8 IsWrite);\r | |
65 | \r | |
66 | #endif\r |