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1 | /** @file\r |
2 | TIS (TPM Interface Specification) functions used by TPM1.2.\r | |
3 | \r | |
6f785cfc | 4 | Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r |
c1d93242 JY |
5 | This program and the accompanying materials \r |
6 | are licensed and made available under the terms and conditions of the BSD License \r | |
7 | which accompanies this distribution. The full text of the license may be found at \r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include <Uefi.h>\r | |
16 | #include <IndustryStandard/Tpm12.h>\r | |
17 | #include <Library/BaseLib.h>\r | |
18 | #include <Library/BaseMemoryLib.h>\r | |
19 | #include <Library/IoLib.h>\r | |
20 | #include <Library/TimerLib.h>\r | |
21 | #include <Library/DebugLib.h>\r | |
22 | #include <Library/Tpm12CommandLib.h>\r | |
23 | #include <Library/PcdLib.h>\r | |
24 | \r | |
25 | //\r | |
26 | // Set structure alignment to 1-byte\r | |
27 | //\r | |
28 | #pragma pack (1)\r | |
29 | \r | |
30 | //\r | |
31 | // Register set map as specified in TIS specification Chapter 10\r | |
32 | //\r | |
33 | typedef struct {\r | |
34 | ///\r | |
35 | /// Used to gain ownership for this particular port.\r | |
36 | ///\r | |
37 | UINT8 Access; // 0\r | |
38 | UINT8 Reserved1[7]; // 1\r | |
39 | ///\r | |
40 | /// Controls interrupts.\r | |
41 | ///\r | |
42 | UINT32 IntEnable; // 8\r | |
43 | ///\r | |
44 | /// SIRQ vector to be used by the TPM.\r | |
45 | ///\r | |
46 | UINT8 IntVector; // 0ch\r | |
47 | UINT8 Reserved2[3]; // 0dh\r | |
48 | ///\r | |
49 | /// What caused interrupt.\r | |
50 | ///\r | |
51 | UINT32 IntSts; // 10h\r | |
52 | ///\r | |
53 | /// Shows which interrupts are supported by that particular TPM.\r | |
54 | ///\r | |
55 | UINT32 IntfCapability; // 14h\r | |
56 | ///\r | |
57 | /// Status Register. Provides status of the TPM.\r | |
58 | ///\r | |
59 | UINT8 Status; // 18h\r | |
60 | ///\r | |
61 | /// Number of consecutive writes that can be done to the TPM.\r | |
62 | ///\r | |
63 | UINT16 BurstCount; // 19h\r | |
64 | UINT8 Reserved3[9];\r | |
65 | ///\r | |
66 | /// Read or write FIFO, depending on transaction.\r | |
67 | ///\r | |
68 | UINT32 DataFifo; // 24h\r | |
69 | UINT8 Reserved4[0xed8]; // 28h\r | |
70 | ///\r | |
71 | /// Vendor ID\r | |
72 | ///\r | |
73 | UINT16 Vid; // 0f00h\r | |
74 | ///\r | |
75 | /// Device ID\r | |
76 | ///\r | |
77 | UINT16 Did; // 0f02h\r | |
78 | ///\r | |
79 | /// Revision ID\r | |
80 | ///\r | |
81 | UINT8 Rid; // 0f04h\r | |
82 | ///\r | |
83 | /// TCG defined configuration registers.\r | |
84 | ///\r | |
85 | UINT8 TcgDefined[0x7b]; // 0f05h\r | |
86 | ///\r | |
87 | /// Alias to I/O legacy space.\r | |
88 | ///\r | |
89 | UINT32 LegacyAddress1; // 0f80h\r | |
90 | ///\r | |
91 | /// Additional 8 bits for I/O legacy space extension.\r | |
92 | ///\r | |
93 | UINT32 LegacyAddress1Ex; // 0f84h\r | |
94 | ///\r | |
95 | /// Alias to second I/O legacy space.\r | |
96 | ///\r | |
97 | UINT32 LegacyAddress2; // 0f88h\r | |
98 | ///\r | |
99 | /// Additional 8 bits for second I/O legacy space extension.\r | |
100 | ///\r | |
101 | UINT32 LegacyAddress2Ex; // 0f8ch\r | |
102 | ///\r | |
103 | /// Vendor-defined configuration registers.\r | |
104 | ///\r | |
105 | UINT8 VendorDefined[0x70];// 0f90h\r | |
106 | } TIS_PC_REGISTERS;\r | |
107 | \r | |
108 | //\r | |
109 | // Restore original structure alignment\r | |
110 | //\r | |
111 | #pragma pack ()\r | |
112 | \r | |
113 | //\r | |
114 | // Define pointer types used to access TIS registers on PC\r | |
115 | //\r | |
116 | typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;\r | |
117 | \r | |
118 | //\r | |
119 | // Define bits of ACCESS and STATUS registers\r | |
120 | //\r | |
121 | \r | |
122 | ///\r | |
123 | /// This bit is a 1 to indicate that the other bits in this register are valid.\r | |
124 | ///\r | |
125 | #define TIS_PC_VALID BIT7\r | |
126 | ///\r | |
127 | /// Indicate that this locality is active.\r | |
128 | ///\r | |
129 | #define TIS_PC_ACC_ACTIVE BIT5\r | |
130 | ///\r | |
131 | /// Set to 1 to indicate that this locality had the TPM taken away while\r | |
132 | /// this locality had the TIS_PC_ACC_ACTIVE bit set.\r | |
133 | ///\r | |
134 | #define TIS_PC_ACC_SEIZED BIT4\r | |
135 | ///\r | |
136 | /// Set to 1 to indicate that TPM MUST reset the\r | |
137 | /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r | |
138 | /// locality that is writing this bit.\r | |
139 | ///\r | |
140 | #define TIS_PC_ACC_SEIZE BIT3\r | |
141 | ///\r | |
142 | /// When this bit is 1, another locality is requesting usage of the TPM.\r | |
143 | ///\r | |
144 | #define TIS_PC_ACC_PENDIND BIT2\r | |
145 | ///\r | |
146 | /// Set to 1 to indicate that this locality is requesting to use TPM.\r | |
147 | ///\r | |
148 | #define TIS_PC_ACC_RQUUSE BIT1\r | |
149 | ///\r | |
150 | /// A value of 1 indicates that a T/OS has not been established on the platform\r | |
151 | ///\r | |
152 | #define TIS_PC_ACC_ESTABLISH BIT0\r | |
153 | \r | |
154 | ///\r | |
155 | /// When this bit is 1, TPM is in the Ready state, \r | |
156 | /// indicating it is ready to receive a new command.\r | |
157 | ///\r | |
158 | #define TIS_PC_STS_READY BIT6\r | |
159 | ///\r | |
160 | /// Write a 1 to this bit to cause the TPM to execute that command.\r | |
161 | ///\r | |
162 | #define TIS_PC_STS_GO BIT5\r | |
163 | ///\r | |
164 | /// This bit indicates that the TPM has data available as a response.\r | |
165 | ///\r | |
166 | #define TIS_PC_STS_DATA BIT4\r | |
167 | ///\r | |
168 | /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r | |
169 | ///\r | |
170 | #define TIS_PC_STS_EXPECT BIT3\r | |
171 | ///\r | |
172 | /// Writes a 1 to this bit to force the TPM to re-send the response.\r | |
173 | ///\r | |
174 | #define TIS_PC_STS_RETRY BIT1\r | |
175 | \r | |
176 | //\r | |
177 | // Default TimeOut value\r | |
178 | //\r | |
179 | #define TIS_TIMEOUT_A (750 * 1000) // 750ms\r | |
180 | #define TIS_TIMEOUT_B (2000 * 1000) // 2s\r | |
181 | #define TIS_TIMEOUT_C (750 * 1000) // 750ms\r | |
182 | #define TIS_TIMEOUT_D (750 * 1000) // 750ms\r | |
183 | \r | |
184 | //\r | |
185 | // Max TPM command/reponse length\r | |
186 | //\r | |
187 | #define TPMCMDBUFLENGTH 1024\r | |
188 | \r | |
189 | /**\r | |
190 | Check whether TPM chip exist.\r | |
191 | \r | |
192 | @param[in] TisReg Pointer to TIS register.\r | |
193 | \r | |
194 | @retval TRUE TPM chip exists.\r | |
195 | @retval FALSE TPM chip is not found.\r | |
196 | **/\r | |
197 | BOOLEAN\r | |
198 | Tpm12TisPcPresenceCheck (\r | |
199 | IN TIS_PC_REGISTERS_PTR TisReg\r | |
200 | )\r | |
201 | {\r | |
202 | UINT8 RegRead;\r | |
203 | \r | |
204 | RegRead = MmioRead8 ((UINTN)&TisReg->Access);\r | |
205 | return (BOOLEAN)(RegRead != (UINT8)-1);\r | |
206 | }\r | |
207 | \r | |
208 | /**\r | |
209 | Check whether the value of a TPM chip register satisfies the input BIT setting.\r | |
210 | \r | |
211 | @param[in] Register Address port of register to be checked.\r | |
212 | @param[in] BitSet Check these data bits are set.\r | |
213 | @param[in] BitClear Check these data bits are clear.\r | |
214 | @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.\r | |
215 | \r | |
216 | @retval EFI_SUCCESS The register satisfies the check bit.\r | |
217 | @retval EFI_TIMEOUT The register can't run into the expected status in time.\r | |
218 | **/\r | |
219 | EFI_STATUS\r | |
c1d93242 JY |
220 | Tpm12TisPcWaitRegisterBits (\r |
221 | IN UINT8 *Register,\r | |
222 | IN UINT8 BitSet,\r | |
223 | IN UINT8 BitClear,\r | |
224 | IN UINT32 TimeOut\r | |
225 | )\r | |
226 | {\r | |
227 | UINT8 RegRead;\r | |
228 | UINT32 WaitTime;\r | |
229 | \r | |
230 | for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r | |
231 | RegRead = MmioRead8 ((UINTN)Register);\r | |
232 | if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)\r | |
233 | return EFI_SUCCESS;\r | |
234 | MicroSecondDelay (30);\r | |
235 | }\r | |
236 | return EFI_TIMEOUT;\r | |
237 | }\r | |
238 | \r | |
239 | /**\r | |
240 | Get BurstCount by reading the burstCount field of a TIS regiger \r | |
241 | in the time of default TIS_TIMEOUT_D.\r | |
242 | \r | |
243 | @param[in] TisReg Pointer to TIS register.\r | |
244 | @param[out] BurstCount Pointer to a buffer to store the got BurstConut.\r | |
245 | \r | |
246 | @retval EFI_SUCCESS Get BurstCount.\r | |
247 | @retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.\r | |
248 | @retval EFI_TIMEOUT BurstCount can't be got in time.\r | |
249 | **/\r | |
250 | EFI_STATUS\r | |
c1d93242 JY |
251 | Tpm12TisPcReadBurstCount (\r |
252 | IN TIS_PC_REGISTERS_PTR TisReg,\r | |
253 | OUT UINT16 *BurstCount\r | |
254 | )\r | |
255 | {\r | |
256 | UINT32 WaitTime;\r | |
257 | UINT8 DataByte0;\r | |
258 | UINT8 DataByte1;\r | |
259 | \r | |
260 | if (BurstCount == NULL || TisReg == NULL) {\r | |
261 | return EFI_INVALID_PARAMETER;\r | |
262 | }\r | |
263 | \r | |
264 | WaitTime = 0;\r | |
265 | do {\r | |
266 | //\r | |
267 | // TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,\r | |
268 | // so it needs to use MmioRead8 to read two times\r | |
269 | //\r | |
270 | DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);\r | |
271 | DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);\r | |
272 | *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);\r | |
273 | if (*BurstCount != 0) {\r | |
274 | return EFI_SUCCESS;\r | |
275 | }\r | |
276 | MicroSecondDelay (30);\r | |
277 | WaitTime += 30;\r | |
278 | } while (WaitTime < TIS_TIMEOUT_D);\r | |
279 | \r | |
280 | return EFI_TIMEOUT;\r | |
281 | }\r | |
282 | \r | |
283 | /**\r | |
284 | Set TPM chip to ready state by sending ready command TIS_PC_STS_READY \r | |
285 | to Status Register in time.\r | |
286 | \r | |
287 | @param[in] TisReg Pointer to TIS register.\r | |
288 | \r | |
289 | @retval EFI_SUCCESS TPM chip enters into ready state.\r | |
290 | @retval EFI_INVALID_PARAMETER TisReg is NULL.\r | |
291 | @retval EFI_TIMEOUT TPM chip can't be set to ready state in time.\r | |
292 | **/\r | |
293 | EFI_STATUS\r | |
c1d93242 JY |
294 | Tpm12TisPcPrepareCommand (\r |
295 | IN TIS_PC_REGISTERS_PTR TisReg\r | |
296 | )\r | |
297 | {\r | |
298 | EFI_STATUS Status;\r | |
299 | \r | |
300 | if (TisReg == NULL) {\r | |
301 | return EFI_INVALID_PARAMETER;\r | |
302 | }\r | |
303 | \r | |
304 | MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r | |
305 | Status = Tpm12TisPcWaitRegisterBits (\r | |
306 | &TisReg->Status,\r | |
307 | TIS_PC_STS_READY,\r | |
308 | 0,\r | |
309 | TIS_TIMEOUT_B\r | |
310 | );\r | |
311 | return Status;\r | |
312 | }\r | |
313 | \r | |
314 | /**\r | |
315 | Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE \r | |
316 | to ACCESS Register in the time of default TIS_TIMEOUT_A.\r | |
317 | \r | |
318 | @param[in] TisReg Pointer to TIS register.\r | |
319 | \r | |
320 | @retval EFI_SUCCESS Get the control of TPM chip.\r | |
321 | @retval EFI_INVALID_PARAMETER TisReg is NULL.\r | |
322 | @retval EFI_NOT_FOUND TPM chip doesn't exit.\r | |
323 | @retval EFI_TIMEOUT Can't get the TPM control in time.\r | |
324 | **/\r | |
325 | EFI_STATUS\r | |
c1d93242 JY |
326 | Tpm12TisPcRequestUseTpm (\r |
327 | IN TIS_PC_REGISTERS_PTR TisReg\r | |
328 | )\r | |
329 | {\r | |
330 | EFI_STATUS Status;\r | |
331 | \r | |
332 | if (TisReg == NULL) {\r | |
333 | return EFI_INVALID_PARAMETER;\r | |
334 | }\r | |
335 | \r | |
336 | if (!Tpm12TisPcPresenceCheck (TisReg)) {\r | |
337 | return EFI_NOT_FOUND;\r | |
338 | }\r | |
339 | \r | |
340 | MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);\r | |
341 | Status = Tpm12TisPcWaitRegisterBits (\r | |
342 | &TisReg->Access,\r | |
343 | (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),\r | |
344 | 0,\r | |
345 | TIS_TIMEOUT_A\r | |
346 | );\r | |
347 | return Status;\r | |
348 | }\r | |
349 | \r | |
350 | /**\r | |
351 | Send a command to TPM for execution and return response data.\r | |
352 | \r | |
353 | @param[in] TisReg TPM register space base address. \r | |
354 | @param[in] BufferIn Buffer for command data. \r | |
355 | @param[in] SizeIn Size of command data. \r | |
356 | @param[in, out] BufferOut Buffer for response data. \r | |
357 | @param[in, out] SizeOut Size of response data. \r | |
358 | \r | |
359 | @retval EFI_SUCCESS Operation completed successfully.\r | |
c1d93242 JY |
360 | @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r |
361 | @retval EFI_DEVICE_ERROR Unexpected device behavior.\r | |
362 | @retval EFI_UNSUPPORTED Unsupported TPM version\r | |
363 | \r | |
364 | **/\r | |
365 | EFI_STATUS\r | |
366 | Tpm12TisTpmCommand (\r | |
367 | IN TIS_PC_REGISTERS_PTR TisReg,\r | |
368 | IN UINT8 *BufferIn,\r | |
369 | IN UINT32 SizeIn,\r | |
370 | IN OUT UINT8 *BufferOut,\r | |
371 | IN OUT UINT32 *SizeOut\r | |
372 | )\r | |
373 | {\r | |
374 | EFI_STATUS Status;\r | |
375 | UINT16 BurstCount;\r | |
376 | UINT32 Index;\r | |
377 | UINT32 TpmOutSize;\r | |
378 | UINT16 Data16;\r | |
379 | UINT32 Data32;\r | |
380 | \r | |
381 | DEBUG_CODE (\r | |
382 | UINTN DebugSize;\r | |
383 | \r | |
384 | DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand Send - "));\r | |
385 | if (SizeIn > 0x100) {\r | |
386 | DebugSize = 0x40;\r | |
387 | } else {\r | |
388 | DebugSize = SizeIn;\r | |
389 | }\r | |
390 | for (Index = 0; Index < DebugSize; Index++) {\r | |
391 | DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));\r | |
392 | }\r | |
393 | if (DebugSize != SizeIn) {\r | |
394 | DEBUG ((EFI_D_INFO, "...... "));\r | |
395 | for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r | |
396 | DEBUG ((EFI_D_INFO, "%02x ", BufferIn[Index]));\r | |
397 | }\r | |
398 | }\r | |
399 | DEBUG ((EFI_D_INFO, "\n"));\r | |
400 | );\r | |
401 | TpmOutSize = 0;\r | |
402 | \r | |
403 | Status = Tpm12TisPcPrepareCommand (TisReg);\r | |
404 | if (EFI_ERROR (Status)){\r | |
405 | DEBUG ((DEBUG_ERROR, "Tpm12 is not ready for command!\n"));\r | |
6f785cfc | 406 | return EFI_DEVICE_ERROR;\r |
c1d93242 JY |
407 | }\r |
408 | //\r | |
409 | // Send the command data to Tpm\r | |
410 | //\r | |
411 | Index = 0;\r | |
412 | while (Index < SizeIn) {\r | |
413 | Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r | |
414 | if (EFI_ERROR (Status)) {\r | |
6f785cfc | 415 | Status = EFI_DEVICE_ERROR;\r |
c1d93242 JY |
416 | goto Exit;\r |
417 | }\r | |
418 | for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {\r | |
419 | MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));\r | |
420 | Index++;\r | |
421 | }\r | |
422 | }\r | |
423 | //\r | |
424 | // Check the Tpm status STS_EXPECT change from 1 to 0\r | |
425 | //\r | |
426 | Status = Tpm12TisPcWaitRegisterBits (\r | |
427 | &TisReg->Status,\r | |
428 | (UINT8) TIS_PC_VALID,\r | |
429 | TIS_PC_STS_EXPECT,\r | |
430 | TIS_TIMEOUT_C\r | |
431 | );\r | |
432 | if (EFI_ERROR (Status)) {\r | |
433 | DEBUG ((DEBUG_ERROR, "Tpm12 The send buffer too small!\n"));\r | |
434 | Status = EFI_BUFFER_TOO_SMALL;\r | |
435 | goto Exit;\r | |
436 | }\r | |
437 | //\r | |
438 | // Executed the TPM command and waiting for the response data ready\r | |
439 | //\r | |
440 | MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);\r | |
441 | Status = Tpm12TisPcWaitRegisterBits (\r | |
442 | &TisReg->Status,\r | |
443 | (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),\r | |
444 | 0,\r | |
445 | TIS_TIMEOUT_B\r | |
446 | );\r | |
447 | if (EFI_ERROR (Status)) {\r | |
448 | DEBUG ((DEBUG_ERROR, "Wait for Tpm12 response data time out!!\n"));\r | |
6f785cfc | 449 | Status = EFI_DEVICE_ERROR;\r |
c1d93242 JY |
450 | goto Exit;\r |
451 | }\r | |
452 | //\r | |
453 | // Get response data header\r | |
454 | //\r | |
455 | Index = 0;\r | |
456 | BurstCount = 0;\r | |
457 | while (Index < sizeof (TPM_RSP_COMMAND_HDR)) {\r | |
458 | Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r | |
459 | if (EFI_ERROR (Status)) {\r | |
6f785cfc | 460 | Status = EFI_DEVICE_ERROR;\r |
c1d93242 JY |
461 | goto Exit;\r |
462 | }\r | |
463 | for (; BurstCount > 0; BurstCount--) {\r | |
464 | *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r | |
465 | Index++;\r | |
466 | if (Index == sizeof (TPM_RSP_COMMAND_HDR)) break;\r | |
467 | }\r | |
468 | }\r | |
469 | DEBUG_CODE (\r | |
470 | DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand ReceiveHeader - "));\r | |
471 | for (Index = 0; Index < sizeof (TPM_RSP_COMMAND_HDR); Index++) {\r | |
472 | DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));\r | |
473 | }\r | |
474 | DEBUG ((EFI_D_INFO, "\n"));\r | |
475 | );\r | |
476 | //\r | |
477 | // Check the reponse data header (tag,parasize and returncode )\r | |
478 | //\r | |
479 | CopyMem (&Data16, BufferOut, sizeof (UINT16));\r | |
480 | if (SwapBytes16 (Data16) != TPM_TAG_RSP_COMMAND) {\r | |
481 | DEBUG ((EFI_D_ERROR, "TPM12: TPM_ST_RSP error - %x\n", TPM_TAG_RSP_COMMAND));\r | |
482 | Status = EFI_UNSUPPORTED;\r | |
483 | goto Exit;\r | |
484 | }\r | |
485 | \r | |
486 | CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));\r | |
487 | TpmOutSize = SwapBytes32 (Data32);\r | |
488 | if (*SizeOut < TpmOutSize) {\r | |
489 | Status = EFI_BUFFER_TOO_SMALL;\r | |
490 | goto Exit;\r | |
491 | }\r | |
492 | *SizeOut = TpmOutSize;\r | |
493 | //\r | |
494 | // Continue reading the remaining data\r | |
495 | //\r | |
496 | while ( Index < TpmOutSize ) {\r | |
497 | for (; BurstCount > 0; BurstCount--) {\r | |
498 | *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r | |
499 | Index++;\r | |
500 | if (Index == TpmOutSize) {\r | |
501 | Status = EFI_SUCCESS;\r | |
502 | goto Exit;\r | |
503 | }\r | |
504 | }\r | |
505 | Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r | |
506 | if (EFI_ERROR (Status)) {\r | |
6f785cfc | 507 | Status = EFI_DEVICE_ERROR;\r |
c1d93242 JY |
508 | goto Exit;\r |
509 | }\r | |
510 | }\r | |
511 | Exit:\r | |
512 | DEBUG_CODE (\r | |
513 | DEBUG ((EFI_D_INFO, "Tpm12TisTpmCommand Receive - "));\r | |
514 | for (Index = 0; Index < TpmOutSize; Index++) {\r | |
515 | DEBUG ((EFI_D_INFO, "%02x ", BufferOut[Index]));\r | |
516 | }\r | |
517 | DEBUG ((EFI_D_INFO, "\n"));\r | |
518 | );\r | |
519 | MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r | |
520 | return Status;\r | |
521 | }\r | |
522 | \r | |
523 | /**\r | |
524 | This service enables the sending of commands to the TPM12.\r | |
525 | \r | |
526 | @param[in] InputParameterBlockSize Size of the TPM12 input parameter block.\r | |
527 | @param[in] InputParameterBlock Pointer to the TPM12 input parameter block.\r | |
528 | @param[in,out] OutputParameterBlockSize Size of the TPM12 output parameter block.\r | |
529 | @param[in] OutputParameterBlock Pointer to the TPM12 output parameter block.\r | |
530 | \r | |
531 | @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.\r | |
532 | @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.\r | |
533 | @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small. \r | |
534 | **/\r | |
535 | EFI_STATUS\r | |
536 | EFIAPI\r | |
537 | Tpm12SubmitCommand (\r | |
538 | IN UINT32 InputParameterBlockSize,\r | |
539 | IN UINT8 *InputParameterBlock,\r | |
540 | IN OUT UINT32 *OutputParameterBlockSize,\r | |
541 | IN UINT8 *OutputParameterBlock\r | |
542 | )\r | |
543 | {\r | |
544 | return Tpm12TisTpmCommand (\r | |
545 | (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r | |
546 | InputParameterBlock,\r | |
547 | InputParameterBlockSize,\r | |
548 | OutputParameterBlock,\r | |
549 | OutputParameterBlockSize\r | |
550 | );\r | |
551 | }\r | |
552 | \r | |
553 | /**\r | |
554 | This service requests use TPM12.\r | |
555 | \r | |
556 | @retval EFI_SUCCESS Get the control of TPM12 chip.\r | |
557 | @retval EFI_NOT_FOUND TPM12 not found.\r | |
558 | @retval EFI_DEVICE_ERROR Unexpected device behavior.\r | |
559 | **/\r | |
560 | EFI_STATUS\r | |
561 | EFIAPI\r | |
562 | Tpm12RequestUseTpm (\r | |
563 | VOID\r | |
564 | )\r | |
565 | {\r | |
566 | return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r | |
567 | }\r |