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c1d93242 JY |
1 | /** @file\r |
2 | TIS (TPM Interface Specification) functions used by TPM1.2.\r | |
b3548d32 LG |
3 | \r |
4 | Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
6aaac383 | 5 | (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r |
289b714b | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
c1d93242 JY |
7 | \r |
8 | **/\r | |
9 | \r | |
10 | #include <Uefi.h>\r | |
11 | #include <IndustryStandard/Tpm12.h>\r | |
12 | #include <Library/BaseLib.h>\r | |
13 | #include <Library/BaseMemoryLib.h>\r | |
14 | #include <Library/IoLib.h>\r | |
15 | #include <Library/TimerLib.h>\r | |
16 | #include <Library/DebugLib.h>\r | |
17 | #include <Library/Tpm12CommandLib.h>\r | |
18 | #include <Library/PcdLib.h>\r | |
19 | \r | |
8e997ab8 JY |
20 | #include <IndustryStandard/TpmPtp.h>\r |
21 | #include <IndustryStandard/TpmTis.h>\r | |
c1d93242 | 22 | \r |
8e997ab8 JY |
23 | typedef enum {\r |
24 | PtpInterfaceTis,\r | |
25 | PtpInterfaceFifo,\r | |
26 | PtpInterfaceCrb,\r | |
27 | PtpInterfaceMax,\r | |
28 | } PTP_INTERFACE_TYPE;\r | |
c1d93242 JY |
29 | \r |
30 | //\r | |
f9fd0c21 | 31 | // Max TPM command/response length\r |
c1d93242 JY |
32 | //\r |
33 | #define TPMCMDBUFLENGTH 1024\r | |
34 | \r | |
35 | /**\r | |
36 | Check whether TPM chip exist.\r | |
37 | \r | |
38 | @param[in] TisReg Pointer to TIS register.\r | |
39 | \r | |
40 | @retval TRUE TPM chip exists.\r | |
41 | @retval FALSE TPM chip is not found.\r | |
42 | **/\r | |
43 | BOOLEAN\r | |
44 | Tpm12TisPcPresenceCheck (\r | |
45 | IN TIS_PC_REGISTERS_PTR TisReg\r | |
46 | )\r | |
47 | {\r | |
48 | UINT8 RegRead;\r | |
b3548d32 | 49 | \r |
c1d93242 JY |
50 | RegRead = MmioRead8 ((UINTN)&TisReg->Access);\r |
51 | return (BOOLEAN)(RegRead != (UINT8)-1);\r | |
52 | }\r | |
53 | \r | |
e4780913 JY |
54 | /**\r |
55 | Return PTP interface type.\r | |
56 | \r | |
57 | @param[in] Register Pointer to PTP register.\r | |
58 | \r | |
59 | @return PTP interface type.\r | |
60 | **/\r | |
61 | PTP_INTERFACE_TYPE\r | |
62 | Tpm12GetPtpInterface (\r | |
63 | IN VOID *Register\r | |
64 | )\r | |
65 | {\r | |
66 | PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;\r | |
67 | PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;\r | |
68 | \r | |
69 | if (!Tpm12TisPcPresenceCheck (Register)) {\r | |
70 | return PtpInterfaceMax;\r | |
71 | }\r | |
72 | //\r | |
73 | // Check interface id\r | |
74 | //\r | |
75 | InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);\r | |
76 | InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);\r | |
77 | \r | |
78 | if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&\r | |
79 | (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&\r | |
80 | (InterfaceId.Bits.CapCRB != 0)) {\r | |
81 | return PtpInterfaceCrb;\r | |
82 | }\r | |
83 | if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&\r | |
84 | (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&\r | |
85 | (InterfaceId.Bits.CapFIFO != 0) &&\r | |
86 | (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {\r | |
87 | return PtpInterfaceFifo;\r | |
88 | }\r | |
89 | return PtpInterfaceTis;\r | |
90 | }\r | |
91 | \r | |
c1d93242 JY |
92 | /**\r |
93 | Check whether the value of a TPM chip register satisfies the input BIT setting.\r | |
94 | \r | |
95 | @param[in] Register Address port of register to be checked.\r | |
96 | @param[in] BitSet Check these data bits are set.\r | |
97 | @param[in] BitClear Check these data bits are clear.\r | |
98 | @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.\r | |
99 | \r | |
100 | @retval EFI_SUCCESS The register satisfies the check bit.\r | |
101 | @retval EFI_TIMEOUT The register can't run into the expected status in time.\r | |
102 | **/\r | |
103 | EFI_STATUS\r | |
c1d93242 JY |
104 | Tpm12TisPcWaitRegisterBits (\r |
105 | IN UINT8 *Register,\r | |
106 | IN UINT8 BitSet,\r | |
107 | IN UINT8 BitClear,\r | |
108 | IN UINT32 TimeOut\r | |
109 | )\r | |
110 | {\r | |
111 | UINT8 RegRead;\r | |
112 | UINT32 WaitTime;\r | |
113 | \r | |
114 | for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r | |
115 | RegRead = MmioRead8 ((UINTN)Register);\r | |
116 | if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)\r | |
117 | return EFI_SUCCESS;\r | |
118 | MicroSecondDelay (30);\r | |
119 | }\r | |
120 | return EFI_TIMEOUT;\r | |
121 | }\r | |
122 | \r | |
123 | /**\r | |
f9fd0c21 | 124 | Get BurstCount by reading the burstCount field of a TIS register\r |
c1d93242 JY |
125 | in the time of default TIS_TIMEOUT_D.\r |
126 | \r | |
127 | @param[in] TisReg Pointer to TIS register.\r | |
d6b926e7 | 128 | @param[out] BurstCount Pointer to a buffer to store the got BurstCount.\r |
c1d93242 JY |
129 | \r |
130 | @retval EFI_SUCCESS Get BurstCount.\r | |
131 | @retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.\r | |
132 | @retval EFI_TIMEOUT BurstCount can't be got in time.\r | |
133 | **/\r | |
134 | EFI_STATUS\r | |
c1d93242 JY |
135 | Tpm12TisPcReadBurstCount (\r |
136 | IN TIS_PC_REGISTERS_PTR TisReg,\r | |
137 | OUT UINT16 *BurstCount\r | |
138 | )\r | |
139 | {\r | |
140 | UINT32 WaitTime;\r | |
141 | UINT8 DataByte0;\r | |
142 | UINT8 DataByte1;\r | |
143 | \r | |
144 | if (BurstCount == NULL || TisReg == NULL) {\r | |
145 | return EFI_INVALID_PARAMETER;\r | |
146 | }\r | |
147 | \r | |
148 | WaitTime = 0;\r | |
149 | do {\r | |
150 | //\r | |
151 | // TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,\r | |
152 | // so it needs to use MmioRead8 to read two times\r | |
153 | //\r | |
154 | DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);\r | |
155 | DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);\r | |
156 | *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);\r | |
157 | if (*BurstCount != 0) {\r | |
158 | return EFI_SUCCESS;\r | |
159 | }\r | |
160 | MicroSecondDelay (30);\r | |
161 | WaitTime += 30;\r | |
162 | } while (WaitTime < TIS_TIMEOUT_D);\r | |
163 | \r | |
164 | return EFI_TIMEOUT;\r | |
165 | }\r | |
166 | \r | |
167 | /**\r | |
b3548d32 | 168 | Set TPM chip to ready state by sending ready command TIS_PC_STS_READY\r |
c1d93242 JY |
169 | to Status Register in time.\r |
170 | \r | |
171 | @param[in] TisReg Pointer to TIS register.\r | |
172 | \r | |
173 | @retval EFI_SUCCESS TPM chip enters into ready state.\r | |
174 | @retval EFI_INVALID_PARAMETER TisReg is NULL.\r | |
175 | @retval EFI_TIMEOUT TPM chip can't be set to ready state in time.\r | |
176 | **/\r | |
177 | EFI_STATUS\r | |
c1d93242 JY |
178 | Tpm12TisPcPrepareCommand (\r |
179 | IN TIS_PC_REGISTERS_PTR TisReg\r | |
180 | )\r | |
181 | {\r | |
182 | EFI_STATUS Status;\r | |
183 | \r | |
184 | if (TisReg == NULL) {\r | |
185 | return EFI_INVALID_PARAMETER;\r | |
186 | }\r | |
187 | \r | |
188 | MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r | |
189 | Status = Tpm12TisPcWaitRegisterBits (\r | |
190 | &TisReg->Status,\r | |
191 | TIS_PC_STS_READY,\r | |
192 | 0,\r | |
193 | TIS_TIMEOUT_B\r | |
194 | );\r | |
195 | return Status;\r | |
196 | }\r | |
197 | \r | |
198 | /**\r | |
b3548d32 | 199 | Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE\r |
c1d93242 JY |
200 | to ACCESS Register in the time of default TIS_TIMEOUT_A.\r |
201 | \r | |
202 | @param[in] TisReg Pointer to TIS register.\r | |
203 | \r | |
204 | @retval EFI_SUCCESS Get the control of TPM chip.\r | |
205 | @retval EFI_INVALID_PARAMETER TisReg is NULL.\r | |
206 | @retval EFI_NOT_FOUND TPM chip doesn't exit.\r | |
207 | @retval EFI_TIMEOUT Can't get the TPM control in time.\r | |
208 | **/\r | |
209 | EFI_STATUS\r | |
c1d93242 JY |
210 | Tpm12TisPcRequestUseTpm (\r |
211 | IN TIS_PC_REGISTERS_PTR TisReg\r | |
212 | )\r | |
213 | {\r | |
214 | EFI_STATUS Status;\r | |
b3548d32 | 215 | \r |
c1d93242 JY |
216 | if (TisReg == NULL) {\r |
217 | return EFI_INVALID_PARAMETER;\r | |
218 | }\r | |
b3548d32 | 219 | \r |
c1d93242 JY |
220 | if (!Tpm12TisPcPresenceCheck (TisReg)) {\r |
221 | return EFI_NOT_FOUND;\r | |
222 | }\r | |
223 | \r | |
224 | MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);\r | |
225 | Status = Tpm12TisPcWaitRegisterBits (\r | |
226 | &TisReg->Access,\r | |
227 | (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),\r | |
228 | 0,\r | |
229 | TIS_TIMEOUT_A\r | |
230 | );\r | |
231 | return Status;\r | |
232 | }\r | |
233 | \r | |
234 | /**\r | |
235 | Send a command to TPM for execution and return response data.\r | |
236 | \r | |
b3548d32 LG |
237 | @param[in] TisReg TPM register space base address.\r |
238 | @param[in] BufferIn Buffer for command data.\r | |
239 | @param[in] SizeIn Size of command data.\r | |
240 | @param[in, out] BufferOut Buffer for response data.\r | |
241 | @param[in, out] SizeOut Size of response data.\r | |
242 | \r | |
c1d93242 | 243 | @retval EFI_SUCCESS Operation completed successfully.\r |
c1d93242 JY |
244 | @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r |
245 | @retval EFI_DEVICE_ERROR Unexpected device behavior.\r | |
246 | @retval EFI_UNSUPPORTED Unsupported TPM version\r | |
247 | \r | |
248 | **/\r | |
249 | EFI_STATUS\r | |
250 | Tpm12TisTpmCommand (\r | |
251 | IN TIS_PC_REGISTERS_PTR TisReg,\r | |
252 | IN UINT8 *BufferIn,\r | |
253 | IN UINT32 SizeIn,\r | |
254 | IN OUT UINT8 *BufferOut,\r | |
255 | IN OUT UINT32 *SizeOut\r | |
256 | )\r | |
257 | {\r | |
258 | EFI_STATUS Status;\r | |
259 | UINT16 BurstCount;\r | |
260 | UINT32 Index;\r | |
261 | UINT32 TpmOutSize;\r | |
262 | UINT16 Data16;\r | |
263 | UINT32 Data32;\r | |
ee46ac08 | 264 | UINT16 RspTag;\r |
c1d93242 | 265 | \r |
f9f4fb23 | 266 | DEBUG_CODE_BEGIN ();\r |
c1d93242 JY |
267 | UINTN DebugSize;\r |
268 | \r | |
e905fbb0 | 269 | DEBUG ((DEBUG_VERBOSE, "Tpm12TisTpmCommand Send - "));\r |
c1d93242 JY |
270 | if (SizeIn > 0x100) {\r |
271 | DebugSize = 0x40;\r | |
272 | } else {\r | |
273 | DebugSize = SizeIn;\r | |
274 | }\r | |
275 | for (Index = 0; Index < DebugSize; Index++) {\r | |
e905fbb0 | 276 | DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));\r |
c1d93242 JY |
277 | }\r |
278 | if (DebugSize != SizeIn) {\r | |
e905fbb0 | 279 | DEBUG ((DEBUG_VERBOSE, "...... "));\r |
c1d93242 | 280 | for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r |
e905fbb0 | 281 | DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));\r |
c1d93242 JY |
282 | }\r |
283 | }\r | |
e905fbb0 | 284 | DEBUG ((DEBUG_VERBOSE, "\n"));\r |
f9f4fb23 | 285 | DEBUG_CODE_END ();\r |
c1d93242 JY |
286 | TpmOutSize = 0;\r |
287 | \r | |
288 | Status = Tpm12TisPcPrepareCommand (TisReg);\r | |
289 | if (EFI_ERROR (Status)){\r | |
290 | DEBUG ((DEBUG_ERROR, "Tpm12 is not ready for command!\n"));\r | |
6f785cfc | 291 | return EFI_DEVICE_ERROR;\r |
c1d93242 JY |
292 | }\r |
293 | //\r | |
294 | // Send the command data to Tpm\r | |
295 | //\r | |
296 | Index = 0;\r | |
297 | while (Index < SizeIn) {\r | |
298 | Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r | |
299 | if (EFI_ERROR (Status)) {\r | |
6f785cfc | 300 | Status = EFI_DEVICE_ERROR;\r |
c1d93242 JY |
301 | goto Exit;\r |
302 | }\r | |
303 | for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {\r | |
304 | MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));\r | |
305 | Index++;\r | |
306 | }\r | |
307 | }\r | |
308 | //\r | |
309 | // Check the Tpm status STS_EXPECT change from 1 to 0\r | |
310 | //\r | |
311 | Status = Tpm12TisPcWaitRegisterBits (\r | |
312 | &TisReg->Status,\r | |
313 | (UINT8) TIS_PC_VALID,\r | |
314 | TIS_PC_STS_EXPECT,\r | |
315 | TIS_TIMEOUT_C\r | |
316 | );\r | |
317 | if (EFI_ERROR (Status)) {\r | |
318 | DEBUG ((DEBUG_ERROR, "Tpm12 The send buffer too small!\n"));\r | |
319 | Status = EFI_BUFFER_TOO_SMALL;\r | |
320 | goto Exit;\r | |
321 | }\r | |
322 | //\r | |
323 | // Executed the TPM command and waiting for the response data ready\r | |
324 | //\r | |
325 | MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);\r | |
326 | Status = Tpm12TisPcWaitRegisterBits (\r | |
327 | &TisReg->Status,\r | |
328 | (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),\r | |
329 | 0,\r | |
330 | TIS_TIMEOUT_B\r | |
331 | );\r | |
332 | if (EFI_ERROR (Status)) {\r | |
333 | DEBUG ((DEBUG_ERROR, "Wait for Tpm12 response data time out!!\n"));\r | |
6f785cfc | 334 | Status = EFI_DEVICE_ERROR;\r |
c1d93242 JY |
335 | goto Exit;\r |
336 | }\r | |
337 | //\r | |
338 | // Get response data header\r | |
339 | //\r | |
340 | Index = 0;\r | |
341 | BurstCount = 0;\r | |
342 | while (Index < sizeof (TPM_RSP_COMMAND_HDR)) {\r | |
343 | Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r | |
344 | if (EFI_ERROR (Status)) {\r | |
6f785cfc | 345 | Status = EFI_DEVICE_ERROR;\r |
c1d93242 JY |
346 | goto Exit;\r |
347 | }\r | |
348 | for (; BurstCount > 0; BurstCount--) {\r | |
349 | *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r | |
350 | Index++;\r | |
351 | if (Index == sizeof (TPM_RSP_COMMAND_HDR)) break;\r | |
352 | }\r | |
353 | }\r | |
f9f4fb23 | 354 | DEBUG_CODE_BEGIN ();\r |
e905fbb0 | 355 | DEBUG ((DEBUG_VERBOSE, "Tpm12TisTpmCommand ReceiveHeader - "));\r |
c1d93242 | 356 | for (Index = 0; Index < sizeof (TPM_RSP_COMMAND_HDR); Index++) {\r |
e905fbb0 | 357 | DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));\r |
c1d93242 | 358 | }\r |
e905fbb0 | 359 | DEBUG ((DEBUG_VERBOSE, "\n"));\r |
f9f4fb23 | 360 | DEBUG_CODE_END ();\r |
c1d93242 | 361 | //\r |
ee46ac08 | 362 | // Check the response data header (tag, parasize and returncode)\r |
c1d93242 JY |
363 | //\r |
364 | CopyMem (&Data16, BufferOut, sizeof (UINT16));\r | |
ee46ac08 ZC |
365 | RspTag = SwapBytes16 (Data16);\r |
366 | if (RspTag != TPM_TAG_RSP_COMMAND && RspTag != TPM_TAG_RSP_AUTH1_COMMAND && RspTag != TPM_TAG_RSP_AUTH2_COMMAND) {\r | |
e905fbb0 | 367 | DEBUG ((DEBUG_ERROR, "TPM12: Response tag error - current tag value is %x\n", RspTag));\r |
c1d93242 JY |
368 | Status = EFI_UNSUPPORTED;\r |
369 | goto Exit;\r | |
370 | }\r | |
371 | \r | |
372 | CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));\r | |
373 | TpmOutSize = SwapBytes32 (Data32);\r | |
374 | if (*SizeOut < TpmOutSize) {\r | |
375 | Status = EFI_BUFFER_TOO_SMALL;\r | |
376 | goto Exit;\r | |
377 | }\r | |
378 | *SizeOut = TpmOutSize;\r | |
379 | //\r | |
380 | // Continue reading the remaining data\r | |
381 | //\r | |
382 | while ( Index < TpmOutSize ) {\r | |
383 | for (; BurstCount > 0; BurstCount--) {\r | |
384 | *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r | |
385 | Index++;\r | |
386 | if (Index == TpmOutSize) {\r | |
387 | Status = EFI_SUCCESS;\r | |
388 | goto Exit;\r | |
389 | }\r | |
390 | }\r | |
391 | Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r | |
392 | if (EFI_ERROR (Status)) {\r | |
6f785cfc | 393 | Status = EFI_DEVICE_ERROR;\r |
c1d93242 JY |
394 | goto Exit;\r |
395 | }\r | |
396 | }\r | |
397 | Exit:\r | |
f9f4fb23 | 398 | DEBUG_CODE_BEGIN ();\r |
e905fbb0 | 399 | DEBUG ((DEBUG_VERBOSE, "Tpm12TisTpmCommand Receive - "));\r |
c1d93242 | 400 | for (Index = 0; Index < TpmOutSize; Index++) {\r |
e905fbb0 | 401 | DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));\r |
c1d93242 | 402 | }\r |
e905fbb0 | 403 | DEBUG ((DEBUG_VERBOSE, "\n"));\r |
f9f4fb23 | 404 | DEBUG_CODE_END ();\r |
c1d93242 JY |
405 | MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r |
406 | return Status;\r | |
407 | }\r | |
408 | \r | |
409 | /**\r | |
410 | This service enables the sending of commands to the TPM12.\r | |
411 | \r | |
412 | @param[in] InputParameterBlockSize Size of the TPM12 input parameter block.\r | |
413 | @param[in] InputParameterBlock Pointer to the TPM12 input parameter block.\r | |
414 | @param[in,out] OutputParameterBlockSize Size of the TPM12 output parameter block.\r | |
415 | @param[in] OutputParameterBlock Pointer to the TPM12 output parameter block.\r | |
416 | \r | |
417 | @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.\r | |
418 | @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.\r | |
b3548d32 | 419 | @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.\r |
c1d93242 JY |
420 | **/\r |
421 | EFI_STATUS\r | |
422 | EFIAPI\r | |
423 | Tpm12SubmitCommand (\r | |
424 | IN UINT32 InputParameterBlockSize,\r | |
425 | IN UINT8 *InputParameterBlock,\r | |
426 | IN OUT UINT32 *OutputParameterBlockSize,\r | |
427 | IN UINT8 *OutputParameterBlock\r | |
428 | )\r | |
429 | {\r | |
e4780913 | 430 | PTP_INTERFACE_TYPE PtpInterface;\r |
c1d93242 | 431 | \r |
8e997ab8 | 432 | //\r |
e4780913 | 433 | // Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.\r |
8e997ab8 | 434 | //\r |
e4780913 JY |
435 | PtpInterface = Tpm12GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r |
436 | switch (PtpInterface) {\r | |
437 | case PtpInterfaceFifo:\r | |
438 | case PtpInterfaceTis:\r | |
439 | return Tpm12TisTpmCommand (\r | |
440 | (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r | |
441 | InputParameterBlock,\r | |
442 | InputParameterBlockSize,\r | |
443 | OutputParameterBlock,\r | |
444 | OutputParameterBlockSize\r | |
445 | );\r | |
446 | case PtpInterfaceCrb:\r | |
447 | //\r | |
448 | // No need to support CRB because it is only accept TPM2 command.\r | |
449 | //\r | |
450 | default:\r | |
451 | return EFI_DEVICE_ERROR;\r | |
8e997ab8 | 452 | }\r |
e4780913 | 453 | \r |
8e997ab8 JY |
454 | }\r |
455 | \r | |
456 | /**\r | |
457 | Check whether the value of a TPM chip register satisfies the input BIT setting.\r | |
458 | \r | |
459 | @param[in] Register Address port of register to be checked.\r | |
460 | @param[in] BitSet Check these data bits are set.\r | |
461 | @param[in] BitClear Check these data bits are clear.\r | |
462 | @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.\r | |
463 | \r | |
464 | @retval EFI_SUCCESS The register satisfies the check bit.\r | |
465 | @retval EFI_TIMEOUT The register can't run into the expected status in time.\r | |
466 | **/\r | |
467 | EFI_STATUS\r | |
468 | Tpm12PtpCrbWaitRegisterBits (\r | |
469 | IN UINT32 *Register,\r | |
470 | IN UINT32 BitSet,\r | |
471 | IN UINT32 BitClear,\r | |
472 | IN UINT32 TimeOut\r | |
473 | )\r | |
474 | {\r | |
475 | UINT32 RegRead;\r | |
476 | UINT32 WaitTime;\r | |
477 | \r | |
478 | for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r | |
479 | RegRead = MmioRead32 ((UINTN)Register);\r | |
480 | if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {\r | |
481 | return EFI_SUCCESS;\r | |
482 | }\r | |
483 | MicroSecondDelay (30);\r | |
484 | }\r | |
485 | return EFI_TIMEOUT;\r | |
486 | }\r | |
487 | \r | |
488 | /**\r | |
489 | Get the control of TPM chip.\r | |
490 | \r | |
491 | @param[in] CrbReg Pointer to CRB register.\r | |
492 | \r | |
493 | @retval EFI_SUCCESS Get the control of TPM chip.\r | |
494 | @retval EFI_INVALID_PARAMETER CrbReg is NULL.\r | |
495 | @retval EFI_NOT_FOUND TPM chip doesn't exit.\r | |
496 | @retval EFI_TIMEOUT Can't get the TPM control in time.\r | |
497 | **/\r | |
498 | EFI_STATUS\r | |
499 | Tpm12PtpCrbRequestUseTpm (\r | |
500 | IN PTP_CRB_REGISTERS_PTR CrbReg\r | |
501 | )\r | |
502 | {\r | |
503 | EFI_STATUS Status;\r | |
504 | \r | |
505 | MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);\r | |
506 | Status = Tpm12PtpCrbWaitRegisterBits (\r | |
507 | &CrbReg->LocalityStatus,\r | |
508 | PTP_CRB_LOCALITY_STATUS_GRANTED,\r | |
509 | 0,\r | |
510 | PTP_TIMEOUT_A\r | |
511 | );\r | |
512 | return Status;\r | |
513 | }\r | |
514 | \r | |
c1d93242 JY |
515 | /**\r |
516 | This service requests use TPM12.\r | |
517 | \r | |
518 | @retval EFI_SUCCESS Get the control of TPM12 chip.\r | |
519 | @retval EFI_NOT_FOUND TPM12 not found.\r | |
520 | @retval EFI_DEVICE_ERROR Unexpected device behavior.\r | |
521 | **/\r | |
522 | EFI_STATUS\r | |
523 | EFIAPI\r | |
524 | Tpm12RequestUseTpm (\r | |
525 | VOID\r | |
526 | )\r | |
527 | {\r | |
8e997ab8 JY |
528 | PTP_INTERFACE_TYPE PtpInterface;\r |
529 | \r | |
530 | //\r | |
531 | // Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.\r | |
532 | // Some other program might leverage this function to check the existence of TPM chip.\r | |
533 | //\r | |
534 | PtpInterface = Tpm12GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r | |
535 | switch (PtpInterface) {\r | |
536 | case PtpInterfaceCrb:\r | |
537 | return Tpm12PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r | |
538 | case PtpInterfaceFifo:\r | |
539 | case PtpInterfaceTis:\r | |
540 | return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r | |
541 | default:\r | |
542 | return EFI_NOT_FOUND;\r | |
543 | }\r | |
c1d93242 | 544 | }\r |