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1 | /** @file\r |
2 | Header file for Registers and Structure definitions\r | |
3 | \r | |
4 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | #ifndef __OPAL_PASSWORD_NVME_REG_H__\r | |
15 | #define __OPAL_PASSWORD_NVME_REG_H__\r | |
16 | \r | |
17 | //\r | |
18 | // PCI Header for PCIe root port configuration\r | |
19 | //\r | |
20 | #define NVME_PCIE_PCICMD 0x04\r | |
21 | #define NVME_PCIE_BNUM 0x18\r | |
22 | #define NVME_PCIE_SEC_BNUM 0x19\r | |
23 | #define NVME_PCIE_IOBL 0x1C\r | |
24 | #define NVME_PCIE_MBL 0x20\r | |
25 | #define NVME_PCIE_PMBL 0x24\r | |
26 | #define NVME_PCIE_PMBU32 0x28\r | |
27 | #define NVME_PCIE_PMLU32 0x2C\r | |
28 | #define NVME_PCIE_INTR 0x3C\r | |
29 | \r | |
30 | //\r | |
31 | // NVMe related definitions\r | |
32 | //\r | |
33 | #define PCI_CLASS_MASS_STORAGE_NVM 0x08 // mass storage sub-class non-volatile memory.\r | |
34 | #define PCI_IF_NVMHCI 0x02 // mass storage programming interface NVMHCI.\r | |
35 | \r | |
36 | #define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based\r | |
37 | #define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based\r | |
38 | \r | |
39 | #define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based\r | |
40 | #define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based\r | |
41 | \r | |
42 | #define NVME_MAX_IO_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ\r | |
43 | \r | |
44 | #define NVME_CSQ_DEPTH (NVME_CSQ_SIZE+1)\r | |
45 | #define NVME_CCQ_DEPTH (NVME_CCQ_SIZE+1)\r | |
46 | #define NVME_PRP_SIZE (4) // Pages of PRP list\r | |
47 | \r | |
48 | #define NVME_CONTROLLER_ID 0\r | |
49 | \r | |
50 | //\r | |
51 | // Time out Value for Nvme transaction execution\r | |
52 | //\r | |
53 | #define NVME_GENERIC_TIMEOUT 5000000 ///< us\r | |
54 | #define NVME_CMD_WAIT 100 ///< us\r | |
55 | #define NVME_CMD_TIMEOUT 20000000 ///< us\r | |
56 | \r | |
57 | \r | |
58 | \r | |
59 | #define NVME_MEM_MAX_SIZE \\r | |
60 | (( \\r | |
61 | 1 /* Controller Data */ + \\r | |
62 | 1 /* Identify Data */ + \\r | |
63 | 1 /* ASQ */ + \\r | |
64 | 1 /* ACQ */ + \\r | |
65 | 1 /* SQs */ + \\r | |
66 | 1 /* CQs */ + \\r | |
67 | NVME_PRP_SIZE * NVME_CSQ_DEPTH /* PRPs */ + \\r | |
68 | 1 /* SECURITY */ \\r | |
69 | ) * EFI_PAGE_SIZE)\r | |
70 | \r | |
71 | \r | |
72 | //\r | |
73 | // controller register offsets\r | |
74 | //\r | |
75 | #define NVME_CAP_OFFSET 0x0000 // Controller Capabilities\r | |
76 | #define NVME_VER_OFFSET 0x0008 // Version\r | |
77 | #define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set\r | |
78 | #define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear\r | |
79 | #define NVME_CC_OFFSET 0x0014 // Controller Configuration\r | |
80 | #define NVME_CSTS_OFFSET 0x001c // Controller Status\r | |
81 | #define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes\r | |
82 | #define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address\r | |
83 | #define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address\r | |
84 | #define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell\r | |
85 | #define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell\r | |
86 | \r | |
87 | //\r | |
88 | // These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))\r | |
89 | // Get the doorbell stride bit shift Value from the controller capabilities.\r | |
90 | //\r | |
91 | #define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell\r | |
92 | #define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell\r | |
93 | \r | |
94 | \r | |
95 | #pragma pack(1)\r | |
96 | \r | |
97 | //\r | |
98 | // 3.1.1 Offset 00h: CAP - Controller Capabilities\r | |
99 | //\r | |
100 | typedef struct {\r | |
101 | UINT16 Mqes; // Maximum Queue Entries Supported\r | |
102 | UINT8 Cqr:1; // Contiguous Queues Required\r | |
103 | UINT8 Ams:2; // Arbitration Mechanism Supported\r | |
104 | UINT8 Rsvd1:5;\r | |
105 | UINT8 To; // Timeout\r | |
106 | UINT16 Dstrd:4;\r | |
107 | UINT16 Rsvd2:1;\r | |
108 | UINT16 Css:4; // Command Sets Supported\r | |
109 | UINT16 Rsvd3:7;\r | |
110 | UINT8 Mpsmin:4;\r | |
111 | UINT8 Mpsmax:4;\r | |
112 | UINT8 Rsvd4;\r | |
113 | } NVME_CAP;\r | |
114 | \r | |
115 | //\r | |
116 | // 3.1.2 Offset 08h: VS - Version\r | |
117 | //\r | |
118 | typedef struct {\r | |
119 | UINT16 Mnr; // Minor version number\r | |
120 | UINT16 Mjr; // Major version number\r | |
121 | } NVME_VER;\r | |
122 | \r | |
123 | //\r | |
124 | // 3.1.5 Offset 14h: CC - Controller Configuration\r | |
125 | //\r | |
126 | typedef struct {\r | |
127 | UINT16 En:1; // Enable\r | |
128 | UINT16 Rsvd1:3;\r | |
129 | UINT16 Css:3; // Command Set Selected\r | |
130 | UINT16 Mps:4; // Memory Page Size\r | |
131 | UINT16 Ams:3; // Arbitration Mechanism Selected\r | |
132 | UINT16 Shn:2; // Shutdown Notification\r | |
133 | UINT8 Iosqes:4; // I/O Submission Queue Entry Size\r | |
134 | UINT8 Iocqes:4; // I/O Completion Queue Entry Size\r | |
135 | UINT8 Rsvd2;\r | |
136 | } NVME_CC;\r | |
137 | \r | |
138 | //\r | |
139 | // 3.1.6 Offset 1Ch: CSTS - Controller Status\r | |
140 | //\r | |
141 | typedef struct {\r | |
142 | UINT32 Rdy:1; // Ready\r | |
143 | UINT32 Cfs:1; // Controller Fatal Status\r | |
144 | UINT32 Shst:2; // Shutdown Status\r | |
145 | UINT32 Nssro:1; // NVM Subsystem Reset Occurred\r | |
146 | UINT32 Rsvd1:27;\r | |
147 | } NVME_CSTS;\r | |
148 | \r | |
149 | //\r | |
150 | // 3.1.8 Offset 24h: AQA - Admin Queue Attributes\r | |
151 | //\r | |
152 | typedef struct {\r | |
153 | UINT16 Asqs:12; // Submission Queue Size\r | |
154 | UINT16 Rsvd1:4;\r | |
155 | UINT16 Acqs:12; // Completion Queue Size\r | |
156 | UINT16 Rsvd2:4;\r | |
157 | } NVME_AQA;\r | |
158 | \r | |
159 | //\r | |
160 | // 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address\r | |
161 | //\r | |
162 | #define NVME_ASQ UINT64\r | |
163 | \r | |
164 | //\r | |
165 | // 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address\r | |
166 | //\r | |
167 | #define NVME_ACQ UINT64\r | |
168 | \r | |
169 | //\r | |
170 | // 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r | |
171 | //\r | |
172 | typedef struct {\r | |
173 | UINT16 Sqt;\r | |
174 | UINT16 Rsvd1;\r | |
175 | } NVME_SQTDBL;\r | |
176 | \r | |
177 | //\r | |
178 | // 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell\r | |
179 | //\r | |
180 | typedef struct {\r | |
181 | UINT16 Cqh;\r | |
182 | UINT16 Rsvd1;\r | |
183 | } NVME_CQHDBL;\r | |
184 | \r | |
185 | //\r | |
186 | // NVM command set structures\r | |
187 | //\r | |
188 | // Read Command\r | |
189 | //\r | |
190 | typedef struct {\r | |
191 | //\r | |
192 | // CDW 10, 11\r | |
193 | //\r | |
194 | UINT64 Slba; /* Starting Sector Address */\r | |
195 | //\r | |
196 | // CDW 12\r | |
197 | //\r | |
198 | UINT16 Nlb; /* Number of Sectors */\r | |
199 | UINT16 Rsvd1:10;\r | |
200 | UINT16 Prinfo:4; /* Protection Info Check */\r | |
201 | UINT16 Fua:1; /* Force Unit Access */\r | |
202 | UINT16 Lr:1; /* Limited Retry */\r | |
203 | //\r | |
204 | // CDW 13\r | |
205 | //\r | |
206 | UINT32 Af:4; /* Access Frequency */\r | |
207 | UINT32 Al:2; /* Access Latency */\r | |
208 | UINT32 Sr:1; /* Sequential Request */\r | |
209 | UINT32 In:1; /* Incompressible */\r | |
210 | UINT32 Rsvd2:24;\r | |
211 | //\r | |
212 | // CDW 14\r | |
213 | //\r | |
214 | UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r | |
215 | //\r | |
216 | // CDW 15\r | |
217 | //\r | |
218 | UINT16 Elbat; /* Expected Logical Block Application Tag */\r | |
219 | UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r | |
220 | } NVME_READ;\r | |
221 | \r | |
222 | //\r | |
223 | // Write Command\r | |
224 | //\r | |
225 | typedef struct {\r | |
226 | //\r | |
227 | // CDW 10, 11\r | |
228 | //\r | |
229 | UINT64 Slba; /* Starting Sector Address */\r | |
230 | //\r | |
231 | // CDW 12\r | |
232 | //\r | |
233 | UINT16 Nlb; /* Number of Sectors */\r | |
234 | UINT16 Rsvd1:10;\r | |
235 | UINT16 Prinfo:4; /* Protection Info Check */\r | |
236 | UINT16 Fua:1; /* Force Unit Access */\r | |
237 | UINT16 Lr:1; /* Limited Retry */\r | |
238 | //\r | |
239 | // CDW 13\r | |
240 | //\r | |
241 | UINT32 Af:4; /* Access Frequency */\r | |
242 | UINT32 Al:2; /* Access Latency */\r | |
243 | UINT32 Sr:1; /* Sequential Request */\r | |
244 | UINT32 In:1; /* Incompressible */\r | |
245 | UINT32 Rsvd2:24;\r | |
246 | //\r | |
247 | // CDW 14\r | |
248 | //\r | |
249 | UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r | |
250 | //\r | |
251 | // CDW 15\r | |
252 | //\r | |
253 | UINT16 Lbat; /* Logical Block Application Tag */\r | |
254 | UINT16 Lbatm; /* Logical Block Application Tag Mask */\r | |
255 | } NVME_WRITE;\r | |
256 | \r | |
257 | //\r | |
258 | // Flush\r | |
259 | //\r | |
260 | typedef struct {\r | |
261 | //\r | |
262 | // CDW 10\r | |
263 | //\r | |
264 | UINT32 Flush; /* Flush */\r | |
265 | } NVME_FLUSH;\r | |
266 | \r | |
267 | //\r | |
268 | // Write Uncorrectable command\r | |
269 | //\r | |
270 | typedef struct {\r | |
271 | //\r | |
272 | // CDW 10, 11\r | |
273 | //\r | |
274 | UINT64 Slba; /* Starting LBA */\r | |
275 | //\r | |
276 | // CDW 12\r | |
277 | //\r | |
278 | UINT32 Nlb:16; /* Number of Logical Blocks */\r | |
279 | UINT32 Rsvd1:16;\r | |
280 | } NVME_WRITE_UNCORRECTABLE;\r | |
281 | \r | |
282 | //\r | |
283 | // Write Zeroes command\r | |
284 | //\r | |
285 | typedef struct {\r | |
286 | //\r | |
287 | // CDW 10, 11\r | |
288 | //\r | |
289 | UINT64 Slba; /* Starting LBA */\r | |
290 | //\r | |
291 | // CDW 12\r | |
292 | //\r | |
293 | UINT16 Nlb; /* Number of Logical Blocks */\r | |
294 | UINT16 Rsvd1:10;\r | |
295 | UINT16 Prinfo:4; /* Protection Info Check */\r | |
296 | UINT16 Fua:1; /* Force Unit Access */\r | |
297 | UINT16 Lr:1; /* Limited Retry */\r | |
298 | //\r | |
299 | // CDW 13\r | |
300 | //\r | |
301 | UINT32 Rsvd2;\r | |
302 | //\r | |
303 | // CDW 14\r | |
304 | //\r | |
305 | UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r | |
306 | //\r | |
307 | // CDW 15\r | |
308 | //\r | |
309 | UINT16 Lbat; /* Logical Block Application Tag */\r | |
310 | UINT16 Lbatm; /* Logical Block Application Tag Mask */\r | |
311 | } NVME_WRITE_ZEROES;\r | |
312 | \r | |
313 | //\r | |
314 | // Compare command\r | |
315 | //\r | |
316 | typedef struct {\r | |
317 | //\r | |
318 | // CDW 10, 11\r | |
319 | //\r | |
320 | UINT64 Slba; /* Starting LBA */\r | |
321 | //\r | |
322 | // CDW 12\r | |
323 | //\r | |
324 | UINT16 Nlb; /* Number of Logical Blocks */\r | |
325 | UINT16 Rsvd1:10;\r | |
326 | UINT16 Prinfo:4; /* Protection Info Check */\r | |
327 | UINT16 Fua:1; /* Force Unit Access */\r | |
328 | UINT16 Lr:1; /* Limited Retry */\r | |
329 | //\r | |
330 | // CDW 13\r | |
331 | //\r | |
332 | UINT32 Rsvd2;\r | |
333 | //\r | |
334 | // CDW 14\r | |
335 | //\r | |
336 | UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r | |
337 | //\r | |
338 | // CDW 15\r | |
339 | //\r | |
340 | UINT16 Elbat; /* Expected Logical Block Application Tag */\r | |
341 | UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r | |
342 | } NVME_COMPARE;\r | |
343 | \r | |
344 | typedef union {\r | |
345 | NVME_READ Read;\r | |
346 | NVME_WRITE Write;\r | |
347 | NVME_FLUSH Flush;\r | |
348 | NVME_WRITE_UNCORRECTABLE WriteUncorrectable;\r | |
349 | NVME_WRITE_ZEROES WriteZeros;\r | |
350 | NVME_COMPARE Compare;\r | |
351 | } NVME_CMD;\r | |
352 | \r | |
353 | typedef struct {\r | |
354 | UINT16 Mp; /* Maximum Power */\r | |
355 | UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */\r | |
356 | UINT8 Mps:1; /* Max Power Scale */\r | |
357 | UINT8 Nops:1; /* Non-Operational State */\r | |
358 | UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */\r | |
359 | UINT32 Enlat; /* Entry Latency */\r | |
360 | UINT32 Exlat; /* Exit Latency */\r | |
361 | UINT8 Rrt:5; /* Relative Read Throughput */\r | |
362 | UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */\r | |
363 | UINT8 Rrl:5; /* Relative Read Leatency */\r | |
364 | UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */\r | |
365 | UINT8 Rwt:5; /* Relative Write Throughput */\r | |
366 | UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */\r | |
367 | UINT8 Rwl:5; /* Relative Write Leatency */\r | |
368 | UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */\r | |
369 | UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */\r | |
370 | } NVME_PSDESCRIPTOR;\r | |
371 | \r | |
372 | //\r | |
373 | // Identify Controller Data\r | |
374 | //\r | |
375 | typedef struct {\r | |
376 | //\r | |
377 | // Controller Capabilities and Features 0-255\r | |
378 | //\r | |
379 | UINT16 Vid; /* PCI Vendor ID */\r | |
380 | UINT16 Ssvid; /* PCI sub-system vendor ID */\r | |
381 | UINT8 Sn[20]; /* Produce serial number */\r | |
382 | \r | |
383 | UINT8 Mn[40]; /* Proeduct model number */\r | |
384 | UINT8 Fr[8]; /* Firmware Revision */\r | |
385 | UINT8 Rab; /* Recommended Arbitration Burst */\r | |
386 | UINT8 Ieee_oiu[3]; /* Organization Unique Identifier */\r | |
387 | UINT8 Cmic; /* Multi-interface Capabilities */\r | |
388 | UINT8 Mdts; /* Maximum Data Transfer Size */\r | |
389 | UINT8 Cntlid[2]; /* Controller ID */\r | |
390 | UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */\r | |
391 | //\r | |
392 | // Admin Command Set Attributes\r | |
393 | //\r | |
394 | UINT16 Oacs; /* Optional Admin Command Support */\r | |
395 | UINT8 Acl; /* Abort Command Limit */\r | |
396 | UINT8 Aerl; /* Async Event Request Limit */\r | |
397 | UINT8 Frmw; /* Firmware updates */\r | |
398 | UINT8 Lpa; /* Log Page Attributes */\r | |
399 | UINT8 Elpe; /* Error Log Page Entries */\r | |
400 | UINT8 Npss; /* Number of Power States Support */\r | |
401 | UINT8 Avscc; /* Admin Vendor Specific Command Configuration */\r | |
402 | UINT8 Apsta; /* Autonomous Power State Transition Attributes */\r | |
403 | UINT8 Rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */\r | |
404 | //\r | |
405 | // NVM Command Set Attributes\r | |
406 | //\r | |
407 | UINT8 Sqes; /* Submission Queue Entry Size */\r | |
408 | UINT8 Cqes; /* Completion Queue Entry Size */\r | |
409 | UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */\r | |
410 | UINT32 Nn; /* Number of Namespaces */\r | |
411 | UINT16 Oncs; /* Optional NVM Command Support */\r | |
412 | UINT16 Fuses; /* Fused Operation Support */\r | |
413 | UINT8 Fna; /* Format NVM Attributes */\r | |
414 | UINT8 Vwc; /* Volatile Write Cache */\r | |
415 | UINT16 Awun; /* Atomic Write Unit Normal */\r | |
416 | UINT16 Awupf; /* Atomic Write Unit Power Fail */\r | |
417 | UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */\r | |
418 | UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */\r | |
419 | UINT16 Acwu; /* Atomic Compare & Write Unit */\r | |
420 | UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */\r | |
421 | UINT32 Sgls; /* SGL Support */\r | |
422 | UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */\r | |
423 | //\r | |
424 | // I/O Command set Attributes\r | |
425 | //\r | |
426 | UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */\r | |
427 | //\r | |
428 | // Power State Descriptors\r | |
429 | //\r | |
430 | NVME_PSDESCRIPTOR PsDescriptor[32];\r | |
431 | \r | |
432 | UINT8 VendorData[1024]; /* Vendor specific Data */\r | |
433 | } NVME_ADMIN_CONTROLLER_DATA;\r | |
434 | \r | |
435 | typedef struct {\r | |
436 | UINT16 Security : 1; /* supports security send/receive commands */\r | |
437 | UINT16 Format : 1; /* supports format nvm command */\r | |
438 | UINT16 Firmware : 1; /* supports firmware activate/download commands */\r | |
439 | UINT16 Oacs_rsvd : 13;\r | |
440 | } OACS; // optional admin command support: NVME_ADMIN_CONTROLLER_DATA.Oacs\r | |
441 | \r | |
442 | typedef struct {\r | |
443 | UINT16 Ms; /* Metadata Size */\r | |
444 | UINT8 Lbads; /* LBA Data Size */\r | |
445 | UINT8 Rp:2; /* Relative Performance */\r | |
446 | #define LBAF_RP_BEST 00b\r | |
447 | #define LBAF_RP_BETTER 01b\r | |
448 | #define LBAF_RP_GOOD 10b\r | |
449 | #define LBAF_RP_DEGRADED 11b\r | |
450 | UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */\r | |
451 | } NVME_LBAFORMAT;\r | |
452 | \r | |
453 | //\r | |
454 | // Identify Namespace Data\r | |
455 | //\r | |
456 | typedef struct {\r | |
457 | //\r | |
458 | // NVM Command Set Specific\r | |
459 | //\r | |
460 | UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */\r | |
461 | UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */\r | |
462 | UINT64 Nuse; /* Namespace Utilization */\r | |
463 | UINT8 Nsfeat; /* Namespace Features */\r | |
464 | UINT8 Nlbaf; /* Number of LBA Formats */\r | |
465 | UINT8 Flbas; /* Formatted LBA Size */\r | |
466 | UINT8 Mc; /* Metadata Capabilities */\r | |
467 | UINT8 Dpc; /* End-to-end Data Protection capabilities */\r | |
468 | UINT8 Dps; /* End-to-end Data Protection Type Settings */\r | |
469 | UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */\r | |
470 | UINT8 Rescap; /* Reservation Capabilities */\r | |
471 | UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */\r | |
472 | UINT64 Eui64; /* IEEE Extended Unique Identifier */\r | |
473 | //\r | |
474 | // LBA Format\r | |
475 | //\r | |
476 | NVME_LBAFORMAT LbaFormat[16];\r | |
477 | \r | |
478 | UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */\r | |
479 | UINT8 VendorData[3712]; /* Vendor specific Data */\r | |
480 | } NVME_ADMIN_NAMESPACE_DATA;\r | |
481 | \r | |
482 | //\r | |
483 | // NvmExpress Admin Identify Cmd\r | |
484 | //\r | |
485 | typedef struct {\r | |
486 | //\r | |
487 | // CDW 10\r | |
488 | //\r | |
489 | UINT32 Cns:2;\r | |
490 | UINT32 Rsvd1:30;\r | |
491 | } NVME_ADMIN_IDENTIFY;\r | |
492 | \r | |
493 | //\r | |
494 | // NvmExpress Admin Create I/O Completion Queue\r | |
495 | //\r | |
496 | typedef struct {\r | |
497 | //\r | |
498 | // CDW 10\r | |
499 | //\r | |
500 | UINT32 Qid:16; /* Queue Identifier */\r | |
501 | UINT32 Qsize:16; /* Queue Size */\r | |
502 | \r | |
503 | //\r | |
504 | // CDW 11\r | |
505 | //\r | |
506 | UINT32 Pc:1; /* Physically Contiguous */\r | |
507 | UINT32 Ien:1; /* Interrupts Enabled */\r | |
508 | UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */\r | |
509 | UINT32 Iv:16; /* Interrupt Vector */\r | |
510 | } NVME_ADMIN_CRIOCQ;\r | |
511 | \r | |
512 | //\r | |
513 | // NvmExpress Admin Create I/O Submission Queue\r | |
514 | //\r | |
515 | typedef struct {\r | |
516 | //\r | |
517 | // CDW 10\r | |
518 | //\r | |
519 | UINT32 Qid:16; /* Queue Identifier */\r | |
520 | UINT32 Qsize:16; /* Queue Size */\r | |
521 | \r | |
522 | //\r | |
523 | // CDW 11\r | |
524 | //\r | |
525 | UINT32 Pc:1; /* Physically Contiguous */\r | |
526 | UINT32 Qprio:2; /* Queue Priority */\r | |
527 | UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */\r | |
528 | UINT32 Cqid:16; /* Completion Queue ID */\r | |
529 | } NVME_ADMIN_CRIOSQ;\r | |
530 | \r | |
531 | //\r | |
532 | // NvmExpress Admin Delete I/O Completion Queue\r | |
533 | //\r | |
534 | typedef struct {\r | |
535 | //\r | |
536 | // CDW 10\r | |
537 | //\r | |
538 | UINT16 Qid;\r | |
539 | UINT16 Rsvd1;\r | |
540 | } NVME_ADMIN_DEIOCQ;\r | |
541 | \r | |
542 | //\r | |
543 | // NvmExpress Admin Delete I/O Submission Queue\r | |
544 | //\r | |
545 | typedef struct {\r | |
546 | //\r | |
547 | // CDW 10\r | |
548 | //\r | |
549 | UINT16 Qid;\r | |
550 | UINT16 Rsvd1;\r | |
551 | } NVME_ADMIN_DEIOSQ;\r | |
552 | \r | |
553 | //\r | |
554 | // NvmExpress Admin Security Send\r | |
555 | //\r | |
556 | typedef struct {\r | |
557 | //\r | |
558 | // CDW 10\r | |
559 | //\r | |
560 | UINT32 Resv:8; /* Reserve */\r | |
561 | UINT32 Spsp:16; /* SP Specific */\r | |
562 | UINT32 Secp:8; /* Security Protocol */\r | |
563 | \r | |
564 | //\r | |
565 | // CDW 11\r | |
566 | //\r | |
567 | UINT32 Tl; /* Transfer Length */\r | |
568 | } NVME_ADMIN_SECSEND;\r | |
569 | \r | |
570 | //\r | |
571 | // NvmExpress Admin Abort Command\r | |
572 | //\r | |
573 | typedef struct {\r | |
574 | //\r | |
575 | // CDW 10\r | |
576 | //\r | |
577 | UINT32 Sqid:16; /* Submission Queue identifier */\r | |
578 | UINT32 Cid:16; /* Command Identifier */\r | |
579 | } NVME_ADMIN_ABORT;\r | |
580 | \r | |
581 | //\r | |
582 | // NvmExpress Admin Firmware Activate Command\r | |
583 | //\r | |
584 | typedef struct {\r | |
585 | //\r | |
586 | // CDW 10\r | |
587 | //\r | |
588 | UINT32 Fs:3; /* Submission Queue identifier */\r | |
589 | UINT32 Aa:2; /* Command Identifier */\r | |
590 | UINT32 Rsvd1:27;\r | |
591 | } NVME_ADMIN_FIRMWARE_ACTIVATE;\r | |
592 | \r | |
593 | //\r | |
594 | // NvmExpress Admin Firmware Image Download Command\r | |
595 | //\r | |
596 | typedef struct {\r | |
597 | //\r | |
598 | // CDW 10\r | |
599 | //\r | |
600 | UINT32 Numd; /* Number of Dwords */\r | |
601 | //\r | |
602 | // CDW 11\r | |
603 | //\r | |
604 | UINT32 Ofst; /* Offset */\r | |
605 | } NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;\r | |
606 | \r | |
607 | //\r | |
608 | // NvmExpress Admin Get Features Command\r | |
609 | //\r | |
610 | typedef struct {\r | |
611 | //\r | |
612 | // CDW 10\r | |
613 | //\r | |
614 | UINT32 Fid:8; /* Feature Identifier */\r | |
615 | UINT32 Sel:3; /* Select */\r | |
616 | UINT32 Rsvd1:21;\r | |
617 | } NVME_ADMIN_GET_FEATURES;\r | |
618 | \r | |
619 | //\r | |
620 | // NvmExpress Admin Get Log Page Command\r | |
621 | //\r | |
622 | typedef struct {\r | |
623 | //\r | |
624 | // CDW 10\r | |
625 | //\r | |
626 | UINT32 Lid:8; /* Log Page Identifier */\r | |
627 | #define LID_ERROR_INFO\r | |
628 | #define LID_SMART_INFO\r | |
629 | #define LID_FW_SLOT_INFO\r | |
630 | UINT32 Rsvd1:8;\r | |
631 | UINT32 Numd:12; /* Number of Dwords */\r | |
632 | UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */\r | |
633 | } NVME_ADMIN_GET_LOG_PAGE;\r | |
634 | \r | |
635 | //\r | |
636 | // NvmExpress Admin Set Features Command\r | |
637 | //\r | |
638 | typedef struct {\r | |
639 | //\r | |
640 | // CDW 10\r | |
641 | //\r | |
642 | UINT32 Fid:8; /* Feature Identifier */\r | |
643 | UINT32 Rsvd1:23;\r | |
644 | UINT32 Sv:1; /* Save */\r | |
645 | } NVME_ADMIN_SET_FEATURES;\r | |
646 | \r | |
647 | //\r | |
648 | // NvmExpress Admin Format NVM Command\r | |
649 | //\r | |
650 | typedef struct {\r | |
651 | //\r | |
652 | // CDW 10\r | |
653 | //\r | |
654 | UINT32 Lbaf:4; /* LBA Format */\r | |
655 | UINT32 Ms:1; /* Metadata Settings */\r | |
656 | UINT32 Pi:3; /* Protection Information */\r | |
657 | UINT32 Pil:1; /* Protection Information Location */\r | |
658 | UINT32 Ses:3; /* Secure Erase Settings */\r | |
659 | UINT32 Rsvd1:20;\r | |
660 | } NVME_ADMIN_FORMAT_NVM;\r | |
661 | \r | |
662 | //\r | |
663 | // NvmExpress Admin Security Receive Command\r | |
664 | //\r | |
665 | typedef struct {\r | |
666 | //\r | |
667 | // CDW 10\r | |
668 | //\r | |
669 | UINT32 Rsvd1:8;\r | |
670 | UINT32 Spsp:16; /* SP Specific */\r | |
671 | UINT32 Secp:8; /* Security Protocol */\r | |
672 | //\r | |
673 | // CDW 11\r | |
674 | //\r | |
675 | UINT32 Al; /* Allocation Length */\r | |
676 | } NVME_ADMIN_SECURITY_RECEIVE;\r | |
677 | \r | |
678 | //\r | |
679 | // NvmExpress Admin Security Send Command\r | |
680 | //\r | |
681 | typedef struct {\r | |
682 | //\r | |
683 | // CDW 10\r | |
684 | //\r | |
685 | UINT32 Rsvd1:8;\r | |
686 | UINT32 Spsp:16; /* SP Specific */\r | |
687 | UINT32 Secp:8; /* Security Protocol */\r | |
688 | //\r | |
689 | // CDW 11\r | |
690 | //\r | |
691 | UINT32 Tl; /* Transfer Length */\r | |
692 | } NVME_ADMIN_SECURITY_SEND;\r | |
693 | \r | |
694 | typedef union {\r | |
695 | NVME_ADMIN_IDENTIFY Identify;\r | |
696 | NVME_ADMIN_CRIOCQ CrIoCq;\r | |
697 | NVME_ADMIN_CRIOSQ CrIoSq;\r | |
698 | NVME_ADMIN_DEIOCQ DeIoCq;\r | |
699 | NVME_ADMIN_DEIOSQ DeIoSq;\r | |
700 | NVME_ADMIN_ABORT Abort;\r | |
701 | NVME_ADMIN_FIRMWARE_ACTIVATE Activate;\r | |
702 | NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;\r | |
703 | NVME_ADMIN_GET_FEATURES GetFeatures;\r | |
704 | NVME_ADMIN_GET_LOG_PAGE GetLogPage;\r | |
705 | NVME_ADMIN_SET_FEATURES SetFeatures;\r | |
706 | NVME_ADMIN_FORMAT_NVM FormatNvm;\r | |
707 | NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;\r | |
708 | NVME_ADMIN_SECURITY_SEND SecuritySend;\r | |
709 | } NVME_ADMIN_CMD;\r | |
710 | \r | |
711 | typedef struct {\r | |
712 | UINT32 Cdw10;\r | |
713 | UINT32 Cdw11;\r | |
714 | UINT32 Cdw12;\r | |
715 | UINT32 Cdw13;\r | |
716 | UINT32 Cdw14;\r | |
717 | UINT32 Cdw15;\r | |
718 | } NVME_RAW;\r | |
719 | \r | |
720 | typedef union {\r | |
721 | NVME_ADMIN_CMD Admin; // Union of Admin commands\r | |
722 | NVME_CMD Nvm; // Union of Nvm commands\r | |
723 | NVME_RAW Raw;\r | |
724 | } NVME_PAYLOAD;\r | |
725 | \r | |
726 | //\r | |
727 | // Submission Queue\r | |
728 | //\r | |
729 | typedef struct {\r | |
730 | //\r | |
731 | // CDW 0, Common to all comnmands\r | |
732 | //\r | |
733 | UINT8 Opc; // Opcode\r | |
734 | UINT8 Fuse:2; // Fused Operation\r | |
735 | UINT8 Rsvd1:5;\r | |
736 | UINT8 Psdt:1; // PRP or SGL for Data Transfer\r | |
737 | UINT16 Cid; // Command Identifier\r | |
738 | \r | |
739 | //\r | |
740 | // CDW 1\r | |
741 | //\r | |
742 | UINT32 Nsid; // Namespace Identifier\r | |
743 | \r | |
744 | //\r | |
745 | // CDW 2,3\r | |
746 | //\r | |
747 | UINT64 Rsvd2;\r | |
748 | \r | |
749 | //\r | |
750 | // CDW 4,5\r | |
751 | //\r | |
752 | UINT64 Mptr; // Metadata Pointer\r | |
753 | \r | |
754 | //\r | |
755 | // CDW 6-9\r | |
756 | //\r | |
757 | UINT64 Prp[2]; // First and second PRP entries\r | |
758 | \r | |
759 | NVME_PAYLOAD Payload;\r | |
760 | \r | |
761 | } NVME_SQ;\r | |
762 | \r | |
763 | //\r | |
764 | // Completion Queue\r | |
765 | //\r | |
766 | typedef struct {\r | |
767 | //\r | |
768 | // CDW 0\r | |
769 | //\r | |
770 | UINT32 Dword0;\r | |
771 | //\r | |
772 | // CDW 1\r | |
773 | //\r | |
774 | UINT32 Rsvd1;\r | |
775 | //\r | |
776 | // CDW 2\r | |
777 | //\r | |
778 | UINT16 Sqhd; // Submission Queue Head Pointer\r | |
779 | UINT16 Sqid; // Submission Queue Identifier\r | |
780 | //\r | |
781 | // CDW 3\r | |
782 | //\r | |
783 | UINT16 Cid; // Command Identifier\r | |
784 | UINT16 Pt:1; // Phase Tag\r | |
785 | UINT16 Sc:8; // Status Code\r | |
786 | UINT16 Sct:3; // Status Code Type\r | |
787 | UINT16 Rsvd2:2;\r | |
788 | UINT16 Mo:1; // More\r | |
789 | UINT16 Dnr:1; // Retry\r | |
790 | } NVME_CQ;\r | |
791 | \r | |
792 | //\r | |
793 | // Nvm Express Admin cmd opcodes\r | |
794 | //\r | |
795 | #define NVME_ADMIN_DELIOSQ_OPC 0\r | |
796 | #define NVME_ADMIN_CRIOSQ_OPC 1\r | |
797 | #define NVME_ADMIN_DELIOCQ_OPC 4\r | |
798 | #define NVME_ADMIN_CRIOCQ_OPC 5\r | |
799 | #define NVME_ADMIN_IDENTIFY_OPC 6\r | |
800 | #define NVME_ADMIN_SECURITY_SEND_OPC 0x81\r | |
801 | #define NVME_ADMIN_SECURITY_RECV_OPC 0x82\r | |
802 | \r | |
803 | #define NVME_IO_FLUSH_OPC 0\r | |
804 | #define NVME_IO_WRITE_OPC 1\r | |
805 | #define NVME_IO_READ_OPC 2\r | |
806 | \r | |
807 | //\r | |
808 | // Offset from the beginning of private Data queue Buffer\r | |
809 | //\r | |
810 | #define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE\r | |
811 | \r | |
812 | #pragma pack()\r | |
813 | \r | |
814 | #endif\r | |
815 | \r |