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5d73d92f | 1 | /** @file\r |
2 | Header file for Pci shell Debug1 function.\r | |
3 | \r | |
541ddf44 | 4 | Copyright (c) 2013 Hewlett-Packard Development Company, L.P.\r |
5d73d92f | 5 | Copyright (c) 2005 - 2010, Intel Corporation. All rights reserved.<BR>\r |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef _EFI_SHELL_PCI_H_\r | |
17 | #define _EFI_SHELL_PCI_H_\r | |
18 | \r | |
19 | typedef enum {\r | |
20 | PciDevice,\r | |
21 | PciP2pBridge,\r | |
22 | PciCardBusBridge,\r | |
23 | PciUndefined\r | |
24 | } PCI_HEADER_TYPE;\r | |
25 | \r | |
26 | #define HEADER_TYPE_MULTI_FUNCTION 0x80\r | |
27 | \r | |
28 | #define MAX_BUS_NUMBER 255\r | |
29 | #define MAX_DEVICE_NUMBER 31\r | |
30 | #define MAX_FUNCTION_NUMBER 7\r | |
31 | \r | |
32 | #define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10\r | |
33 | #define EFI_PCI_CAPABILITY_ID_PCIX 0x07\r | |
34 | \r | |
35 | #define CALC_EFI_PCI_ADDRESS(Bus, Dev, Func, Reg) \\r | |
36 | ((UINT64) ((((UINTN) Bus) << 24) + (((UINTN) Dev) << 16) + (((UINTN) Func) << 8) + ((UINTN) Reg)))\r | |
37 | \r | |
38 | #define CALC_EFI_PCIEX_ADDRESS(Bus, Dev, Func, ExReg) ( \\r | |
39 | (UINT64) ((((UINTN) Bus) << 24) + (((UINTN) Dev) << 16) + (((UINTN) Func) << 8) + (LShiftU64 ((UINT64) ExReg, 32))) \\r | |
40 | );\r | |
41 | \r | |
42 | #define INDEX_OF(Field) ((UINT8 *) (Field) - (UINT8 *) mConfigSpace)\r | |
43 | \r | |
44 | #define PCI_BIT_0 0x00000001\r | |
45 | #define PCI_BIT_1 0x00000002\r | |
46 | #define PCI_BIT_2 0x00000004\r | |
47 | #define PCI_BIT_3 0x00000008\r | |
48 | #define PCI_BIT_4 0x00000010\r | |
49 | #define PCI_BIT_5 0x00000020\r | |
50 | #define PCI_BIT_6 0x00000040\r | |
51 | #define PCI_BIT_7 0x00000080\r | |
52 | #define PCI_BIT_8 0x00000100\r | |
53 | #define PCI_BIT_9 0x00000200\r | |
54 | #define PCI_BIT_10 0x00000400\r | |
55 | #define PCI_BIT_11 0x00000800\r | |
56 | #define PCI_BIT_12 0x00001000\r | |
57 | #define PCI_BIT_13 0x00002000\r | |
58 | #define PCI_BIT_14 0x00004000\r | |
59 | #define PCI_BIT_15 0x00008000\r | |
60 | \r | |
61 | //\r | |
62 | // PCIE device/port types\r | |
63 | //\r | |
64 | #define PCIE_PCIE_ENDPOINT 0\r | |
65 | #define PCIE_LEGACY_PCIE_ENDPOINT 1\r | |
66 | #define PCIE_ROOT_COMPLEX_ROOT_PORT 4\r | |
67 | #define PCIE_SWITCH_UPSTREAM_PORT 5\r | |
68 | #define PCIE_SWITCH_DOWNSTREAM_PORT 6\r | |
69 | #define PCIE_PCIE_TO_PCIX_BRIDGE 7\r | |
70 | #define PCIE_PCIX_TO_PCIE_BRIDGE 8\r | |
71 | #define PCIE_ROOT_COMPLEX_INTEGRATED_PORT 9\r | |
72 | #define PCIE_ROOT_COMPLEX_EVENT_COLLECTOR 10\r | |
73 | #define PCIE_DEVICE_PORT_TYPE_MAX 11\r | |
74 | \r | |
75 | #define IS_PCIE_ENDPOINT(DevicePortType) \\r | |
76 | ((DevicePortType) == PCIE_PCIE_ENDPOINT || \\r | |
77 | (DevicePortType) == PCIE_LEGACY_PCIE_ENDPOINT || \\r | |
78 | (DevicePortType) == PCIE_ROOT_COMPLEX_INTEGRATED_PORT)\r | |
79 | \r | |
80 | #define IS_PCIE_SWITCH(DevicePortType) \\r | |
81 | ((DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) || \\r | |
82 | (DevicePortType == PCIE_SWITCH_DOWNSTREAM_PORT))\r | |
83 | \r | |
84 | //\r | |
85 | // Capabilities Register\r | |
86 | //\r | |
87 | #define PCIE_CAP_VERSION(PcieCapReg) \\r | |
88 | ((PcieCapReg) & 0x0f)\r | |
89 | #define PCIE_CAP_DEVICEPORT_TYPE(PcieCapReg) \\r | |
90 | (((PcieCapReg) >> 4) & 0x0f)\r | |
91 | #define PCIE_CAP_SLOT_IMPLEMENTED(PcieCapReg) \\r | |
92 | (((PcieCapReg) >> 8) & 0x1)\r | |
93 | #define PCIE_CAP_INT_MSG_NUM(PcieCapReg) \\r | |
94 | (((PcieCapReg) >> 9) & 0x1f)\r | |
95 | //\r | |
96 | // Device Capabilities Register\r | |
97 | //\r | |
98 | #define PCIE_CAP_MAX_PAYLOAD(PcieDeviceCap) \\r | |
99 | ((PcieDeviceCap) & 0x7)\r | |
100 | #define PCIE_CAP_PHANTOM_FUNC(PcieDeviceCap) \\r | |
101 | (((PcieDeviceCap) >> 3) & 0x3)\r | |
102 | #define PCIE_CAP_EXTENDED_TAG(PcieDeviceCap) \\r | |
103 | (((PcieDeviceCap) >> 5) & 0x1)\r | |
a1d4bfcc | 104 | #define PCIE_CAP_L0SLATENCY(PcieDeviceCap) \\r |
5d73d92f | 105 | (((PcieDeviceCap) >> 6) & 0x7)\r |
a1d4bfcc | 106 | #define PCIE_CAP_L1LATENCY(PcieDeviceCap) \\r |
5d73d92f | 107 | (((PcieDeviceCap) >> 9) & 0x7)\r |
108 | #define PCIE_CAP_ERR_REPORTING(PcieDeviceCap) \\r | |
109 | (((PcieDeviceCap) >> 15) & 0x1)\r | |
110 | #define PCIE_CAP_SLOT_POWER_VALUE(PcieDeviceCap) \\r | |
111 | (((PcieDeviceCap) >> 18) & 0x0ff)\r | |
112 | #define PCIE_CAP_SLOT_POWER_SCALE(PcieDeviceCap) \\r | |
113 | (((PcieDeviceCap) >> 26) & 0x3)\r | |
114 | #define PCIE_CAP_FUNC_LEVEL_RESET(PcieDeviceCap) \\r | |
115 | (((PcieDeviceCap) >> 28) & 0x1)\r | |
116 | //\r | |
117 | // Device Control Register\r | |
118 | //\r | |
119 | #define PCIE_CAP_COR_ERR_REPORTING_ENABLE(PcieDeviceControl) \\r | |
120 | ((PcieDeviceControl) & 0x1)\r | |
121 | #define PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE(PcieDeviceControl) \\r | |
122 | (((PcieDeviceControl) >> 1) & 0x1)\r | |
123 | #define PCIE_CAP_FATAL_ERR_REPORTING_ENABLE(PcieDeviceControl) \\r | |
124 | (((PcieDeviceControl) >> 2) & 0x1)\r | |
125 | #define PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE(PcieDeviceControl) \\r | |
126 | (((PcieDeviceControl) >> 3) & 0x1)\r | |
127 | #define PCIE_CAP_RELAXED_ORDERING_ENABLE(PcieDeviceControl) \\r | |
128 | (((PcieDeviceControl) >> 4) & 0x1)\r | |
129 | #define PCIE_CAP_MAX_PAYLOAD_SIZE(PcieDeviceControl) \\r | |
130 | (((PcieDeviceControl) >> 5) & 0x7)\r | |
131 | #define PCIE_CAP_EXTENDED_TAG_ENABLE(PcieDeviceControl) \\r | |
132 | (((PcieDeviceControl) >> 8) & 0x1)\r | |
133 | #define PCIE_CAP_PHANTOM_FUNC_ENABLE(PcieDeviceControl) \\r | |
134 | (((PcieDeviceControl) >> 9) & 0x1)\r | |
135 | #define PCIE_CAP_AUX_PM_ENABLE(PcieDeviceControl) \\r | |
136 | (((PcieDeviceControl) >> 10) & 0x1)\r | |
137 | #define PCIE_CAP_NO_SNOOP_ENABLE(PcieDeviceControl) \\r | |
138 | (((PcieDeviceControl) >> 11) & 0x1)\r | |
139 | #define PCIE_CAP_MAX_READ_REQ_SIZE(PcieDeviceControl) \\r | |
140 | (((PcieDeviceControl) >> 12) & 0x7)\r | |
141 | #define PCIE_CAP_BRG_CONF_RETRY(PcieDeviceControl) \\r | |
142 | (((PcieDeviceControl) >> 15) & 0x1)\r | |
143 | //\r | |
144 | // Device Status Register\r | |
145 | //\r | |
146 | #define PCIE_CAP_COR_ERR_DETECTED(PcieDeviceStatus) \\r | |
147 | ((PcieDeviceStatus) & 0x1)\r | |
148 | #define PCIE_CAP_NONFAT_ERR_DETECTED(PcieDeviceStatus) \\r | |
149 | (((PcieDeviceStatus) >> 1) & 0x1)\r | |
150 | #define PCIE_CAP_FATAL_ERR_DETECTED(PcieDeviceStatus) \\r | |
151 | (((PcieDeviceStatus) >> 2) & 0x1)\r | |
152 | #define PCIE_CAP_UNSUP_REQ_DETECTED(PcieDeviceStatus) \\r | |
153 | (((PcieDeviceStatus) >> 3) & 0x1)\r | |
154 | #define PCIE_CAP_AUX_POWER_DETECTED(PcieDeviceStatus) \\r | |
155 | (((PcieDeviceStatus) >> 4) & 0x1)\r | |
156 | #define PCIE_CAP_TRANSACTION_PENDING(PcieDeviceStatus) \\r | |
157 | (((PcieDeviceStatus) >> 5) & 0x1)\r | |
158 | //\r | |
159 | // Link Capabilities Register\r | |
160 | //\r | |
541ddf44 | 161 | #define PCIE_CAP_MAX_LINK_SPEED(PcieLinkCap) \\r |
5d73d92f | 162 | ((PcieLinkCap) & 0x0f)\r |
163 | #define PCIE_CAP_MAX_LINK_WIDTH(PcieLinkCap) \\r | |
164 | (((PcieLinkCap) >> 4) & 0x3f)\r | |
165 | #define PCIE_CAP_ASPM_SUPPORT(PcieLinkCap) \\r | |
166 | (((PcieLinkCap) >> 10) & 0x3)\r | |
a1d4bfcc | 167 | #define PCIE_CAP_L0S_LATENCY(PcieLinkCap) \\r |
5d73d92f | 168 | (((PcieLinkCap) >> 12) & 0x7)\r |
169 | #define PCIE_CAP_L1_LATENCY(PcieLinkCap) \\r | |
170 | (((PcieLinkCap) >> 15) & 0x7)\r | |
171 | #define PCIE_CAP_CLOCK_PM(PcieLinkCap) \\r | |
172 | (((PcieLinkCap) >> 18) & 0x1)\r | |
173 | #define PCIE_CAP_SUP_DOWN_ERR_REPORTING(PcieLinkCap) \\r | |
174 | (((PcieLinkCap) >> 19) & 0x1)\r | |
175 | #define PCIE_CAP_LINK_ACTIVE_REPORTING(PcieLinkCap) \\r | |
176 | (((PcieLinkCap) >> 20) & 0x1)\r | |
177 | #define PCIE_CAP_LINK_BWD_NOTIF_CAP(PcieLinkCap) \\r | |
178 | (((PcieLinkCap) >> 21) & 0x1)\r | |
179 | #define PCIE_CAP_PORT_NUMBER(PcieLinkCap) \\r | |
180 | (((PcieLinkCap) >> 24) & 0x0ff)\r | |
181 | //\r | |
182 | // Link Control Register\r | |
183 | //\r | |
184 | #define PCIE_CAP_ASPM_CONTROL(PcieLinkControl) \\r | |
185 | ((PcieLinkControl) & 0x3)\r | |
186 | #define PCIE_CAP_RCB(PcieLinkControl) \\r | |
187 | (((PcieLinkControl) >> 3) & 0x1)\r | |
188 | #define PCIE_CAP_LINK_DISABLE(PcieLinkControl) \\r | |
189 | (((PcieLinkControl) >> 4) & 0x1)\r | |
190 | #define PCIE_CAP_COMMON_CLK_CONF(PcieLinkControl) \\r | |
191 | (((PcieLinkControl) >> 6) & 0x1)\r | |
192 | #define PCIE_CAP_EXT_SYNC(PcieLinkControl) \\r | |
193 | (((PcieLinkControl) >> 7) & 0x1)\r | |
194 | #define PCIE_CAP_CLK_PWR_MNG(PcieLinkControl) \\r | |
195 | (((PcieLinkControl) >> 8) & 0x1)\r | |
196 | #define PCIE_CAP_HW_AUTO_WIDTH_DISABLE(PcieLinkControl) \\r | |
197 | (((PcieLinkControl) >> 9) & 0x1)\r | |
198 | #define PCIE_CAP_LINK_BDW_MNG_INT_EN(PcieLinkControl) \\r | |
199 | (((PcieLinkControl) >> 10) & 0x1)\r | |
200 | #define PCIE_CAP_LINK_AUTO_BDW_INT_EN(PcieLinkControl) \\r | |
201 | (((PcieLinkControl) >> 11) & 0x1)\r | |
202 | //\r | |
203 | // Link Status Register\r | |
204 | //\r | |
205 | #define PCIE_CAP_CUR_LINK_SPEED(PcieLinkStatus) \\r | |
206 | ((PcieLinkStatus) & 0x0f)\r | |
207 | #define PCIE_CAP_NEGO_LINK_WIDTH(PcieLinkStatus) \\r | |
208 | (((PcieLinkStatus) >> 4) & 0x3f)\r | |
209 | #define PCIE_CAP_LINK_TRAINING(PcieLinkStatus) \\r | |
210 | (((PcieLinkStatus) >> 11) & 0x1)\r | |
211 | #define PCIE_CAP_SLOT_CLK_CONF(PcieLinkStatus) \\r | |
212 | (((PcieLinkStatus) >> 12) & 0x1)\r | |
213 | #define PCIE_CAP_DATA_LINK_ACTIVE(PcieLinkStatus) \\r | |
214 | (((PcieLinkStatus) >> 13) & 0x1)\r | |
215 | #define PCIE_CAP_LINK_BDW_MNG_STAT(PcieLinkStatus) \\r | |
216 | (((PcieLinkStatus) >> 14) & 0x1)\r | |
217 | #define PCIE_CAP_LINK_AUTO_BDW_STAT(PcieLinkStatus) \\r | |
218 | (((PcieLinkStatus) >> 15) & 0x1)\r | |
219 | //\r | |
220 | // Slot Capabilities Register\r | |
221 | //\r | |
222 | #define PCIE_CAP_ATT_BUT_PRESENT(PcieSlotCap) \\r | |
223 | ((PcieSlotCap) & 0x1)\r | |
224 | #define PCIE_CAP_PWR_CTRLLER_PRESENT(PcieSlotCap) \\r | |
225 | (((PcieSlotCap) >> 1) & 0x1)\r | |
226 | #define PCIE_CAP_MRL_SENSOR_PRESENT(PcieSlotCap) \\r | |
227 | (((PcieSlotCap) >> 2) & 0x1)\r | |
228 | #define PCIE_CAP_ATT_IND_PRESENT(PcieSlotCap) \\r | |
229 | (((PcieSlotCap) >> 3) & 0x1)\r | |
230 | #define PCIE_CAP_PWD_IND_PRESENT(PcieSlotCap) \\r | |
231 | (((PcieSlotCap) >> 4) & 0x1)\r | |
232 | #define PCIE_CAP_HOTPLUG_SUPPRISE(PcieSlotCap) \\r | |
233 | (((PcieSlotCap) >> 5) & 0x1)\r | |
234 | #define PCIE_CAP_HOTPLUG_CAPABLE(PcieSlotCap) \\r | |
235 | (((PcieSlotCap) >> 6) & 0x1)\r | |
236 | #define PCIE_CAP_SLOT_PWR_LIMIT_VALUE(PcieSlotCap) \\r | |
237 | (((PcieSlotCap) >> 7) & 0x0ff)\r | |
238 | #define PCIE_CAP_SLOT_PWR_LIMIT_SCALE(PcieSlotCap) \\r | |
239 | (((PcieSlotCap) >> 15) & 0x3)\r | |
240 | #define PCIE_CAP_ELEC_INTERLOCK_PRESENT(PcieSlotCap) \\r | |
241 | (((PcieSlotCap) >> 17) & 0x1)\r | |
242 | #define PCIE_CAP_NO_COMM_COMPLETED_SUP(PcieSlotCap) \\r | |
243 | (((PcieSlotCap) >> 18) & 0x1)\r | |
244 | #define PCIE_CAP_PHY_SLOT_NUM(PcieSlotCap) \\r | |
245 | (((PcieSlotCap) >> 19) & 0x1fff)\r | |
246 | //\r | |
247 | // Slot Control Register\r | |
248 | //\r | |
249 | #define PCIE_CAP_ATT_BUT_ENABLE(PcieSlotControl) \\r | |
250 | ((PcieSlotControl) & 0x1)\r | |
251 | #define PCIE_CAP_PWR_FLT_DETECT_ENABLE(PcieSlotControl) \\r | |
252 | (((PcieSlotControl) >> 1) & 0x1)\r | |
253 | #define PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE(PcieSlotControl) \\r | |
254 | (((PcieSlotControl) >> 2) & 0x1)\r | |
255 | #define PCIE_CAP_PRES_DETECT_CHANGE_ENABLE(PcieSlotControl) \\r | |
256 | (((PcieSlotControl) >> 3) & 0x1)\r | |
257 | #define PCIE_CAP_COMM_CMPL_INT_ENABLE(PcieSlotControl) \\r | |
258 | (((PcieSlotControl) >> 4) & 0x1)\r | |
259 | #define PCIE_CAP_HOTPLUG_INT_ENABLE(PcieSlotControl) \\r | |
260 | (((PcieSlotControl) >> 5) & 0x1)\r | |
261 | #define PCIE_CAP_ATT_IND_CTRL(PcieSlotControl) \\r | |
262 | (((PcieSlotControl) >> 6) & 0x3)\r | |
263 | #define PCIE_CAP_PWR_IND_CTRL(PcieSlotControl) \\r | |
264 | (((PcieSlotControl) >> 8) & 0x3)\r | |
265 | #define PCIE_CAP_PWR_CTRLLER_CTRL(PcieSlotControl) \\r | |
266 | (((PcieSlotControl) >> 10) & 0x1)\r | |
267 | #define PCIE_CAP_ELEC_INTERLOCK_CTRL(PcieSlotControl) \\r | |
268 | (((PcieSlotControl) >> 11) & 0x1)\r | |
269 | #define PCIE_CAP_DLINK_STAT_CHANGE_ENABLE(PcieSlotControl) \\r | |
270 | (((PcieSlotControl) >> 12) & 0x1)\r | |
271 | //\r | |
272 | // Slot Status Register\r | |
273 | //\r | |
274 | #define PCIE_CAP_ATT_BUT_PRESSED(PcieSlotStatus) \\r | |
275 | ((PcieSlotStatus) & 0x1)\r | |
276 | #define PCIE_CAP_PWR_FLT_DETECTED(PcieSlotStatus) \\r | |
277 | (((PcieSlotStatus) >> 1) & 0x1)\r | |
278 | #define PCIE_CAP_MRL_SENSOR_CHANGED(PcieSlotStatus) \\r | |
279 | (((PcieSlotStatus) >> 2) & 0x1)\r | |
280 | #define PCIE_CAP_PRES_DETECT_CHANGED(PcieSlotStatus) \\r | |
281 | (((PcieSlotStatus) >> 3) & 0x1)\r | |
282 | #define PCIE_CAP_COMM_COMPLETED(PcieSlotStatus) \\r | |
283 | (((PcieSlotStatus) >> 4) & 0x1)\r | |
284 | #define PCIE_CAP_MRL_SENSOR_STATE(PcieSlotStatus) \\r | |
285 | (((PcieSlotStatus) >> 5) & 0x1)\r | |
286 | #define PCIE_CAP_PRES_DETECT_STATE(PcieSlotStatus) \\r | |
287 | (((PcieSlotStatus) >> 6) & 0x1)\r | |
288 | #define PCIE_CAP_ELEC_INTERLOCK_STATE(PcieSlotStatus) \\r | |
289 | (((PcieSlotStatus) >> 7) & 0x1)\r | |
290 | #define PCIE_CAP_DLINK_STAT_CHANGED(PcieSlotStatus) \\r | |
291 | (((PcieSlotStatus) >> 8) & 0x1)\r | |
292 | //\r | |
293 | // Root Control Register\r | |
294 | //\r | |
295 | #define PCIE_CAP_SYSERR_ON_CORERR_EN(PcieRootControl) \\r | |
296 | ((PcieRootControl) & 0x1)\r | |
297 | #define PCIE_CAP_SYSERR_ON_NONFATERR_EN(PcieRootControl) \\r | |
298 | (((PcieRootControl) >> 1) & 0x1)\r | |
299 | #define PCIE_CAP_SYSERR_ON_FATERR_EN(PcieRootControl) \\r | |
300 | (((PcieRootControl) >> 2) & 0x1)\r | |
301 | #define PCIE_CAP_PME_INT_ENABLE(PcieRootControl) \\r | |
302 | (((PcieRootControl) >> 3) & 0x1)\r | |
303 | #define PCIE_CAP_CRS_SW_VIS_ENABLE(PcieRootControl) \\r | |
304 | (((PcieRootControl) >> 4) & 0x1)\r | |
305 | //\r | |
306 | // Root Capabilities Register\r | |
307 | //\r | |
308 | #define PCIE_CAP_CRS_SW_VIS(PcieRootCap) \\r | |
309 | ((PcieRootCap) & 0x1)\r | |
310 | //\r | |
311 | // Root Status Register\r | |
312 | //\r | |
313 | #define PCIE_CAP_PME_REQ_ID(PcieRootStatus) \\r | |
314 | ((PcieRootStatus) & 0x0ffff)\r | |
315 | #define PCIE_CAP_PME_STATUS(PcieRootStatus) \\r | |
316 | (((PcieRootStatus) >> 16) & 0x1)\r | |
317 | #define PCIE_CAP_PME_PENDING(PcieRootStatus) \\r | |
318 | (((PcieRootStatus) >> 17) & 0x1)\r | |
319 | \r | |
320 | #pragma pack(1)\r | |
321 | //\r | |
322 | // Common part of the PCI configuration space header for devices, P2P bridges,\r | |
323 | // and cardbus bridges\r | |
324 | //\r | |
325 | typedef struct {\r | |
326 | UINT16 VendorId;\r | |
327 | UINT16 DeviceId;\r | |
328 | \r | |
329 | UINT16 Command;\r | |
330 | UINT16 Status;\r | |
331 | \r | |
332 | UINT8 RevisionId;\r | |
333 | UINT8 ClassCode[3];\r | |
334 | \r | |
335 | UINT8 CacheLineSize;\r | |
336 | UINT8 PrimaryLatencyTimer;\r | |
337 | UINT8 HeaderType;\r | |
a1d4bfcc | 338 | UINT8 Bist;\r |
5d73d92f | 339 | \r |
340 | } PCI_COMMON_HEADER;\r | |
341 | \r | |
342 | //\r | |
343 | // PCI configuration space header for devices(after the common part)\r | |
344 | //\r | |
345 | typedef struct {\r | |
346 | UINT32 Bar[6]; // Base Address Registers\r | |
347 | UINT32 CardBusCISPtr; // CardBus CIS Pointer\r | |
348 | UINT16 SubVendorId; // Subsystem Vendor ID\r | |
349 | UINT16 SubSystemId; // Subsystem ID\r | |
350 | UINT32 ROMBar; // Expansion ROM Base Address\r | |
351 | UINT8 CapabilitiesPtr; // Capabilities Pointer\r | |
352 | UINT8 Reserved[3];\r | |
353 | \r | |
354 | UINT32 Reserved1;\r | |
355 | \r | |
356 | UINT8 InterruptLine; // Interrupt Line\r | |
357 | UINT8 InterruptPin; // Interrupt Pin\r | |
358 | UINT8 MinGnt; // Min_Gnt\r | |
359 | UINT8 MaxLat; // Max_Lat\r | |
360 | } PCI_DEVICE_HEADER;\r | |
361 | \r | |
362 | //\r | |
363 | // PCI configuration space header for pci-to-pci bridges(after the common part)\r | |
364 | //\r | |
365 | typedef struct {\r | |
366 | UINT32 Bar[2]; // Base Address Registers\r | |
367 | UINT8 PrimaryBus; // Primary Bus Number\r | |
368 | UINT8 SecondaryBus; // Secondary Bus Number\r | |
369 | UINT8 SubordinateBus; // Subordinate Bus Number\r | |
370 | UINT8 SecondaryLatencyTimer; // Secondary Latency Timer\r | |
371 | UINT8 IoBase; // I/O Base\r | |
372 | UINT8 IoLimit; // I/O Limit\r | |
373 | UINT16 SecondaryStatus; // Secondary Status\r | |
374 | UINT16 MemoryBase; // Memory Base\r | |
375 | UINT16 MemoryLimit; // Memory Limit\r | |
376 | UINT16 PrefetchableMemBase; // Pre-fetchable Memory Base\r | |
377 | UINT16 PrefetchableMemLimit; // Pre-fetchable Memory Limit\r | |
378 | UINT32 PrefetchableBaseUpper; // Pre-fetchable Base Upper 32 bits\r | |
379 | UINT32 PrefetchableLimitUpper; // Pre-fetchable Limit Upper 32 bits\r | |
380 | UINT16 IoBaseUpper; // I/O Base Upper 16 bits\r | |
381 | UINT16 IoLimitUpper; // I/O Limit Upper 16 bits\r | |
382 | UINT8 CapabilitiesPtr; // Capabilities Pointer\r | |
383 | UINT8 Reserved[3];\r | |
384 | \r | |
385 | UINT32 ROMBar; // Expansion ROM Base Address\r | |
386 | UINT8 InterruptLine; // Interrupt Line\r | |
387 | UINT8 InterruptPin; // Interrupt Pin\r | |
388 | UINT16 BridgeControl; // Bridge Control\r | |
389 | } PCI_BRIDGE_HEADER;\r | |
390 | \r | |
391 | //\r | |
392 | // PCI configuration space header for cardbus bridges(after the common part)\r | |
393 | //\r | |
394 | typedef struct {\r | |
395 | UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base\r | |
396 | // Address Register\r | |
397 | //\r | |
398 | UINT8 CapabilitiesPtr; // 14h in pci-cardbus bridge.\r | |
399 | UINT8 Reserved;\r | |
400 | UINT16 SecondaryStatus; // Secondary Status\r | |
401 | UINT8 PciBusNumber; // PCI Bus Number\r | |
402 | UINT8 CardBusBusNumber; // CardBus Bus Number\r | |
403 | UINT8 SubordinateBusNumber; // Subordinate Bus Number\r | |
404 | UINT8 CardBusLatencyTimer; // CardBus Latency Timer\r | |
405 | UINT32 MemoryBase0; // Memory Base Register 0\r | |
406 | UINT32 MemoryLimit0; // Memory Limit Register 0\r | |
407 | UINT32 MemoryBase1;\r | |
408 | UINT32 MemoryLimit1;\r | |
409 | UINT32 IoBase0;\r | |
410 | UINT32 IoLimit0; // I/O Base Register 0\r | |
411 | UINT32 IoBase1; // I/O Limit Register 0\r | |
412 | UINT32 IoLimit1;\r | |
413 | \r | |
414 | UINT8 InterruptLine; // Interrupt Line\r | |
415 | UINT8 InterruptPin; // Interrupt Pin\r | |
416 | UINT16 BridgeControl; // Bridge Control\r | |
417 | } PCI_CARDBUS_HEADER;\r | |
418 | \r | |
419 | //\r | |
420 | // Data region after PCI configuration header(for cardbus bridge)\r | |
421 | //\r | |
422 | typedef struct {\r | |
423 | UINT16 SubVendorId; // Subsystem Vendor ID\r | |
424 | UINT16 SubSystemId; // Subsystem ID\r | |
425 | UINT32 LegacyBase; // Optional 16-Bit PC Card Legacy\r | |
426 | // Mode Base Address\r | |
427 | //\r | |
428 | UINT32 Data[46];\r | |
429 | } PCI_CARDBUS_DATA;\r | |
430 | \r | |
a1d4bfcc | 431 | typedef union {\r |
432 | PCI_DEVICE_HEADER Device;\r | |
433 | PCI_BRIDGE_HEADER Bridge;\r | |
434 | PCI_CARDBUS_HEADER CardBus;\r | |
435 | } NON_COMMON_UNION;\r | |
436 | \r | |
5d73d92f | 437 | typedef struct {\r |
438 | PCI_COMMON_HEADER Common;\r | |
a1d4bfcc | 439 | NON_COMMON_UNION NonCommon;\r |
5d73d92f | 440 | UINT32 Data[48];\r |
441 | } PCI_CONFIG_SPACE;\r | |
442 | \r | |
443 | typedef struct {\r | |
444 | UINT8 PcieCapId;\r | |
445 | UINT8 NextCapPtr;\r | |
446 | UINT16 PcieCapReg;\r | |
447 | UINT32 PcieDeviceCap;\r | |
448 | UINT16 DeviceControl;\r | |
449 | UINT16 DeviceStatus;\r | |
450 | UINT32 LinkCap;\r | |
451 | UINT16 LinkControl;\r | |
452 | UINT16 LinkStatus;\r | |
453 | UINT32 SlotCap;\r | |
454 | UINT16 SlotControl;\r | |
455 | UINT16 SlotStatus;\r | |
5d73d92f | 456 | UINT16 RootControl;\r |
2412c297 | 457 | UINT16 RsvdP;\r |
5d73d92f | 458 | UINT32 RootStatus;\r |
2412c297 | 459 | } PCIE_CAP_STRUCTURE;\r |
5d73d92f | 460 | \r |
461 | #pragma pack()\r | |
462 | \r | |
463 | #endif // _PCI_H_\r |