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18b144ea | 1 | /** @file\r |
2 | IA32/x64 architecture specific defintions needed by debug transfer protocol.It is only\r | |
3 | intended to be used by Debug related module implementation.\r | |
4 | \r | |
93c0bdec | 5 | Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>\r |
18b144ea | 6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php.\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __PROCESSOR_CONTEXT_H__\r | |
17 | #define __PROCESSOR_CONTEXT_H__\r | |
18 | \r | |
19 | //\r | |
20 | // IA-32/x64 processor register index table\r | |
21 | //\r | |
93c0bdec | 22 | #define SOFT_DEBUGGER_REGISTER_DR0 0x00\r |
23 | #define SOFT_DEBUGGER_REGISTER_DR1 0x01\r | |
24 | #define SOFT_DEBUGGER_REGISTER_DR2 0x02\r | |
25 | #define SOFT_DEBUGGER_REGISTER_DR3 0x03\r | |
26 | #define SOFT_DEBUGGER_REGISTER_DR6 0x04\r | |
27 | #define SOFT_DEBUGGER_REGISTER_DR7 0x05\r | |
28 | #define SOFT_DEBUGGER_REGISTER_EFLAGS 0x06\r | |
29 | #define SOFT_DEBUGGER_REGISTER_LDTR 0x07\r | |
30 | #define SOFT_DEBUGGER_REGISTER_TR 0x08\r | |
31 | #define SOFT_DEBUGGER_REGISTER_GDTR0 0x09 // the low 32bit of GDTR\r | |
32 | #define SOFT_DEBUGGER_REGISTER_GDTR1 0x0A // the high 32bit of GDTR\r | |
33 | #define SOFT_DEBUGGER_REGISTER_IDTR0 0x0B // the low 32bit of IDTR\r | |
34 | #define SOFT_DEBUGGER_REGISTER_IDTR1 0x0C // the high 32bot of IDTR\r | |
35 | #define SOFT_DEBUGGER_REGISTER_EIP 0x0D\r | |
36 | #define SOFT_DEBUGGER_REGISTER_GS 0x0E\r | |
37 | #define SOFT_DEBUGGER_REGISTER_FS 0x0F\r | |
38 | #define SOFT_DEBUGGER_REGISTER_ES 0x10\r | |
39 | #define SOFT_DEBUGGER_REGISTER_DS 0x11\r | |
40 | #define SOFT_DEBUGGER_REGISTER_CS 0x12\r | |
41 | #define SOFT_DEBUGGER_REGISTER_SS 0x13\r | |
42 | #define SOFT_DEBUGGER_REGISTER_CR0 0x14\r | |
43 | #define SOFT_DEBUGGER_REGISTER_CR1 0x15\r | |
44 | #define SOFT_DEBUGGER_REGISTER_CR2 0x16\r | |
45 | #define SOFT_DEBUGGER_REGISTER_CR3 0x17\r | |
46 | #define SOFT_DEBUGGER_REGISTER_CR4 0x18\r | |
47 | \r | |
48 | #define SOFT_DEBUGGER_REGISTER_DI 0x19\r | |
49 | #define SOFT_DEBUGGER_REGISTER_SI 0x1A\r | |
50 | #define SOFT_DEBUGGER_REGISTER_BP 0x1B\r | |
51 | #define SOFT_DEBUGGER_REGISTER_SP 0x1C\r | |
52 | #define SOFT_DEBUGGER_REGISTER_DX 0x1D\r | |
53 | #define SOFT_DEBUGGER_REGISTER_CX 0x1E\r | |
54 | #define SOFT_DEBUGGER_REGISTER_BX 0x1F\r | |
55 | #define SOFT_DEBUGGER_REGISTER_AX 0x20\r | |
18b144ea | 56 | \r |
57 | //\r | |
58 | // This below registers are only available for x64 (not valid for Ia32 mode)\r | |
59 | //\r | |
93c0bdec | 60 | #define SOFT_DEBUGGER_REGISTER_CR8 0x21\r |
61 | #define SOFT_DEBUGGER_REGISTER_R8 0x22\r | |
62 | #define SOFT_DEBUGGER_REGISTER_R9 0x23\r | |
63 | #define SOFT_DEBUGGER_REGISTER_R10 0x24\r | |
64 | #define SOFT_DEBUGGER_REGISTER_R11 0x25\r | |
65 | #define SOFT_DEBUGGER_REGISTER_R12 0x26\r | |
66 | #define SOFT_DEBUGGER_REGISTER_R13 0x27\r | |
67 | #define SOFT_DEBUGGER_REGISTER_R14 0x28\r | |
68 | #define SOFT_DEBUGGER_REGISTER_R15 0x29\r | |
18b144ea | 69 | \r |
70 | //\r | |
71 | // This below registers are FP / MMX / XMM registers\r | |
72 | //\r | |
93c0bdec | 73 | #define SOFT_DEBUGGER_REGISTER_FP_BASE 0x30\r |
18b144ea | 74 | \r |
93c0bdec | 75 | #define SOFT_DEBUGGER_REGISTER_FP_FCW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x00)\r |
76 | #define SOFT_DEBUGGER_REGISTER_FP_FSW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x01)\r | |
77 | #define SOFT_DEBUGGER_REGISTER_FP_FTW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x02)\r | |
78 | #define SOFT_DEBUGGER_REGISTER_FP_OPCODE (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x03)\r | |
79 | #define SOFT_DEBUGGER_REGISTER_FP_EIP (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x04)\r | |
80 | #define SOFT_DEBUGGER_REGISTER_FP_CS (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x05)\r | |
81 | #define SOFT_DEBUGGER_REGISTER_FP_DATAOFFSET (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x06)\r | |
82 | #define SOFT_DEBUGGER_REGISTER_FP_DS (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x07)\r | |
83 | #define SOFT_DEBUGGER_REGISTER_FP_MXCSR (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x08)\r | |
84 | #define SOFT_DEBUGGER_REGISTER_FP_MXCSR_MASK (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x09)\r | |
85 | #define SOFT_DEBUGGER_REGISTER_ST0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0A)\r | |
86 | #define SOFT_DEBUGGER_REGISTER_ST1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0B)\r | |
87 | #define SOFT_DEBUGGER_REGISTER_ST2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0C)\r | |
88 | #define SOFT_DEBUGGER_REGISTER_ST3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0D)\r | |
89 | #define SOFT_DEBUGGER_REGISTER_ST4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0E)\r | |
90 | #define SOFT_DEBUGGER_REGISTER_ST5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0F)\r | |
91 | #define SOFT_DEBUGGER_REGISTER_ST6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x10)\r | |
92 | #define SOFT_DEBUGGER_REGISTER_ST7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x11)\r | |
93 | #define SOFT_DEBUGGER_REGISTER_XMM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x12)\r | |
94 | #define SOFT_DEBUGGER_REGISTER_XMM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x13)\r | |
95 | #define SOFT_DEBUGGER_REGISTER_XMM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x14)\r | |
96 | #define SOFT_DEBUGGER_REGISTER_XMM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x15)\r | |
97 | #define SOFT_DEBUGGER_REGISTER_XMM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x16)\r | |
98 | #define SOFT_DEBUGGER_REGISTER_XMM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x17)\r | |
99 | #define SOFT_DEBUGGER_REGISTER_XMM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x18)\r | |
100 | #define SOFT_DEBUGGER_REGISTER_XMM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x19)\r | |
101 | #define SOFT_DEBUGGER_REGISTER_XMM8 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1A)\r | |
102 | #define SOFT_DEBUGGER_REGISTER_XMM9 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1B)\r | |
103 | #define SOFT_DEBUGGER_REGISTER_XMM10 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1C)\r | |
104 | #define SOFT_DEBUGGER_REGISTER_XMM11 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1D)\r | |
105 | #define SOFT_DEBUGGER_REGISTER_XMM12 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1E)\r | |
106 | #define SOFT_DEBUGGER_REGISTER_XMM13 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1F)\r | |
107 | #define SOFT_DEBUGGER_REGISTER_XMM14 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x20)\r | |
108 | #define SOFT_DEBUGGER_REGISTER_XMM15 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x21)\r | |
109 | #define SOFT_DEBUGGER_REGISTER_MM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x22)\r | |
110 | #define SOFT_DEBUGGER_REGISTER_MM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x23)\r | |
111 | #define SOFT_DEBUGGER_REGISTER_MM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x24)\r | |
112 | #define SOFT_DEBUGGER_REGISTER_MM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x25)\r | |
113 | #define SOFT_DEBUGGER_REGISTER_MM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x26)\r | |
114 | #define SOFT_DEBUGGER_REGISTER_MM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x27)\r | |
115 | #define SOFT_DEBUGGER_REGISTER_MM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x28)\r | |
116 | #define SOFT_DEBUGGER_REGISTER_MM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x29)\r | |
18b144ea | 117 | \r |
93c0bdec | 118 | #define SOFT_DEBUGGER_REGISTER_MAX SOFT_DEBUGGER_REGISTER_MM7\r |
119 | \r | |
120 | #define SOFT_DEBUGGER_MSR_EFER (0xC0000080)\r | |
121 | \r | |
122 | #pragma pack(1)\r | |
123 | \r | |
124 | ///\r | |
125 | /// FXSAVE_STATE\r | |
126 | /// FP / MMX / XMM registers (see fxrstor instruction definition)\r | |
127 | ///\r | |
128 | typedef struct {\r | |
129 | UINT16 Fcw;\r | |
130 | UINT16 Fsw;\r | |
131 | UINT16 Ftw;\r | |
132 | UINT16 Opcode;\r | |
133 | UINT32 Eip;\r | |
134 | UINT16 Cs;\r | |
135 | UINT16 Reserved1;\r | |
136 | UINT32 DataOffset;\r | |
137 | UINT16 Ds;\r | |
138 | UINT8 Reserved2[2];\r | |
139 | UINT32 Mxcsr;\r | |
140 | UINT32 Mxcsr_Mask;\r | |
141 | UINT8 St0Mm0[10];\r | |
142 | UINT8 Reserved3[6];\r | |
143 | UINT8 St1Mm1[10];\r | |
144 | UINT8 Reserved4[6];\r | |
145 | UINT8 St2Mm2[10];\r | |
146 | UINT8 Reserved5[6];\r | |
147 | UINT8 St3Mm3[10];\r | |
148 | UINT8 Reserved6[6];\r | |
149 | UINT8 St4Mm4[10];\r | |
150 | UINT8 Reserved7[6];\r | |
151 | UINT8 St5Mm5[10];\r | |
152 | UINT8 Reserved8[6];\r | |
153 | UINT8 St6Mm6[10];\r | |
154 | UINT8 Reserved9[6];\r | |
155 | UINT8 St7Mm7[10];\r | |
156 | UINT8 Reserved10[6];\r | |
157 | UINT8 Xmm0[16];\r | |
158 | UINT8 Xmm1[16];\r | |
159 | UINT8 Xmm2[16];\r | |
160 | UINT8 Xmm3[16];\r | |
161 | UINT8 Xmm4[16];\r | |
162 | UINT8 Xmm5[16];\r | |
163 | UINT8 Xmm6[16];\r | |
164 | UINT8 Xmm7[16];\r | |
165 | UINT8 Reserved11[14 * 16];\r | |
166 | } DEBUG_DATA_IA32_FX_SAVE_STATE;\r | |
167 | \r | |
168 | ///\r | |
169 | /// IA-32 processor context definition\r | |
170 | ///\r | |
171 | typedef struct {\r | |
172 | UINT32 ExceptionData;\r | |
173 | DEBUG_DATA_IA32_FX_SAVE_STATE FxSaveState;\r | |
174 | UINT32 Dr0;\r | |
175 | UINT32 Dr1;\r | |
176 | UINT32 Dr2;\r | |
177 | UINT32 Dr3;\r | |
178 | UINT32 Dr6;\r | |
179 | UINT32 Dr7;\r | |
180 | UINT32 Eflags;\r | |
181 | UINT32 Ldtr;\r | |
182 | UINT32 Tr;\r | |
183 | UINT32 Gdtr[2];\r | |
184 | UINT32 Idtr[2];\r | |
185 | UINT32 Eip;\r | |
186 | UINT32 Gs;\r | |
187 | UINT32 Fs;\r | |
188 | UINT32 Es;\r | |
189 | UINT32 Ds;\r | |
190 | UINT32 Cs;\r | |
191 | UINT32 Ss;\r | |
192 | UINT32 Cr0;\r | |
193 | UINT32 Cr1; ///< Reserved\r | |
194 | UINT32 Cr2;\r | |
195 | UINT32 Cr3;\r | |
196 | UINT32 Cr4;\r | |
197 | UINT32 Edi;\r | |
198 | UINT32 Esi;\r | |
199 | UINT32 Ebp;\r | |
200 | UINT32 Esp;\r | |
201 | UINT32 Edx;\r | |
202 | UINT32 Ecx;\r | |
203 | UINT32 Ebx;\r | |
204 | UINT32 Eax;\r | |
205 | } DEBUG_DATA_IA32_SYSTEM_CONTEXT;\r | |
206 | \r | |
207 | ///\r | |
208 | /// FXSAVE_STATE\r | |
209 | /// FP / MMX / XMM registers (see fxrstor instruction definition)\r | |
210 | ///\r | |
211 | typedef struct {\r | |
212 | UINT16 Fcw;\r | |
213 | UINT16 Fsw;\r | |
214 | UINT16 Ftw;\r | |
215 | UINT16 Opcode;\r | |
216 | UINT32 Eip;\r | |
217 | UINT16 Cs;\r | |
218 | UINT16 Reserved1;\r | |
219 | UINT32 DataOffset;\r | |
220 | UINT16 Ds;\r | |
221 | UINT8 Reserved2[2];\r | |
222 | UINT32 Mxcsr;\r | |
223 | UINT32 Mxcsr_Mask;\r | |
224 | UINT8 St0Mm0[10];\r | |
225 | UINT8 Reserved3[6];\r | |
226 | UINT8 St1Mm1[10];\r | |
227 | UINT8 Reserved4[6];\r | |
228 | UINT8 St2Mm2[10];\r | |
229 | UINT8 Reserved5[6];\r | |
230 | UINT8 St3Mm3[10];\r | |
231 | UINT8 Reserved6[6];\r | |
232 | UINT8 St4Mm4[10];\r | |
233 | UINT8 Reserved7[6];\r | |
234 | UINT8 St5Mm5[10];\r | |
235 | UINT8 Reserved8[6];\r | |
236 | UINT8 St6Mm6[10];\r | |
237 | UINT8 Reserved9[6];\r | |
238 | UINT8 St7Mm7[10];\r | |
239 | UINT8 Reserved10[6];\r | |
240 | UINT8 Xmm0[16];\r | |
241 | UINT8 Xmm1[16];\r | |
242 | UINT8 Xmm2[16];\r | |
243 | UINT8 Xmm3[16];\r | |
244 | UINT8 Xmm4[16];\r | |
245 | UINT8 Xmm5[16];\r | |
246 | UINT8 Xmm6[16];\r | |
247 | UINT8 Xmm7[16];\r | |
248 | UINT8 Xmm8[16];\r | |
249 | UINT8 Xmm9[16];\r | |
250 | UINT8 Xmm10[16];\r | |
251 | UINT8 Xmm11[16];\r | |
252 | UINT8 Xmm12[16];\r | |
253 | UINT8 Xmm13[16];\r | |
254 | UINT8 Xmm14[16];\r | |
255 | UINT8 Xmm15[16];\r | |
256 | UINT8 Reserved11[6 * 16];\r | |
257 | } DEBUG_DATA_X64_FX_SAVE_STATE;\r | |
258 | \r | |
259 | ///\r | |
260 | /// x64 processor context definition\r | |
261 | ///\r | |
262 | typedef struct {\r | |
263 | UINT64 ExceptionData;\r | |
264 | DEBUG_DATA_X64_FX_SAVE_STATE FxSaveState;\r | |
265 | UINT64 Dr0;\r | |
266 | UINT64 Dr1;\r | |
267 | UINT64 Dr2;\r | |
268 | UINT64 Dr3;\r | |
269 | UINT64 Dr6;\r | |
270 | UINT64 Dr7;\r | |
271 | UINT64 Eflags;\r | |
272 | UINT64 Ldtr;\r | |
273 | UINT64 Tr;\r | |
274 | UINT64 Gdtr[2];\r | |
275 | UINT64 Idtr[2];\r | |
276 | UINT64 Eip;\r | |
277 | UINT64 Gs;\r | |
278 | UINT64 Fs;\r | |
279 | UINT64 Es;\r | |
280 | UINT64 Ds;\r | |
281 | UINT64 Cs;\r | |
282 | UINT64 Ss;\r | |
283 | UINT64 Cr0;\r | |
284 | UINT64 Cr1; ///< Reserved\r | |
285 | UINT64 Cr2;\r | |
286 | UINT64 Cr3;\r | |
287 | UINT64 Cr4;\r | |
288 | UINT64 Rdi;\r | |
289 | UINT64 Rsi;\r | |
290 | UINT64 Rbp;\r | |
291 | UINT64 Rsp;\r | |
292 | UINT64 Rdx;\r | |
293 | UINT64 Rcx;\r | |
294 | UINT64 Rbx;\r | |
295 | UINT64 Rax;\r | |
296 | UINT64 Cr8;\r | |
297 | UINT64 R8;\r | |
298 | UINT64 R9;\r | |
299 | UINT64 R10;\r | |
300 | UINT64 R11;\r | |
301 | UINT64 R12;\r | |
302 | UINT64 R13;\r | |
303 | UINT64 R14;\r | |
304 | UINT64 R15;\r | |
305 | } DEBUG_DATA_X64_SYSTEM_CONTEXT;\r | |
18b144ea | 306 | \r |
93c0bdec | 307 | #pragma pack()\r |
18b144ea | 308 | \r |
309 | #endif\r | |
310 | \r |