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f6ab0cee | 1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2006, Intel Corporation. All rights reserved. \r | |
4 | This software and associated documentation (if any) is furnished\r | |
5 | under a license and may only be used or copied in accordance\r | |
6 | with the terms of the license. Except as permitted by such\r | |
7 | license, no part of this software or documentation may be\r | |
8 | reproduced, stored in a retrieval system, or transmitted in any\r | |
9 | form or by any means without the express written consent of\r | |
10 | Intel Corporation.\r | |
11 | \r | |
12 | \r | |
13 | Module Name:\r | |
14 | \r | |
15 | MemoryMappedConfigurationSpaceAccessTable.h\r | |
16 | \r | |
17 | Abstract:\r | |
18 | \r | |
19 | ACPI memory mapped configuration space access table definition, defined at \r | |
20 | in the PCI Firmware Specification, version 3.0 draft version 0.5.\r | |
21 | Specification is available at http://www.pcisig.com.\r | |
22 | \r | |
23 | --*/\r | |
24 | \r | |
25 | #ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_\r | |
26 | #define _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_\r | |
27 | \r | |
28 | //\r | |
29 | // Ensure proper structure formats\r | |
30 | //\r | |
31 | #pragma pack(1)\r | |
32 | //\r | |
33 | // Memory Mapped Configuration Space Access Table (MCFG)\r | |
34 | // This table is a basic description table header followed by\r | |
35 | // a number of base address allocation structures.\r | |
36 | //\r | |
37 | typedef struct {\r | |
38 | UINT64 BaseAddress;\r | |
39 | UINT16 PciSegmentGroupNumber;\r | |
40 | UINT8 StartBusNumber;\r | |
41 | UINT8 EndBusNumber;\r | |
42 | UINT32 Reserved;\r | |
43 | } EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;\r | |
44 | \r | |
45 | //\r | |
46 | // MCFG Revision (defined in spec)\r | |
47 | //\r | |
48 | #define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION 0x01\r | |
49 | \r | |
50 | #pragma pack()\r | |
51 | \r | |
52 | #endif\r |