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21b50a27 | 1 | /** @file\r |
2 | DebugSupport protocol and supporting definitions as defined in the EFI 1.1\r | |
3 | specification.\r | |
4 | \r | |
5 | The DebugSupport protocol is used by source level debuggers to abstract the\r | |
6 | processor and handle context save and restore operations.\r | |
7 | \r | |
8 | Copyright (c) 2006, Intel Corporation \r | |
9 | All rights reserved. This program and the accompanying materials \r | |
10 | are licensed and made available under the terms and conditions of the BSD License \r | |
11 | which accompanies this distribution. The full text of the license may be found at \r | |
12 | http://opensource.org/licenses/bsd-license.php \r | |
13 | \r | |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
16 | \r | |
17 | Module Name: DebugSupport.h\r | |
18 | \r | |
19 | **/\r | |
20 | \r | |
21 | #ifndef __DEBUG_SUPPORT_H__\r | |
22 | #define __DEBUG_SUPPORT_H__\r | |
23 | \r | |
24 | typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;\r | |
25 | \r | |
26 | //\r | |
27 | // Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}\r | |
28 | //\r | |
29 | #define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r | |
30 | { \\r | |
31 | 0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \\r | |
32 | }\r | |
33 | \r | |
34 | //\r | |
35 | // Debug Support definitions\r | |
36 | //\r | |
37 | typedef INTN EFI_EXCEPTION_TYPE;\r | |
38 | \r | |
39 | //\r | |
40 | // IA-32 processor exception types\r | |
41 | //\r | |
42 | #define EXCEPT_IA32_DIVIDE_ERROR 0\r | |
43 | #define EXCEPT_IA32_DEBUG 1\r | |
44 | #define EXCEPT_IA32_NMI 2\r | |
45 | #define EXCEPT_IA32_BREAKPOINT 3\r | |
46 | #define EXCEPT_IA32_OVERFLOW 4\r | |
47 | #define EXCEPT_IA32_BOUND 5\r | |
48 | #define EXCEPT_IA32_INVALID_OPCODE 6\r | |
49 | #define EXCEPT_IA32_DOUBLE_FAULT 8\r | |
50 | #define EXCEPT_IA32_INVALID_TSS 10\r | |
51 | #define EXCEPT_IA32_SEG_NOT_PRESENT 11\r | |
52 | #define EXCEPT_IA32_STACK_FAULT 12\r | |
53 | #define EXCEPT_IA32_GP_FAULT 13\r | |
54 | #define EXCEPT_IA32_PAGE_FAULT 14\r | |
55 | #define EXCEPT_IA32_FP_ERROR 16\r | |
56 | #define EXCEPT_IA32_ALIGNMENT_CHECK 17\r | |
57 | #define EXCEPT_IA32_MACHINE_CHECK 18\r | |
58 | #define EXCEPT_IA32_SIMD 19\r | |
59 | \r | |
60 | //\r | |
61 | // IA-32 processor context definition\r | |
62 | //\r | |
63 | //\r | |
64 | // FXSAVE_STATE\r | |
65 | // FP / MMX / XMM registers (see fxrstor instruction definition)\r | |
66 | //\r | |
67 | typedef struct {\r | |
68 | UINT16 Fcw;\r | |
69 | UINT16 Fsw;\r | |
70 | UINT16 Ftw;\r | |
71 | UINT16 Opcode;\r | |
72 | UINT32 Eip;\r | |
73 | UINT16 Cs;\r | |
74 | UINT16 Reserved1;\r | |
75 | UINT32 DataOffset;\r | |
76 | UINT16 Ds;\r | |
77 | UINT8 Reserved2[10];\r | |
78 | UINT8 St0Mm0[10], Reserved3[6];\r | |
79 | UINT8 St0Mm1[10], Reserved4[6];\r | |
80 | UINT8 St0Mm2[10], Reserved5[6];\r | |
81 | UINT8 St0Mm3[10], Reserved6[6];\r | |
82 | UINT8 St0Mm4[10], Reserved7[6];\r | |
83 | UINT8 St0Mm5[10], Reserved8[6];\r | |
84 | UINT8 St0Mm6[10], Reserved9[6];\r | |
85 | UINT8 St0Mm7[10], Reserved10[6];\r | |
86 | UINT8 Reserved11[22 * 16];\r | |
87 | } EFI_FX_SAVE_STATE_IA32;\r | |
88 | \r | |
89 | typedef struct {\r | |
90 | UINT32 ExceptionData;\r | |
91 | EFI_FX_SAVE_STATE_IA32 FxSaveState;\r | |
92 | UINT32 Dr0;\r | |
93 | UINT32 Dr1;\r | |
94 | UINT32 Dr2;\r | |
95 | UINT32 Dr3;\r | |
96 | UINT32 Dr6;\r | |
97 | UINT32 Dr7;\r | |
98 | UINT32 Cr0;\r | |
99 | UINT32 Cr1; \r | |
100 | UINT32 Cr2;\r | |
101 | UINT32 Cr3;\r | |
102 | UINT32 Cr4;\r | |
103 | UINT32 Eflags;\r | |
104 | UINT32 Ldtr;\r | |
105 | UINT32 Tr;\r | |
106 | UINT32 Gdtr[2];\r | |
107 | UINT32 Idtr[2];\r | |
108 | UINT32 Eip;\r | |
109 | UINT32 Gs;\r | |
110 | UINT32 Fs;\r | |
111 | UINT32 Es;\r | |
112 | UINT32 Ds;\r | |
113 | UINT32 Cs;\r | |
114 | UINT32 Ss;\r | |
115 | UINT32 Edi;\r | |
116 | UINT32 Esi;\r | |
117 | UINT32 Ebp;\r | |
118 | UINT32 Esp;\r | |
119 | UINT32 Ebx;\r | |
120 | UINT32 Edx;\r | |
121 | UINT32 Ecx;\r | |
122 | UINT32 Eax;\r | |
123 | } EFI_SYSTEM_CONTEXT_IA32;\r | |
124 | \r | |
125 | //\r | |
126 | // IPF processor exception types\r | |
127 | //\r | |
128 | #define EXCEPT_IPF_VHTP_TRANSLATION 0\r | |
129 | #define EXCEPT_IPF_INSTRUCTION_TLB 1\r | |
130 | #define EXCEPT_IPF_DATA_TLB 2\r | |
131 | #define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r | |
132 | #define EXCEPT_IPF_ALT_DATA_TLB 4\r | |
133 | #define EXCEPT_IPF_DATA_NESTED_TLB 5\r | |
134 | #define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r | |
135 | #define EXCEPT_IPF_DATA_KEY_MISSED 7\r | |
136 | #define EXCEPT_IPF_DIRTY_BIT 8\r | |
137 | #define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r | |
138 | #define EXCEPT_IPF_DATA_ACCESS_BIT 10\r | |
139 | #define EXCEPT_IPF_BREAKPOINT 11\r | |
140 | #define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r | |
141 | //\r | |
142 | // 13 - 19 reserved\r | |
143 | //\r | |
144 | #define EXCEPT_IPF_PAGE_NOT_PRESENT 20\r | |
145 | #define EXCEPT_IPF_KEY_PERMISSION 21\r | |
146 | #define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22\r | |
147 | #define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23\r | |
148 | #define EXCEPT_IPF_GENERAL_EXCEPTION 24\r | |
149 | #define EXCEPT_IPF_DISABLED_FP_REGISTER 25\r | |
150 | #define EXCEPT_IPF_NAT_CONSUMPTION 26\r | |
151 | #define EXCEPT_IPF_SPECULATION 27\r | |
152 | //\r | |
153 | // 28 reserved\r | |
154 | //\r | |
155 | #define EXCEPT_IPF_DEBUG 29\r | |
156 | #define EXCEPT_IPF_UNALIGNED_REFERENCE 30\r | |
157 | #define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31\r | |
158 | #define EXCEPT_IPF_FP_FAULT 32\r | |
159 | #define EXCEPT_IPF_FP_TRAP 33\r | |
160 | #define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34\r | |
161 | #define EXCEPT_IPF_TAKEN_BRANCH 35\r | |
162 | #define EXCEPT_IPF_SINGLE_STEP 36\r | |
163 | //\r | |
164 | // 37 - 44 reserved\r | |
165 | //\r | |
166 | #define EXCEPT_IPF_IA32_EXCEPTION 45\r | |
167 | #define EXCEPT_IPF_IA32_INTERCEPT 46\r | |
168 | #define EXCEPT_IPF_IA32_INTERRUPT 47\r | |
169 | \r | |
170 | //\r | |
171 | // IPF processor context definition\r | |
172 | //\r | |
173 | typedef struct {\r | |
174 | //\r | |
175 | // The first reserved field is necessary to preserve alignment for the correct\r | |
176 | // bits in UNAT and to insure F2 is 16 byte aligned..\r | |
177 | //\r | |
178 | UINT64 Reserved;\r | |
179 | UINT64 R1;\r | |
180 | UINT64 R2;\r | |
181 | UINT64 R3;\r | |
182 | UINT64 R4;\r | |
183 | UINT64 R5;\r | |
184 | UINT64 R6;\r | |
185 | UINT64 R7;\r | |
186 | UINT64 R8;\r | |
187 | UINT64 R9;\r | |
188 | UINT64 R10;\r | |
189 | UINT64 R11;\r | |
190 | UINT64 R12;\r | |
191 | UINT64 R13;\r | |
192 | UINT64 R14;\r | |
193 | UINT64 R15;\r | |
194 | UINT64 R16;\r | |
195 | UINT64 R17;\r | |
196 | UINT64 R18;\r | |
197 | UINT64 R19;\r | |
198 | UINT64 R20;\r | |
199 | UINT64 R21;\r | |
200 | UINT64 R22;\r | |
201 | UINT64 R23;\r | |
202 | UINT64 R24;\r | |
203 | UINT64 R25;\r | |
204 | UINT64 R26;\r | |
205 | UINT64 R27;\r | |
206 | UINT64 R28;\r | |
207 | UINT64 R29;\r | |
208 | UINT64 R30;\r | |
209 | UINT64 R31;\r | |
210 | \r | |
211 | UINT64 F2[2];\r | |
212 | UINT64 F3[2];\r | |
213 | UINT64 F4[2];\r | |
214 | UINT64 F5[2];\r | |
215 | UINT64 F6[2];\r | |
216 | UINT64 F7[2];\r | |
217 | UINT64 F8[2];\r | |
218 | UINT64 F9[2];\r | |
219 | UINT64 F10[2];\r | |
220 | UINT64 F11[2];\r | |
221 | UINT64 F12[2];\r | |
222 | UINT64 F13[2];\r | |
223 | UINT64 F14[2];\r | |
224 | UINT64 F15[2];\r | |
225 | UINT64 F16[2];\r | |
226 | UINT64 F17[2];\r | |
227 | UINT64 F18[2];\r | |
228 | UINT64 F19[2];\r | |
229 | UINT64 F20[2];\r | |
230 | UINT64 F21[2];\r | |
231 | UINT64 F22[2];\r | |
232 | UINT64 F23[2];\r | |
233 | UINT64 F24[2];\r | |
234 | UINT64 F25[2];\r | |
235 | UINT64 F26[2];\r | |
236 | UINT64 F27[2];\r | |
237 | UINT64 F28[2];\r | |
238 | UINT64 F29[2];\r | |
239 | UINT64 F30[2];\r | |
240 | UINT64 F31[2];\r | |
241 | \r | |
242 | UINT64 Pr;\r | |
243 | \r | |
244 | UINT64 B0;\r | |
245 | UINT64 B1;\r | |
246 | UINT64 B2;\r | |
247 | UINT64 B3;\r | |
248 | UINT64 B4;\r | |
249 | UINT64 B5;\r | |
250 | UINT64 B6;\r | |
251 | UINT64 B7;\r | |
252 | \r | |
253 | //\r | |
254 | // application registers\r | |
255 | //\r | |
256 | UINT64 ArRsc;\r | |
257 | UINT64 ArBsp;\r | |
258 | UINT64 ArBspstore;\r | |
259 | UINT64 ArRnat;\r | |
260 | \r | |
261 | UINT64 ArFcr;\r | |
262 | \r | |
263 | UINT64 ArEflag;\r | |
264 | UINT64 ArCsd;\r | |
265 | UINT64 ArSsd;\r | |
266 | UINT64 ArCflg;\r | |
267 | UINT64 ArFsr;\r | |
268 | UINT64 ArFir;\r | |
269 | UINT64 ArFdr;\r | |
270 | \r | |
271 | UINT64 ArCcv;\r | |
272 | \r | |
273 | UINT64 ArUnat;\r | |
274 | \r | |
275 | UINT64 ArFpsr;\r | |
276 | \r | |
277 | UINT64 ArPfs;\r | |
278 | UINT64 ArLc;\r | |
279 | UINT64 ArEc;\r | |
280 | \r | |
281 | //\r | |
282 | // control registers\r | |
283 | //\r | |
284 | UINT64 CrDcr;\r | |
285 | UINT64 CrItm;\r | |
286 | UINT64 CrIva;\r | |
287 | UINT64 CrPta;\r | |
288 | UINT64 CrIpsr;\r | |
289 | UINT64 CrIsr;\r | |
290 | UINT64 CrIip;\r | |
291 | UINT64 CrIfa;\r | |
292 | UINT64 CrItir;\r | |
293 | UINT64 CrIipa;\r | |
294 | UINT64 CrIfs;\r | |
295 | UINT64 CrIim;\r | |
296 | UINT64 CrIha;\r | |
297 | \r | |
298 | //\r | |
299 | // debug registers\r | |
300 | //\r | |
301 | UINT64 Dbr0;\r | |
302 | UINT64 Dbr1;\r | |
303 | UINT64 Dbr2;\r | |
304 | UINT64 Dbr3;\r | |
305 | UINT64 Dbr4;\r | |
306 | UINT64 Dbr5;\r | |
307 | UINT64 Dbr6;\r | |
308 | UINT64 Dbr7;\r | |
309 | \r | |
310 | UINT64 Ibr0;\r | |
311 | UINT64 Ibr1;\r | |
312 | UINT64 Ibr2;\r | |
313 | UINT64 Ibr3;\r | |
314 | UINT64 Ibr4;\r | |
315 | UINT64 Ibr5;\r | |
316 | UINT64 Ibr6;\r | |
317 | UINT64 Ibr7;\r | |
318 | \r | |
319 | //\r | |
320 | // virtual registers - nat bits for R1-R31\r | |
321 | //\r | |
322 | UINT64 IntNat;\r | |
323 | \r | |
324 | } EFI_SYSTEM_CONTEXT_IPF;\r | |
325 | \r | |
326 | //\r | |
327 | // EBC processor exception types\r | |
328 | //\r | |
329 | #define EXCEPT_EBC_UNDEFINED 0\r | |
330 | #define EXCEPT_EBC_DIVIDE_ERROR 1\r | |
331 | #define EXCEPT_EBC_DEBUG 2\r | |
332 | #define EXCEPT_EBC_BREAKPOINT 3\r | |
333 | #define EXCEPT_EBC_OVERFLOW 4\r | |
334 | #define EXCEPT_EBC_INVALID_OPCODE 5 // opcode out of range\r | |
335 | #define EXCEPT_EBC_STACK_FAULT 6\r | |
336 | #define EXCEPT_EBC_ALIGNMENT_CHECK 7\r | |
337 | #define EXCEPT_EBC_INSTRUCTION_ENCODING 8 // malformed instruction\r | |
338 | #define EXCEPT_EBC_BAD_BREAK 9 // BREAK 0 or undefined BREAK\r | |
339 | #define EXCEPT_EBC_STEP 10 // to support debug stepping\r | |
340 | //\r | |
341 | // For coding convenience, define the maximum valid EBC exception.\r | |
342 | //\r | |
343 | #define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r | |
344 | \r | |
345 | //\r | |
346 | // EBC processor context definition\r | |
347 | //\r | |
348 | typedef struct {\r | |
349 | UINT64 R0;\r | |
350 | UINT64 R1;\r | |
351 | UINT64 R2;\r | |
352 | UINT64 R3;\r | |
353 | UINT64 R4;\r | |
354 | UINT64 R5;\r | |
355 | UINT64 R6;\r | |
356 | UINT64 R7;\r | |
357 | UINT64 Flags;\r | |
358 | UINT64 ControlFlags;\r | |
359 | UINT64 Ip;\r | |
360 | } EFI_SYSTEM_CONTEXT_EBC;\r | |
361 | \r | |
362 | //\r | |
363 | // Universal EFI_SYSTEM_CONTEXT definition\r | |
364 | //\r | |
365 | typedef union {\r | |
366 | EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r | |
367 | EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r | |
368 | EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r | |
369 | } EFI_SYSTEM_CONTEXT;\r | |
370 | \r | |
371 | //\r | |
372 | // DebugSupport callback function prototypes\r | |
373 | //\r | |
374 | \r | |
375 | /** \r | |
376 | Registers and enables an exception callback function for the specified exception.\r | |
377 | \r | |
378 | @param ExceptionType Exception types in EBC, IA-32, X64, or IPF\r | |
379 | @param SystemContext Exception content.\r | |
380 | \r | |
381 | **/\r | |
382 | typedef\r | |
383 | VOID\r | |
384 | (*EFI_EXCEPTION_CALLBACK) (\r | |
385 | IN EFI_EXCEPTION_TYPE ExceptionType,\r | |
386 | IN OUT EFI_SYSTEM_CONTEXT SystemContext\r | |
387 | );\r | |
388 | \r | |
389 | /** \r | |
390 |