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a47463f2 | 1 | /** @file\r |
2 | CPU DXE Module.\r | |
3 | \r | |
e41aad15 | 4 | Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r |
01a1c0fc | 5 | This program and the accompanying materials\r |
a47463f2 | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include "CpuDxe.h"\r | |
6022e28c | 16 | #include "CpuMp.h"\r |
a47463f2 | 17 | \r |
18 | //\r | |
19 | // Global Variables\r | |
20 | //\r | |
a47463f2 | 21 | BOOLEAN InterruptState = FALSE;\r |
22 | EFI_HANDLE mCpuHandle = NULL;\r | |
23 | BOOLEAN mIsFlushingGCD;\r | |
a47463f2 | 24 | UINT64 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;\r |
25 | UINT64 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;\r | |
26 | \r | |
27 | FIXED_MTRR mFixedMtrrTable[] = {\r | |
28 | {\r | |
29 | MTRR_LIB_IA32_MTRR_FIX64K_00000,\r | |
30 | 0,\r | |
31 | 0x10000\r | |
32 | },\r | |
33 | {\r | |
34 | MTRR_LIB_IA32_MTRR_FIX16K_80000,\r | |
35 | 0x80000,\r | |
36 | 0x4000\r | |
37 | },\r | |
38 | {\r | |
39 | MTRR_LIB_IA32_MTRR_FIX16K_A0000,\r | |
40 | 0xA0000,\r | |
41 | 0x4000\r | |
42 | },\r | |
43 | {\r | |
44 | MTRR_LIB_IA32_MTRR_FIX4K_C0000,\r | |
45 | 0xC0000,\r | |
46 | 0x1000\r | |
47 | },\r | |
48 | {\r | |
49 | MTRR_LIB_IA32_MTRR_FIX4K_C8000,\r | |
50 | 0xC8000,\r | |
51 | 0x1000\r | |
52 | },\r | |
53 | {\r | |
54 | MTRR_LIB_IA32_MTRR_FIX4K_D0000,\r | |
55 | 0xD0000,\r | |
56 | 0x1000\r | |
57 | },\r | |
58 | {\r | |
59 | MTRR_LIB_IA32_MTRR_FIX4K_D8000,\r | |
60 | 0xD8000,\r | |
61 | 0x1000\r | |
62 | },\r | |
63 | {\r | |
64 | MTRR_LIB_IA32_MTRR_FIX4K_E0000,\r | |
65 | 0xE0000,\r | |
66 | 0x1000\r | |
67 | },\r | |
68 | {\r | |
69 | MTRR_LIB_IA32_MTRR_FIX4K_E8000,\r | |
70 | 0xE8000,\r | |
71 | 0x1000\r | |
72 | },\r | |
73 | {\r | |
74 | MTRR_LIB_IA32_MTRR_FIX4K_F0000,\r | |
75 | 0xF0000,\r | |
76 | 0x1000\r | |
77 | },\r | |
78 | {\r | |
79 | MTRR_LIB_IA32_MTRR_FIX4K_F8000,\r | |
80 | 0xF8000,\r | |
81 | 0x1000\r | |
82 | },\r | |
83 | };\r | |
84 | \r | |
85 | \r | |
86 | EFI_CPU_ARCH_PROTOCOL gCpu = {\r | |
87 | CpuFlushCpuDataCache,\r | |
88 | CpuEnableInterrupt,\r | |
89 | CpuDisableInterrupt,\r | |
90 | CpuGetInterruptState,\r | |
91 | CpuInit,\r | |
92 | CpuRegisterInterruptHandler,\r | |
93 | CpuGetTimerValue,\r | |
94 | CpuSetMemoryAttributes,\r | |
95 | 1, // NumberOfTimers\r | |
96 | 4 // DmaBufferAlignment\r | |
97 | };\r | |
98 | \r | |
a47463f2 | 99 | //\r |
100 | // CPU Arch Protocol Functions\r | |
101 | //\r | |
102 | \r | |
a47463f2 | 103 | /**\r |
104 | Flush CPU data cache. If the instruction cache is fully coherent\r | |
105 | with all DMA operations then function can just return EFI_SUCCESS.\r | |
106 | \r | |
107 | @param This Protocol instance structure\r | |
108 | @param Start Physical address to start flushing from.\r | |
109 | @param Length Number of bytes to flush. Round up to chipset\r | |
110 | granularity.\r | |
111 | @param FlushType Specifies the type of flush operation to perform.\r | |
112 | \r | |
113 | @retval EFI_SUCCESS If cache was flushed\r | |
114 | @retval EFI_UNSUPPORTED If flush type is not supported.\r | |
115 | @retval EFI_DEVICE_ERROR If requested range could not be flushed.\r | |
116 | \r | |
117 | **/\r | |
118 | EFI_STATUS\r | |
119 | EFIAPI\r | |
120 | CpuFlushCpuDataCache (\r | |
121 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
122 | IN EFI_PHYSICAL_ADDRESS Start,\r | |
123 | IN UINT64 Length,\r | |
124 | IN EFI_CPU_FLUSH_TYPE FlushType\r | |
125 | )\r | |
126 | {\r | |
127 | if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {\r | |
128 | AsmWbinvd ();\r | |
129 | return EFI_SUCCESS;\r | |
130 | } else if (FlushType == EfiCpuFlushTypeInvalidate) {\r | |
131 | AsmInvd ();\r | |
132 | return EFI_SUCCESS;\r | |
133 | } else {\r | |
134 | return EFI_UNSUPPORTED;\r | |
135 | }\r | |
136 | }\r | |
137 | \r | |
138 | \r | |
139 | /**\r | |
140 | Enables CPU interrupts.\r | |
141 | \r | |
142 | @param This Protocol instance structure\r | |
143 | \r | |
144 | @retval EFI_SUCCESS If interrupts were enabled in the CPU\r | |
145 | @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.\r | |
146 | \r | |
147 | **/\r | |
148 | EFI_STATUS\r | |
149 | EFIAPI\r | |
150 | CpuEnableInterrupt (\r | |
151 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
152 | )\r | |
153 | {\r | |
154 | EnableInterrupts ();\r | |
155 | \r | |
156 | InterruptState = TRUE;\r | |
157 | return EFI_SUCCESS;\r | |
158 | }\r | |
159 | \r | |
160 | \r | |
161 | /**\r | |
162 | Disables CPU interrupts.\r | |
163 | \r | |
164 | @param This Protocol instance structure\r | |
165 | \r | |
166 | @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r | |
167 | @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.\r | |
168 | \r | |
169 | **/\r | |
170 | EFI_STATUS\r | |
171 | EFIAPI\r | |
172 | CpuDisableInterrupt (\r | |
173 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
174 | )\r | |
175 | {\r | |
176 | DisableInterrupts ();\r | |
177 | \r | |
178 | InterruptState = FALSE;\r | |
179 | return EFI_SUCCESS;\r | |
180 | }\r | |
181 | \r | |
182 | \r | |
183 | /**\r | |
184 | Return the state of interrupts.\r | |
185 | \r | |
186 | @param This Protocol instance structure\r | |
187 | @param State Pointer to the CPU's current interrupt state\r | |
188 | \r | |
189 | @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r | |
190 | @retval EFI_INVALID_PARAMETER State is NULL.\r | |
191 | \r | |
192 | **/\r | |
193 | EFI_STATUS\r | |
194 | EFIAPI\r | |
195 | CpuGetInterruptState (\r | |
196 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
197 | OUT BOOLEAN *State\r | |
198 | )\r | |
199 | {\r | |
200 | if (State == NULL) {\r | |
201 | return EFI_INVALID_PARAMETER;\r | |
202 | }\r | |
203 | \r | |
204 | *State = InterruptState;\r | |
205 | return EFI_SUCCESS;\r | |
206 | }\r | |
207 | \r | |
208 | \r | |
209 | /**\r | |
210 | Generates an INIT to the CPU.\r | |
211 | \r | |
212 | @param This Protocol instance structure\r | |
213 | @param InitType Type of CPU INIT to perform\r | |
214 | \r | |
215 | @retval EFI_SUCCESS If CPU INIT occurred. This value should never be\r | |
216 | seen.\r | |
217 | @retval EFI_DEVICE_ERROR If CPU INIT failed.\r | |
218 | @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.\r | |
219 | \r | |
220 | **/\r | |
221 | EFI_STATUS\r | |
222 | EFIAPI\r | |
223 | CpuInit (\r | |
224 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
225 | IN EFI_CPU_INIT_TYPE InitType\r | |
226 | )\r | |
227 | {\r | |
228 | return EFI_UNSUPPORTED;\r | |
229 | }\r | |
230 | \r | |
231 | \r | |
232 | /**\r | |
233 | Registers a function to be called from the CPU interrupt handler.\r | |
234 | \r | |
235 | @param This Protocol instance structure\r | |
236 | @param InterruptType Defines which interrupt to hook. IA-32\r | |
237 | valid range is 0x00 through 0xFF\r | |
238 | @param InterruptHandler A pointer to a function of type\r | |
239 | EFI_CPU_INTERRUPT_HANDLER that is called\r | |
240 | when a processor interrupt occurs. A null\r | |
241 | pointer is an error condition.\r | |
242 | \r | |
243 | @retval EFI_SUCCESS If handler installed or uninstalled.\r | |
244 | @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler\r | |
245 | for InterruptType was previously installed.\r | |
246 | @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for\r | |
247 | InterruptType was not previously installed.\r | |
248 | @retval EFI_UNSUPPORTED The interrupt specified by InterruptType\r | |
249 | is not supported.\r | |
250 | \r | |
251 | **/\r | |
252 | EFI_STATUS\r | |
253 | EFIAPI\r | |
254 | CpuRegisterInterruptHandler (\r | |
255 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
256 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
257 | IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r | |
258 | )\r | |
259 | {\r | |
e41aad15 | 260 | return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);\r |
a47463f2 | 261 | }\r |
262 | \r | |
263 | \r | |
264 | /**\r | |
265 | Returns a timer value from one of the CPU's internal timers. There is no\r | |
266 | inherent time interval between ticks but is a function of the CPU frequency.\r | |
267 | \r | |
268 | @param This - Protocol instance structure.\r | |
269 | @param TimerIndex - Specifies which CPU timer is requested.\r | |
270 | @param TimerValue - Pointer to the returned timer value.\r | |
271 | @param TimerPeriod - A pointer to the amount of time that passes\r | |
272 | in femtoseconds (10-15) for each increment\r | |
273 | of TimerValue. If TimerValue does not\r | |
274 | increment at a predictable rate, then 0 is\r | |
275 | returned. The amount of time that has\r | |
276 | passed between two calls to GetTimerValue()\r | |
277 | can be calculated with the formula\r | |
278 | (TimerValue2 - TimerValue1) * TimerPeriod.\r | |
279 | This parameter is optional and may be NULL.\r | |
280 | \r | |
281 | @retval EFI_SUCCESS - If the CPU timer count was returned.\r | |
282 | @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.\r | |
283 | @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.\r | |
284 | @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r | |
285 | \r | |
286 | **/\r | |
287 | EFI_STATUS\r | |
288 | EFIAPI\r | |
289 | CpuGetTimerValue (\r | |
290 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
291 | IN UINT32 TimerIndex,\r | |
292 | OUT UINT64 *TimerValue,\r | |
293 | OUT UINT64 *TimerPeriod OPTIONAL\r | |
294 | )\r | |
295 | {\r | |
296 | if (TimerValue == NULL) {\r | |
297 | return EFI_INVALID_PARAMETER;\r | |
298 | }\r | |
299 | \r | |
300 | if (TimerIndex != 0) {\r | |
301 | return EFI_INVALID_PARAMETER;\r | |
302 | }\r | |
303 | \r | |
304 | *TimerValue = AsmReadTsc ();\r | |
305 | \r | |
306 | if (TimerPeriod != NULL) {\r | |
307 | //\r | |
308 | // BugBug: Hard coded. Don't know how to do this generically\r | |
309 | //\r | |
310 | *TimerPeriod = 1000000000;\r | |
311 | }\r | |
312 | \r | |
313 | return EFI_SUCCESS;\r | |
314 | }\r | |
315 | \r | |
316 | \r | |
317 | /**\r | |
4ec21e8b | 318 | Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.\r |
319 | \r | |
320 | This function modifies the attributes for the memory region specified by BaseAddress and\r | |
321 | Length from their current attributes to the attributes specified by Attributes.\r | |
322 | \r | |
323 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
324 | @param BaseAddress The physical address that is the start address of a memory region.\r | |
325 | @param Length The size in bytes of the memory region.\r | |
326 | @param Attributes The bit mask of attributes to set for the memory region.\r | |
327 | \r | |
328 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
329 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
330 | BaseAddress and Length cannot be modified.\r | |
331 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
332 | Attributes specified an illegal combination of attributes that\r | |
333 | cannot be set together.\r | |
334 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
335 | the memory resource range.\r | |
336 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
337 | resource range specified by BaseAddress and Length.\r | |
338 | The bit mask of attributes is not support for the memory resource\r | |
339 | range specified by BaseAddress and Length.\r | |
a47463f2 | 340 | \r |
341 | **/\r | |
342 | EFI_STATUS\r | |
343 | EFIAPI\r | |
344 | CpuSetMemoryAttributes (\r | |
345 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
346 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
347 | IN UINT64 Length,\r | |
348 | IN UINT64 Attributes\r | |
349 | )\r | |
350 | {\r | |
351 | RETURN_STATUS Status;\r | |
352 | MTRR_MEMORY_CACHE_TYPE CacheType;\r | |
94941c88 LE |
353 | EFI_STATUS MpStatus;\r |
354 | EFI_MP_SERVICES_PROTOCOL *MpService;\r | |
355 | MTRR_SETTINGS MtrrSettings;\r | |
a47463f2 | 356 | \r |
947a573a | 357 | if (!IsMtrrSupported ()) {\r |
358 | return EFI_UNSUPPORTED;\r | |
359 | }\r | |
360 | \r | |
a47463f2 | 361 | //\r |
362 | // If this function is called because GCD SetMemorySpaceAttributes () is called\r | |
363 | // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory\r | |
364 | // map with MTRR values. So there is no need to modify MTRRs, just return immediately\r | |
365 | // to avoid unnecessary computing.\r | |
366 | //\r | |
367 | if (mIsFlushingGCD) {\r | |
79aca636 SEHM |
368 | DEBUG((EFI_D_INFO, " Flushing GCD\n"));\r |
369 | return EFI_SUCCESS;\r | |
370 | }\r | |
a47463f2 | 371 | \r |
372 | switch (Attributes) {\r | |
373 | case EFI_MEMORY_UC:\r | |
374 | CacheType = CacheUncacheable;\r | |
375 | break;\r | |
376 | \r | |
377 | case EFI_MEMORY_WC:\r | |
378 | CacheType = CacheWriteCombining;\r | |
379 | break;\r | |
380 | \r | |
381 | case EFI_MEMORY_WT:\r | |
382 | CacheType = CacheWriteThrough;\r | |
383 | break;\r | |
384 | \r | |
385 | case EFI_MEMORY_WP:\r | |
386 | CacheType = CacheWriteProtected;\r | |
387 | break;\r | |
388 | \r | |
389 | case EFI_MEMORY_WB:\r | |
390 | CacheType = CacheWriteBack;\r | |
391 | break;\r | |
392 | \r | |
4ec21e8b | 393 | case EFI_MEMORY_UCE:\r |
394 | case EFI_MEMORY_RP:\r | |
395 | case EFI_MEMORY_XP:\r | |
396 | case EFI_MEMORY_RUNTIME:\r | |
a47463f2 | 397 | return EFI_UNSUPPORTED;\r |
4ec21e8b | 398 | \r |
399 | default:\r | |
400 | return EFI_INVALID_PARAMETER;\r | |
a47463f2 | 401 | }\r |
402 | //\r | |
403 | // call MTRR libary function\r | |
404 | //\r | |
f877f300 | 405 | Status = MtrrSetMemoryAttribute (\r |
a47463f2 | 406 | BaseAddress,\r |
407 | Length,\r | |
408 | CacheType\r | |
409 | );\r | |
410 | \r | |
94941c88 LE |
411 | if (!RETURN_ERROR (Status)) {\r |
412 | MpStatus = gBS->LocateProtocol (\r | |
413 | &gEfiMpServiceProtocolGuid,\r | |
414 | NULL,\r | |
415 | (VOID **)&MpService\r | |
416 | );\r | |
417 | //\r | |
418 | // Synchronize the update with all APs\r | |
419 | //\r | |
420 | if (!EFI_ERROR (MpStatus)) {\r | |
421 | MtrrGetAllMtrrs (&MtrrSettings);\r | |
422 | MpStatus = MpService->StartupAllAPs (\r | |
423 | MpService, // This\r | |
424 | SetMtrrsFromBuffer, // Procedure\r | |
425 | TRUE, // SingleThread\r | |
426 | NULL, // WaitEvent\r | |
427 | 0, // TimeoutInMicrosecsond\r | |
428 | &MtrrSettings, // ProcedureArgument\r | |
429 | NULL // FailedCpuList\r | |
430 | );\r | |
431 | ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED);\r | |
432 | }\r | |
433 | }\r | |
a47463f2 | 434 | return (EFI_STATUS) Status;\r |
435 | }\r | |
436 | \r | |
437 | /**\r | |
438 | Initializes the valid bits mask and valid address mask for MTRRs.\r | |
439 | \r | |
440 | This function initializes the valid bits mask and valid address mask for MTRRs.\r | |
441 | \r | |
442 | **/\r | |
443 | VOID\r | |
444 | InitializeMtrrMask (\r | |
445 | VOID\r | |
446 | )\r | |
447 | {\r | |
448 | UINT32 RegEax;\r | |
449 | UINT8 PhysicalAddressBits;\r | |
450 | \r | |
451 | AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r | |
452 | \r | |
453 | if (RegEax >= 0x80000008) {\r | |
454 | AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r | |
455 | \r | |
456 | PhysicalAddressBits = (UINT8) RegEax;\r | |
457 | \r | |
458 | mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;\r | |
459 | mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;\r | |
460 | } else {\r | |
461 | mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;\r | |
462 | mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;\r | |
463 | }\r | |
464 | }\r | |
465 | \r | |
466 | /**\r | |
430fbbe0 | 467 | Gets GCD Mem Space type from MTRR Type.\r |
a47463f2 | 468 | \r |
430fbbe0 | 469 | This function gets GCD Mem Space type from MTRR Type.\r |
a47463f2 | 470 | \r |
430fbbe0 | 471 | @param MtrrAttributes MTRR memory type\r |
a47463f2 | 472 | \r |
473 | @return GCD Mem Space type\r | |
474 | \r | |
475 | **/\r | |
476 | UINT64\r | |
477 | GetMemorySpaceAttributeFromMtrrType (\r | |
2c4b1bdc | 478 | IN UINT8 MtrrAttributes\r |
a47463f2 | 479 | )\r |
480 | {\r | |
481 | switch (MtrrAttributes) {\r | |
482 | case MTRR_CACHE_UNCACHEABLE:\r | |
483 | return EFI_MEMORY_UC;\r | |
484 | case MTRR_CACHE_WRITE_COMBINING:\r | |
485 | return EFI_MEMORY_WC;\r | |
486 | case MTRR_CACHE_WRITE_THROUGH:\r | |
487 | return EFI_MEMORY_WT;\r | |
488 | case MTRR_CACHE_WRITE_PROTECTED:\r | |
489 | return EFI_MEMORY_WP;\r | |
490 | case MTRR_CACHE_WRITE_BACK:\r | |
491 | return EFI_MEMORY_WB;\r | |
492 | default:\r | |
493 | return 0;\r | |
494 | }\r | |
495 | }\r | |
496 | \r | |
497 | /**\r | |
498 | Searches memory descriptors covered by given memory range.\r | |
499 | \r | |
500 | This function searches into the Gcd Memory Space for descriptors\r | |
501 | (from StartIndex to EndIndex) that contains the memory range\r | |
502 | specified by BaseAddress and Length.\r | |
503 | \r | |
504 | @param MemorySpaceMap Gcd Memory Space Map as array.\r | |
505 | @param NumberOfDescriptors Number of descriptors in map.\r | |
506 | @param BaseAddress BaseAddress for the requested range.\r | |
507 | @param Length Length for the requested range.\r | |
508 | @param StartIndex Start index into the Gcd Memory Space Map.\r | |
509 | @param EndIndex End index into the Gcd Memory Space Map.\r | |
510 | \r | |
511 | @retval EFI_SUCCESS Search successfully.\r | |
512 | @retval EFI_NOT_FOUND The requested descriptors does not exist.\r | |
513 | \r | |
514 | **/\r | |
515 | EFI_STATUS\r | |
516 | SearchGcdMemorySpaces (\r | |
517 | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r | |
518 | IN UINTN NumberOfDescriptors,\r | |
519 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
520 | IN UINT64 Length,\r | |
521 | OUT UINTN *StartIndex,\r | |
522 | OUT UINTN *EndIndex\r | |
523 | )\r | |
524 | {\r | |
525 | UINTN Index;\r | |
526 | \r | |
527 | *StartIndex = 0;\r | |
528 | *EndIndex = 0;\r | |
529 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r | |
530 | if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&\r | |
531 | BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
532 | *StartIndex = Index;\r | |
533 | }\r | |
534 | if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&\r | |
535 | BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
536 | *EndIndex = Index;\r | |
537 | return EFI_SUCCESS;\r | |
538 | }\r | |
539 | }\r | |
540 | return EFI_NOT_FOUND;\r | |
541 | }\r | |
542 | \r | |
543 | /**\r | |
544 | Sets the attributes for a specified range in Gcd Memory Space Map.\r | |
545 | \r | |
546 | This function sets the attributes for a specified range in\r | |
547 | Gcd Memory Space Map.\r | |
548 | \r | |
549 | @param MemorySpaceMap Gcd Memory Space Map as array\r | |
550 | @param NumberOfDescriptors Number of descriptors in map\r | |
551 | @param BaseAddress BaseAddress for the range\r | |
552 | @param Length Length for the range\r | |
553 | @param Attributes Attributes to set\r | |
554 | \r | |
555 | @retval EFI_SUCCESS Memory attributes set successfully\r | |
556 | @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space\r | |
557 | \r | |
558 | **/\r | |
559 | EFI_STATUS\r | |
560 | SetGcdMemorySpaceAttributes (\r | |
561 | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r | |
562 | IN UINTN NumberOfDescriptors,\r | |
563 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
564 | IN UINT64 Length,\r | |
565 | IN UINT64 Attributes\r | |
566 | )\r | |
567 | {\r | |
568 | EFI_STATUS Status;\r | |
569 | UINTN Index;\r | |
570 | UINTN StartIndex;\r | |
571 | UINTN EndIndex;\r | |
572 | EFI_PHYSICAL_ADDRESS RegionStart;\r | |
573 | UINT64 RegionLength;\r | |
574 | \r | |
575 | //\r | |
576 | // Get all memory descriptors covered by the memory range\r | |
577 | //\r | |
578 | Status = SearchGcdMemorySpaces (\r | |
579 | MemorySpaceMap,\r | |
580 | NumberOfDescriptors,\r | |
581 | BaseAddress,\r | |
582 | Length,\r | |
583 | &StartIndex,\r | |
584 | &EndIndex\r | |
585 | );\r | |
586 | if (EFI_ERROR (Status)) {\r | |
587 | return Status;\r | |
588 | }\r | |
589 | \r | |
590 | //\r | |
591 | // Go through all related descriptors and set attributes accordingly\r | |
592 | //\r | |
593 | for (Index = StartIndex; Index <= EndIndex; Index++) {\r | |
594 | if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r | |
595 | continue;\r | |
596 | }\r | |
597 | //\r | |
598 | // Calculate the start and end address of the overlapping range\r | |
599 | //\r | |
600 | if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {\r | |
601 | RegionStart = BaseAddress;\r | |
602 | } else {\r | |
603 | RegionStart = MemorySpaceMap[Index].BaseAddress;\r | |
604 | }\r | |
605 | if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
606 | RegionLength = BaseAddress + Length - RegionStart;\r | |
607 | } else {\r | |
608 | RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r | |
609 | }\r | |
610 | //\r | |
611 | // Set memory attributes according to MTRR attribute and the original attribute of descriptor\r | |
612 | //\r | |
613 | gDS->SetMemorySpaceAttributes (\r | |
614 | RegionStart,\r | |
615 | RegionLength,\r | |
616 | (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)\r | |
617 | );\r | |
618 | }\r | |
619 | \r | |
620 | return EFI_SUCCESS;\r | |
621 | }\r | |
622 | \r | |
623 | \r | |
624 | /**\r | |
625 | Refreshes the GCD Memory Space attributes according to MTRRs.\r | |
626 | \r | |
627 | This function refreshes the GCD Memory Space attributes according to MTRRs.\r | |
628 | \r | |
629 | **/\r | |
630 | VOID\r | |
631 | RefreshGcdMemoryAttributes (\r | |
632 | VOID\r | |
633 | )\r | |
634 | {\r | |
635 | EFI_STATUS Status;\r | |
636 | UINTN Index;\r | |
637 | UINTN SubIndex;\r | |
638 | UINT64 RegValue;\r | |
639 | EFI_PHYSICAL_ADDRESS BaseAddress;\r | |
640 | UINT64 Length;\r | |
641 | UINT64 Attributes;\r | |
642 | UINT64 CurrentAttributes;\r | |
2c4b1bdc | 643 | UINT8 MtrrType;\r |
a47463f2 | 644 | UINTN NumberOfDescriptors;\r |
645 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r | |
646 | UINT64 DefaultAttributes;\r | |
6640eb36 | 647 | VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r |
a47463f2 | 648 | MTRR_FIXED_SETTINGS MtrrFixedSettings;\r |
3b9be416 | 649 | UINT32 FirmwareVariableMtrrCount;\r |
2c4b1bdc | 650 | UINT8 DefaultMemoryType;\r |
3b9be416 | 651 | \r |
947a573a | 652 | if (!IsMtrrSupported ()) {\r |
653 | return;\r | |
654 | }\r | |
655 | \r | |
3b9be416 | 656 | FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();\r |
5bdfa4e5 | 657 | ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r |
a47463f2 | 658 | \r |
91ec7824 | 659 | mIsFlushingGCD = TRUE;\r |
a47463f2 | 660 | MemorySpaceMap = NULL;\r |
661 | \r | |
662 | //\r | |
663 | // Initialize the valid bits mask and valid address mask for MTRRs\r | |
664 | //\r | |
665 | InitializeMtrrMask ();\r | |
666 | \r | |
667 | //\r | |
668 | // Get the memory attribute of variable MTRRs\r | |
669 | //\r | |
670 | MtrrGetMemoryAttributeInVariableMtrr (\r | |
671 | mValidMtrrBitsMask,\r | |
672 | mValidMtrrAddressMask,\r | |
673 | VariableMtrr\r | |
674 | );\r | |
675 | \r | |
676 | //\r | |
677 | // Get the memory space map from GCD\r | |
678 | //\r | |
679 | Status = gDS->GetMemorySpaceMap (\r | |
680 | &NumberOfDescriptors,\r | |
681 | &MemorySpaceMap\r | |
682 | );\r | |
683 | ASSERT_EFI_ERROR (Status);\r | |
684 | \r | |
2c4b1bdc | 685 | DefaultMemoryType = (UINT8) MtrrGetDefaultMemoryType ();\r |
91ec7824 | 686 | DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType);\r |
a47463f2 | 687 | \r |
688 | //\r | |
689 | // Set default attributes to all spaces.\r | |
690 | //\r | |
691 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r | |
692 | if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r | |
693 | continue;\r | |
694 | }\r | |
695 | gDS->SetMemorySpaceAttributes (\r | |
696 | MemorySpaceMap[Index].BaseAddress,\r | |
697 | MemorySpaceMap[Index].Length,\r | |
698 | (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |\r | |
699 | (MemorySpaceMap[Index].Capabilities & DefaultAttributes)\r | |
700 | );\r | |
701 | }\r | |
702 | \r | |
703 | //\r | |
704 | // Go for variable MTRRs with WB attribute\r | |
705 | //\r | |
3b9be416 | 706 | for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r |
a47463f2 | 707 | if (VariableMtrr[Index].Valid &&\r |
708 | VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {\r | |
709 | SetGcdMemorySpaceAttributes (\r | |
710 | MemorySpaceMap,\r | |
711 | NumberOfDescriptors,\r | |
712 | VariableMtrr[Index].BaseAddress,\r | |
713 | VariableMtrr[Index].Length,\r | |
714 | EFI_MEMORY_WB\r | |
715 | );\r | |
716 | }\r | |
717 | }\r | |
91ec7824 | 718 | \r |
a47463f2 | 719 | //\r |
91ec7824 | 720 | // Go for variable MTRRs with the attribute except for WB and UC attributes\r |
a47463f2 | 721 | //\r |
3b9be416 | 722 | for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r |
d4605c23 | 723 | if (VariableMtrr[Index].Valid &&\r |
91ec7824 | 724 | VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK &&\r |
725 | VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE) {\r | |
2c4b1bdc | 726 | Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);\r |
a47463f2 | 727 | SetGcdMemorySpaceAttributes (\r |
728 | MemorySpaceMap,\r | |
729 | NumberOfDescriptors,\r | |
730 | VariableMtrr[Index].BaseAddress,\r | |
731 | VariableMtrr[Index].Length,\r | |
732 | Attributes\r | |
733 | );\r | |
734 | }\r | |
735 | }\r | |
736 | \r | |
91ec7824 | 737 | //\r |
738 | // Go for variable MTRRs with UC attribute\r | |
739 | //\r | |
740 | for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r | |
741 | if (VariableMtrr[Index].Valid &&\r | |
742 | VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE) {\r | |
743 | SetGcdMemorySpaceAttributes (\r | |
744 | MemorySpaceMap,\r | |
745 | NumberOfDescriptors,\r | |
746 | VariableMtrr[Index].BaseAddress,\r | |
747 | VariableMtrr[Index].Length,\r | |
748 | EFI_MEMORY_UC\r | |
749 | );\r | |
750 | }\r | |
751 | }\r | |
752 | \r | |
a47463f2 | 753 | //\r |
754 | // Go for fixed MTRRs\r | |
755 | //\r | |
756 | Attributes = 0;\r | |
757 | BaseAddress = 0;\r | |
758 | Length = 0;\r | |
759 | MtrrGetFixedMtrr (&MtrrFixedSettings);\r | |
760 | for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r | |
761 | RegValue = MtrrFixedSettings.Mtrr[Index];\r | |
762 | //\r | |
763 | // Check for continuous fixed MTRR sections\r | |
764 | //\r | |
765 | for (SubIndex = 0; SubIndex < 8; SubIndex++) {\r | |
2c4b1bdc | 766 | MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);\r |
a47463f2 | 767 | CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);\r |
768 | if (Length == 0) {\r | |
769 | //\r | |
770 | // A new MTRR attribute begins\r | |
771 | //\r | |
772 | Attributes = CurrentAttributes;\r | |
773 | } else {\r | |
774 | //\r | |
775 | // If fixed MTRR attribute changed, then set memory attribute for previous atrribute\r | |
776 | //\r | |
777 | if (CurrentAttributes != Attributes) {\r | |
778 | SetGcdMemorySpaceAttributes (\r | |
779 | MemorySpaceMap,\r | |
780 | NumberOfDescriptors,\r | |
781 | BaseAddress,\r | |
782 | Length,\r | |
783 | Attributes\r | |
784 | );\r | |
785 | BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;\r | |
786 | Length = 0;\r | |
787 | Attributes = CurrentAttributes;\r | |
788 | }\r | |
789 | }\r | |
790 | Length += mFixedMtrrTable[Index].Length;\r | |
791 | }\r | |
792 | }\r | |
793 | //\r | |
794 | // Handle the last fixed MTRR region\r | |
795 | //\r | |
796 | SetGcdMemorySpaceAttributes (\r | |
797 | MemorySpaceMap,\r | |
798 | NumberOfDescriptors,\r | |
799 | BaseAddress,\r | |
800 | Length,\r | |
801 | Attributes\r | |
802 | );\r | |
803 | \r | |
804 | //\r | |
805 | // Free memory space map allocated by GCD service GetMemorySpaceMap ()\r | |
806 | //\r | |
807 | if (MemorySpaceMap != NULL) {\r | |
808 | FreePool (MemorySpaceMap);\r | |
809 | }\r | |
810 | \r | |
811 | mIsFlushingGCD = FALSE;\r | |
812 | }\r | |
813 | \r | |
a47463f2 | 814 | /**\r |
815 | Initialize Interrupt Descriptor Table for interrupt handling.\r | |
816 | \r | |
817 | **/\r | |
a47463f2 | 818 | VOID\r |
819 | InitInterruptDescriptorTable (\r | |
820 | VOID\r | |
821 | )\r | |
822 | {\r | |
e41aad15 JF |
823 | EFI_STATUS Status;\r |
824 | EFI_VECTOR_HANDOFF_INFO *VectorInfoList;\r | |
825 | EFI_VECTOR_HANDOFF_INFO *VectorInfo;\r | |
826 | \r | |
827 | VectorInfo = NULL;\r | |
828 | Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **) &VectorInfoList);\r | |
829 | if (Status == EFI_SUCCESS && VectorInfoList != NULL) {\r | |
830 | VectorInfo = VectorInfoList;\r | |
a47463f2 | 831 | }\r |
e41aad15 JF |
832 | Status = InitializeCpuInterruptHandlers (VectorInfo);\r |
833 | ASSERT_EFI_ERROR (Status);\r | |
a47463f2 | 834 | }\r |
835 | \r | |
836 | \r | |
32394027 | 837 | /**\r |
838 | Callback function for idle events.\r | |
d4605c23 | 839 | \r |
32394027 | 840 | @param Event Event whose notification function is being invoked.\r |
841 | @param Context The pointer to the notification function's context,\r | |
842 | which is implementation-dependent.\r | |
843 | \r | |
844 | **/\r | |
845 | VOID\r | |
846 | EFIAPI\r | |
847 | IdleLoopEventCallback (\r | |
848 | IN EFI_EVENT Event,\r | |
849 | IN VOID *Context\r | |
850 | )\r | |
851 | {\r | |
852 | CpuSleep ();\r | |
853 | }\r | |
854 | \r | |
855 | \r | |
a47463f2 | 856 | /**\r |
857 | Initialize the state information for the CPU Architectural Protocol.\r | |
858 | \r | |
859 | @param ImageHandle Image handle this driver.\r | |
860 | @param SystemTable Pointer to the System Table.\r | |
861 | \r | |
862 | @retval EFI_SUCCESS Thread can be successfully created\r | |
863 | @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r | |
864 | @retval EFI_DEVICE_ERROR Cannot create the thread\r | |
865 | \r | |
866 | **/\r | |
867 | EFI_STATUS\r | |
868 | EFIAPI\r | |
869 | InitializeCpu (\r | |
870 | IN EFI_HANDLE ImageHandle,\r | |
871 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
872 | )\r | |
873 | {\r | |
874 | EFI_STATUS Status;\r | |
32394027 | 875 | EFI_EVENT IdleLoopEvent;\r |
a47463f2 | 876 | \r |
661cab5d | 877 | InitializeFloatingPointUnits ();\r |
878 | \r | |
a47463f2 | 879 | //\r |
880 | // Make sure interrupts are disabled\r | |
881 | //\r | |
882 | DisableInterrupts ();\r | |
883 | \r | |
884 | //\r | |
885 | // Init GDT for DXE\r | |
886 | //\r | |
887 | InitGlobalDescriptorTable ();\r | |
888 | \r | |
889 | //\r | |
890 | // Setup IDT pointer, IDT and interrupt entry points\r | |
891 | //\r | |
892 | InitInterruptDescriptorTable ();\r | |
893 | \r | |
d4605c23 EB |
894 | //\r |
895 | // Enable the local APIC for Virtual Wire Mode.\r | |
896 | //\r | |
897 | ProgramVirtualWireMode ();\r | |
898 | \r | |
a47463f2 | 899 | //\r |
900 | // Install CPU Architectural Protocol\r | |
901 | //\r | |
902 | Status = gBS->InstallMultipleProtocolInterfaces (\r | |
903 | &mCpuHandle,\r | |
904 | &gEfiCpuArchProtocolGuid, &gCpu,\r | |
905 | NULL\r | |
906 | );\r | |
907 | ASSERT_EFI_ERROR (Status);\r | |
908 | \r | |
909 | //\r | |
910 | // Refresh GCD memory space map according to MTRR value.\r | |
911 | //\r | |
912 | RefreshGcdMemoryAttributes ();\r | |
913 | \r | |
32394027 | 914 | //\r |
915 | // Setup a callback for idle events\r | |
916 | //\r | |
917 | Status = gBS->CreateEventEx (\r | |
918 | EVT_NOTIFY_SIGNAL,\r | |
919 | TPL_NOTIFY,\r | |
920 | IdleLoopEventCallback,\r | |
921 | NULL,\r | |
922 | &gIdleLoopEventGuid,\r | |
923 | &IdleLoopEvent\r | |
924 | );\r | |
925 | ASSERT_EFI_ERROR (Status);\r | |
926 | \r | |
6022e28c JJ |
927 | InitializeMpSupport ();\r |
928 | \r | |
a47463f2 | 929 | return Status;\r |
930 | }\r | |
931 | \r |