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Commit | Line | Data |
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a47463f2 | 1 | /** @file\r |
2 | C based implemention of IA32 interrupt handling only\r | |
3 | requiring a minimal assembly interrupt entry point.\r | |
4 | \r | |
0d4c1db8 | 5 | Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a47463f2 | 7 | \r |
8 | **/\r | |
9 | \r | |
10 | #include "CpuDxe.h"\r | |
a1e8986d | 11 | #include "CpuGdt.h"\r |
a47463f2 | 12 | \r |
13 | //\r | |
14 | // Global descriptor table (GDT) Template\r | |
15 | //\r | |
16 | STATIC GDT_ENTRIES GdtTemplate = {\r | |
17 | //\r | |
18 | // NULL_SEL\r | |
19 | //\r | |
20 | {\r | |
21 | 0x0, // limit 15:0\r | |
22 | 0x0, // base 15:0\r | |
23 | 0x0, // base 23:16\r | |
24 | 0x0, // type\r | |
25 | 0x0, // limit 19:16, flags\r | |
26 | 0x0, // base 31:24\r | |
27 | },\r | |
28 | //\r | |
29 | // LINEAR_SEL\r | |
30 | //\r | |
31 | {\r | |
0d4c1db8 MK |
32 | 0x0FFFF, // limit 15:0\r |
33 | 0x0, // base 15:0\r | |
34 | 0x0, // base 23:16\r | |
35 | 0x092, // present, ring 0, data, read/write\r | |
a47463f2 | 36 | 0x0CF, // page-granular, 32-bit\r |
37 | 0x0,\r | |
38 | },\r | |
39 | //\r | |
40 | // LINEAR_CODE_SEL\r | |
41 | //\r | |
42 | {\r | |
0d4c1db8 MK |
43 | 0x0FFFF, // limit 15:0\r |
44 | 0x0, // base 15:0\r | |
45 | 0x0, // base 23:16\r | |
46 | 0x09F, // present, ring 0, code, execute/read, conforming, accessed\r | |
a47463f2 | 47 | 0x0CF, // page-granular, 32-bit\r |
48 | 0x0,\r | |
49 | },\r | |
50 | //\r | |
51 | // SYS_DATA_SEL\r | |
52 | //\r | |
53 | {\r | |
0d4c1db8 MK |
54 | 0x0FFFF, // limit 15:0\r |
55 | 0x0, // base 15:0\r | |
56 | 0x0, // base 23:16\r | |
57 | 0x093, // present, ring 0, data, read/write, accessed\r | |
a47463f2 | 58 | 0x0CF, // page-granular, 32-bit\r |
59 | 0x0,\r | |
60 | },\r | |
61 | //\r | |
62 | // SYS_CODE_SEL\r | |
63 | //\r | |
64 | {\r | |
0d4c1db8 MK |
65 | 0x0FFFF, // limit 15:0\r |
66 | 0x0, // base 15:0\r | |
67 | 0x0, // base 23:16\r | |
68 | 0x09A, // present, ring 0, code, execute/read\r | |
a47463f2 | 69 | 0x0CF, // page-granular, 32-bit\r |
70 | 0x0,\r | |
71 | },\r | |
72 | //\r | |
0d4c1db8 | 73 | // SPARE4_SEL\r |
a47463f2 | 74 | //\r |
75 | {\r | |
0d4c1db8 MK |
76 | 0x0, // limit 15:0\r |
77 | 0x0, // base 15:0\r | |
78 | 0x0, // base 23:16\r | |
79 | 0x0, // type\r | |
80 | 0x0, // limit 19:16, flags\r | |
81 | 0x0, // base 31:24\r | |
a47463f2 | 82 | },\r |
83 | //\r | |
0d4c1db8 | 84 | // LINEAR_DATA64_SEL\r |
a47463f2 | 85 | //\r |
86 | {\r | |
0d4c1db8 MK |
87 | 0x0FFFF, // limit 15:0\r |
88 | 0x0, // base 15:0\r | |
89 | 0x0, // base 23:16\r | |
90 | 0x092, // present, ring 0, data, read/write\r | |
91 | 0x0CF, // page-granular, 32-bit\r | |
a47463f2 | 92 | 0x0,\r |
93 | },\r | |
94 | //\r | |
0d4c1db8 MK |
95 | // LINEAR_CODE64_SEL\r |
96 | //\r | |
97 | {\r | |
98 | 0x0FFFF, // limit 15:0\r | |
99 | 0x0, // base 15:0\r | |
100 | 0x0, // base 23:16\r | |
101 | 0x09A, // present, ring 0, code, execute/read\r | |
102 | 0x0AF, // page-granular, 64-bit code\r | |
103 | 0x0, // base (high)\r | |
104 | },\r | |
105 | //\r | |
a47463f2 | 106 | // SPARE5_SEL\r |
107 | //\r | |
108 | {\r | |
0d4c1db8 MK |
109 | 0x0, // limit 15:0\r |
110 | 0x0, // base 15:0\r | |
111 | 0x0, // base 23:16\r | |
112 | 0x0, // type\r | |
113 | 0x0, // limit 19:16, flags\r | |
114 | 0x0, // base 31:24\r | |
a47463f2 | 115 | },\r |
116 | };\r | |
117 | \r | |
118 | /**\r | |
430fbbe0 | 119 | Initialize Global Descriptor Table.\r |
a47463f2 | 120 | \r |
121 | **/\r | |
122 | VOID\r | |
123 | InitGlobalDescriptorTable (\r | |
430fbbe0 | 124 | VOID\r |
a47463f2 | 125 | )\r |
126 | {\r | |
127 | GDT_ENTRIES *gdt;\r | |
128 | IA32_DESCRIPTOR gdtPtr;\r | |
129 | \r | |
130 | //\r | |
131 | // Allocate Runtime Data for the GDT\r | |
132 | //\r | |
133 | gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8);\r | |
134 | ASSERT (gdt != NULL);\r | |
135 | gdt = ALIGN_POINTER (gdt, 8);\r | |
136 | \r | |
137 | //\r | |
138 | // Initialize all GDT entries\r | |
139 | //\r | |
140 | CopyMem (gdt, &GdtTemplate, sizeof (GdtTemplate));\r | |
141 | \r | |
142 | //\r | |
143 | // Write GDT register\r | |
144 | //\r | |
145 | gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;\r | |
5b7e61a0 | 146 | gdtPtr.Limit = (UINT16) (sizeof (GdtTemplate) - 1);\r |
a47463f2 | 147 | AsmWriteGdtr (&gdtPtr);\r |
148 | \r | |
149 | //\r | |
150 | // Update selector (segment) registers base on new GDT\r | |
151 | //\r | |
152 | SetCodeSelector ((UINT16)CPU_CODE_SEL);\r | |
153 | SetDataSelectors ((UINT16)CPU_DATA_SEL);\r | |
154 | }\r | |
155 | \r |