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22292ed3 JY |
1 | /** @file\r |
2 | Page table management support.\r | |
3 | \r | |
4 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r | |
627dcba3 LD |
5 | Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r |
6 | \r | |
22292ed3 JY |
7 | This program and the accompanying materials\r |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #include <Base.h>\r | |
18 | #include <Uefi.h>\r | |
dcc02621 JW |
19 | #include <Library/PeCoffGetEntryPointLib.h>\r |
20 | #include <Library/SerialPortLib.h>\r | |
21 | #include <Library/SynchronizationLib.h>\r | |
22 | #include <Library/PrintLib.h>\r | |
2a1408d1 | 23 | #include <Protocol/SmmBase2.h>\r |
d106cf71 JW |
24 | #include <Register/Cpuid.h>\r |
25 | #include <Register/Msr.h>\r | |
c1cab54c JW |
26 | \r |
27 | #include "CpuDxe.h"\r | |
22292ed3 JY |
28 | #include "CpuPageTable.h"\r |
29 | \r | |
d106cf71 JW |
30 | ///\r |
31 | /// Paging registers\r | |
32 | ///\r | |
33 | #define CR0_WP BIT16\r | |
34 | #define CR0_PG BIT31\r | |
35 | #define CR4_PSE BIT4\r | |
36 | #define CR4_PAE BIT5\r | |
37 | \r | |
22292ed3 JY |
38 | ///\r |
39 | /// Page Table Entry\r | |
40 | ///\r | |
41 | #define IA32_PG_P BIT0\r | |
42 | #define IA32_PG_RW BIT1\r | |
43 | #define IA32_PG_U BIT2\r | |
44 | #define IA32_PG_WT BIT3\r | |
45 | #define IA32_PG_CD BIT4\r | |
46 | #define IA32_PG_A BIT5\r | |
47 | #define IA32_PG_D BIT6\r | |
48 | #define IA32_PG_PS BIT7\r | |
49 | #define IA32_PG_PAT_2M BIT12\r | |
50 | #define IA32_PG_PAT_4K IA32_PG_PS\r | |
51 | #define IA32_PG_PMNT BIT62\r | |
52 | #define IA32_PG_NX BIT63\r | |
53 | \r | |
54 | #define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r | |
55 | //\r | |
56 | // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r | |
57 | // X64 PAE PDPTE does not have such restriction\r | |
58 | //\r | |
59 | #define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r | |
60 | \r | |
61 | #define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r | |
62 | \r | |
63 | #define PAGING_4K_MASK 0xFFF\r | |
64 | #define PAGING_2M_MASK 0x1FFFFF\r | |
65 | #define PAGING_1G_MASK 0x3FFFFFFF\r | |
66 | \r | |
67 | #define PAGING_PAE_INDEX_MASK 0x1FF\r | |
68 | \r | |
69 | #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r | |
70 | #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r | |
71 | #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r | |
72 | \r | |
dcc02621 JW |
73 | #define MAX_PF_ENTRY_COUNT 10\r |
74 | #define MAX_DEBUG_MESSAGE_LENGTH 0x100\r | |
75 | #define IA32_PF_EC_ID BIT4\r | |
76 | \r | |
22292ed3 JY |
77 | typedef enum {\r |
78 | PageNone,\r | |
79 | Page4K,\r | |
80 | Page2M,\r | |
81 | Page1G,\r | |
82 | } PAGE_ATTRIBUTE;\r | |
83 | \r | |
84 | typedef struct {\r | |
85 | PAGE_ATTRIBUTE Attribute;\r | |
86 | UINT64 Length;\r | |
87 | UINT64 AddressMask;\r | |
88 | } PAGE_ATTRIBUTE_TABLE;\r | |
89 | \r | |
90 | typedef enum {\r | |
91 | PageActionAssign,\r | |
92 | PageActionSet,\r | |
93 | PageActionClear,\r | |
94 | } PAGE_ACTION;\r | |
95 | \r | |
96 | PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {\r | |
97 | {Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64},\r | |
98 | {Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64},\r | |
99 | {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},\r | |
100 | };\r | |
101 | \r | |
2a1408d1 JW |
102 | PAGE_TABLE_POOL *mPageTablePool = NULL;\r |
103 | PAGE_TABLE_LIB_PAGING_CONTEXT mPagingContext;\r | |
104 | EFI_SMM_BASE2_PROTOCOL *mSmmBase2 = NULL;\r | |
105 | \r | |
dcc02621 JW |
106 | //\r |
107 | // Record the page fault exception count for one instruction execution.\r | |
108 | //\r | |
109 | UINTN *mPFEntryCount;\r | |
110 | UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];\r | |
111 | \r | |
2a1408d1 JW |
112 | /**\r |
113 | Check if current execution environment is in SMM mode or not, via\r | |
114 | EFI_SMM_BASE2_PROTOCOL.\r | |
115 | \r | |
116 | This is necessary because of the fact that MdePkg\Library\SmmMemoryAllocationLib\r | |
117 | supports to free memory outside SMRAM. The library will call gBS->FreePool() or\r | |
118 | gBS->FreePages() and then SetMemorySpaceAttributes interface in turn to change\r | |
119 | memory paging attributes during free operation, if some memory related features\r | |
120 | are enabled (like Heap Guard).\r | |
121 | \r | |
122 | This means that SetMemorySpaceAttributes() has chance to run in SMM mode. This\r | |
123 | will cause incorrect result because SMM mode always loads its own page tables,\r | |
124 | which are usually different from DXE. This function can be used to detect such\r | |
125 | situation and help to avoid further misoperations.\r | |
126 | \r | |
127 | @retval TRUE In SMM mode.\r | |
128 | @retval FALSE Not in SMM mode.\r | |
129 | **/\r | |
130 | BOOLEAN\r | |
131 | IsInSmm (\r | |
132 | VOID\r | |
133 | )\r | |
134 | {\r | |
135 | BOOLEAN InSmm;\r | |
136 | \r | |
137 | InSmm = FALSE;\r | |
138 | if (mSmmBase2 == NULL) {\r | |
139 | gBS->LocateProtocol (&gEfiSmmBase2ProtocolGuid, NULL, (VOID **)&mSmmBase2);\r | |
140 | }\r | |
141 | \r | |
142 | if (mSmmBase2 != NULL) {\r | |
143 | mSmmBase2->InSmm (mSmmBase2, &InSmm);\r | |
144 | }\r | |
145 | \r | |
b72f4873 JW |
146 | //\r |
147 | // mSmmBase2->InSmm() can only detect if the caller is running in SMRAM\r | |
148 | // or from SMM driver. It cannot tell if the caller is running in SMM mode.\r | |
149 | // Check page table base address to guarantee that because SMM mode willl\r | |
150 | // load its own page table.\r | |
151 | //\r | |
152 | return (InSmm &&\r | |
153 | mPagingContext.ContextData.X64.PageTableBase != (UINT64)AsmReadCr3());\r | |
2a1408d1 | 154 | }\r |
147fd35c | 155 | \r |
22292ed3 JY |
156 | /**\r |
157 | Return current paging context.\r | |
158 | \r | |
159 | @param[in,out] PagingContext The paging context.\r | |
160 | **/\r | |
161 | VOID\r | |
162 | GetCurrentPagingContext (\r | |
163 | IN OUT PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext\r | |
164 | )\r | |
165 | {\r | |
d106cf71 JW |
166 | UINT32 RegEax;\r |
167 | CPUID_EXTENDED_CPU_SIG_EDX RegEdx;\r | |
168 | MSR_IA32_EFER_REGISTER MsrEfer;\r | |
22292ed3 | 169 | \r |
2a1408d1 JW |
170 | //\r |
171 | // Don't retrieve current paging context from processor if in SMM mode.\r | |
172 | //\r | |
173 | if (!IsInSmm ()) {\r | |
174 | ZeroMem (&mPagingContext, sizeof(mPagingContext));\r | |
175 | if (sizeof(UINTN) == sizeof(UINT64)) {\r | |
176 | mPagingContext.MachineType = IMAGE_FILE_MACHINE_X64;\r | |
177 | } else {\r | |
178 | mPagingContext.MachineType = IMAGE_FILE_MACHINE_I386;\r | |
179 | }\r | |
d106cf71 | 180 | if ((AsmReadCr0 () & CR0_PG) != 0) {\r |
2a1408d1 JW |
181 | mPagingContext.ContextData.X64.PageTableBase = (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);\r |
182 | } else {\r | |
183 | mPagingContext.ContextData.X64.PageTableBase = 0;\r | |
184 | }\r | |
22292ed3 | 185 | \r |
d106cf71 | 186 | if ((AsmReadCr4 () & CR4_PSE) != 0) {\r |
2a1408d1 JW |
187 | mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE;\r |
188 | }\r | |
d106cf71 | 189 | if ((AsmReadCr4 () & CR4_PAE) != 0) {\r |
2a1408d1 JW |
190 | mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE;\r |
191 | }\r | |
d106cf71 | 192 | if ((AsmReadCr0 () & CR0_WP) != 0) {\r |
2a1408d1 JW |
193 | mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE;\r |
194 | }\r | |
22292ed3 | 195 | \r |
d106cf71 JW |
196 | AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r |
197 | if (RegEax >= CPUID_EXTENDED_CPU_SIG) {\r | |
198 | AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx.Uint32);\r | |
199 | \r | |
200 | if (RegEdx.Bits.NX != 0) {\r | |
2a1408d1 | 201 | // XD supported\r |
d106cf71 JW |
202 | MsrEfer.Uint64 = AsmReadMsr64(MSR_CORE_IA32_EFER);\r |
203 | if (MsrEfer.Bits.NXE != 0) {\r | |
2a1408d1 JW |
204 | // XD activated\r |
205 | mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;\r | |
206 | }\r | |
207 | }\r | |
d106cf71 JW |
208 | \r |
209 | if (RegEdx.Bits.Page1GB != 0) {\r | |
2a1408d1 | 210 | mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAGE_1G_SUPPORT;\r |
22292ed3 | 211 | }\r |
22292ed3 JY |
212 | }\r |
213 | }\r | |
2a1408d1 JW |
214 | \r |
215 | //\r | |
216 | // This can avoid getting SMM paging context if in SMM mode. We cannot assume\r | |
217 | // SMM mode shares the same paging context as DXE.\r | |
218 | //\r | |
219 | CopyMem (PagingContext, &mPagingContext, sizeof (mPagingContext));\r | |
22292ed3 JY |
220 | }\r |
221 | \r | |
222 | /**\r | |
223 | Return length according to page attributes.\r | |
224 | \r | |
225 | @param[in] PageAttributes The page attribute of the page entry.\r | |
226 | \r | |
227 | @return The length of page entry.\r | |
228 | **/\r | |
229 | UINTN\r | |
230 | PageAttributeToLength (\r | |
231 | IN PAGE_ATTRIBUTE PageAttribute\r | |
232 | )\r | |
233 | {\r | |
234 | UINTN Index;\r | |
235 | for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {\r | |
236 | if (PageAttribute == mPageAttributeTable[Index].Attribute) {\r | |
237 | return (UINTN)mPageAttributeTable[Index].Length;\r | |
238 | }\r | |
239 | }\r | |
240 | return 0;\r | |
241 | }\r | |
242 | \r | |
243 | /**\r | |
244 | Return address mask according to page attributes.\r | |
245 | \r | |
246 | @param[in] PageAttributes The page attribute of the page entry.\r | |
247 | \r | |
248 | @return The address mask of page entry.\r | |
249 | **/\r | |
250 | UINTN\r | |
251 | PageAttributeToMask (\r | |
252 | IN PAGE_ATTRIBUTE PageAttribute\r | |
253 | )\r | |
254 | {\r | |
255 | UINTN Index;\r | |
256 | for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {\r | |
257 | if (PageAttribute == mPageAttributeTable[Index].Attribute) {\r | |
258 | return (UINTN)mPageAttributeTable[Index].AddressMask;\r | |
259 | }\r | |
260 | }\r | |
261 | return 0;\r | |
262 | }\r | |
263 | \r | |
264 | /**\r | |
265 | Return page table entry to match the address.\r | |
266 | \r | |
267 | @param[in] PagingContext The paging context.\r | |
268 | @param[in] Address The address to be checked.\r | |
269 | @param[out] PageAttributes The page attribute of the page entry.\r | |
270 | \r | |
271 | @return The page entry.\r | |
272 | **/\r | |
273 | VOID *\r | |
274 | GetPageTableEntry (\r | |
275 | IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext,\r | |
276 | IN PHYSICAL_ADDRESS Address,\r | |
277 | OUT PAGE_ATTRIBUTE *PageAttribute\r | |
278 | )\r | |
279 | {\r | |
280 | UINTN Index1;\r | |
281 | UINTN Index2;\r | |
282 | UINTN Index3;\r | |
283 | UINTN Index4;\r | |
284 | UINT64 *L1PageTable;\r | |
285 | UINT64 *L2PageTable;\r | |
286 | UINT64 *L3PageTable;\r | |
287 | UINT64 *L4PageTable;\r | |
627dcba3 | 288 | UINT64 AddressEncMask;\r |
22292ed3 JY |
289 | \r |
290 | ASSERT (PagingContext != NULL);\r | |
291 | \r | |
292 | Index4 = ((UINTN)RShiftU64 (Address, 39)) & PAGING_PAE_INDEX_MASK;\r | |
293 | Index3 = ((UINTN)Address >> 30) & PAGING_PAE_INDEX_MASK;\r | |
294 | Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK;\r | |
295 | Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK;\r | |
296 | \r | |
627dcba3 LD |
297 | // Make sure AddressEncMask is contained to smallest supported address field.\r |
298 | //\r | |
299 | AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r | |
300 | \r | |
22292ed3 JY |
301 | if (PagingContext->MachineType == IMAGE_FILE_MACHINE_X64) {\r |
302 | L4PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTableBase;\r | |
303 | if (L4PageTable[Index4] == 0) {\r | |
304 | *PageAttribute = PageNone;\r | |
305 | return NULL;\r | |
306 | }\r | |
307 | \r | |
627dcba3 | 308 | L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r |
22292ed3 JY |
309 | } else {\r |
310 | ASSERT((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0);\r | |
311 | L3PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.Ia32.PageTableBase;\r | |
312 | }\r | |
313 | if (L3PageTable[Index3] == 0) {\r | |
314 | *PageAttribute = PageNone;\r | |
315 | return NULL;\r | |
316 | }\r | |
317 | if ((L3PageTable[Index3] & IA32_PG_PS) != 0) {\r | |
318 | // 1G\r | |
319 | *PageAttribute = Page1G;\r | |
320 | return &L3PageTable[Index3];\r | |
321 | }\r | |
322 | \r | |
627dcba3 | 323 | L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r |
22292ed3 JY |
324 | if (L2PageTable[Index2] == 0) {\r |
325 | *PageAttribute = PageNone;\r | |
326 | return NULL;\r | |
327 | }\r | |
328 | if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {\r | |
329 | // 2M\r | |
330 | *PageAttribute = Page2M;\r | |
331 | return &L2PageTable[Index2];\r | |
332 | }\r | |
333 | \r | |
334 | // 4k\r | |
627dcba3 | 335 | L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r |
22292ed3 JY |
336 | if ((L1PageTable[Index1] == 0) && (Address != 0)) {\r |
337 | *PageAttribute = PageNone;\r | |
338 | return NULL;\r | |
339 | }\r | |
340 | *PageAttribute = Page4K;\r | |
341 | return &L1PageTable[Index1];\r | |
342 | }\r | |
343 | \r | |
344 | /**\r | |
345 | Return memory attributes of page entry.\r | |
346 | \r | |
347 | @param[in] PageEntry The page entry.\r | |
348 | \r | |
349 | @return Memory attributes of page entry.\r | |
350 | **/\r | |
351 | UINT64\r | |
352 | GetAttributesFromPageEntry (\r | |
353 | IN UINT64 *PageEntry\r | |
354 | )\r | |
355 | {\r | |
356 | UINT64 Attributes;\r | |
357 | Attributes = 0;\r | |
358 | if ((*PageEntry & IA32_PG_P) == 0) {\r | |
359 | Attributes |= EFI_MEMORY_RP;\r | |
360 | }\r | |
361 | if ((*PageEntry & IA32_PG_RW) == 0) {\r | |
362 | Attributes |= EFI_MEMORY_RO;\r | |
363 | }\r | |
364 | if ((*PageEntry & IA32_PG_NX) != 0) {\r | |
365 | Attributes |= EFI_MEMORY_XP;\r | |
366 | }\r | |
367 | return Attributes;\r | |
368 | }\r | |
369 | \r | |
370 | /**\r | |
371 | Modify memory attributes of page entry.\r | |
372 | \r | |
373 | @param[in] PagingContext The paging context.\r | |
374 | @param[in] PageEntry The page entry.\r | |
375 | @param[in] Attributes The bit mask of attributes to modify for the memory region.\r | |
376 | @param[in] PageAction The page action.\r | |
377 | @param[out] IsModified TRUE means page table modified. FALSE means page table not modified.\r | |
378 | **/\r | |
379 | VOID\r | |
380 | ConvertPageEntryAttribute (\r | |
381 | IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext,\r | |
382 | IN UINT64 *PageEntry,\r | |
383 | IN UINT64 Attributes,\r | |
384 | IN PAGE_ACTION PageAction,\r | |
385 | OUT BOOLEAN *IsModified\r | |
386 | )\r | |
387 | {\r | |
388 | UINT64 CurrentPageEntry;\r | |
389 | UINT64 NewPageEntry;\r | |
390 | \r | |
391 | CurrentPageEntry = *PageEntry;\r | |
392 | NewPageEntry = CurrentPageEntry;\r | |
393 | if ((Attributes & EFI_MEMORY_RP) != 0) {\r | |
394 | switch (PageAction) {\r | |
395 | case PageActionAssign:\r | |
396 | case PageActionSet:\r | |
397 | NewPageEntry &= ~(UINT64)IA32_PG_P;\r | |
398 | break;\r | |
399 | case PageActionClear:\r | |
400 | NewPageEntry |= IA32_PG_P;\r | |
401 | break;\r | |
402 | }\r | |
403 | } else {\r | |
404 | switch (PageAction) {\r | |
405 | case PageActionAssign:\r | |
406 | NewPageEntry |= IA32_PG_P;\r | |
407 | break;\r | |
408 | case PageActionSet:\r | |
409 | case PageActionClear:\r | |
410 | break;\r | |
411 | }\r | |
412 | }\r | |
413 | if ((Attributes & EFI_MEMORY_RO) != 0) {\r | |
414 | switch (PageAction) {\r | |
415 | case PageActionAssign:\r | |
416 | case PageActionSet:\r | |
417 | NewPageEntry &= ~(UINT64)IA32_PG_RW;\r | |
418 | break;\r | |
419 | case PageActionClear:\r | |
420 | NewPageEntry |= IA32_PG_RW;\r | |
421 | break;\r | |
422 | }\r | |
423 | } else {\r | |
424 | switch (PageAction) {\r | |
425 | case PageActionAssign:\r | |
426 | NewPageEntry |= IA32_PG_RW;\r | |
427 | break;\r | |
428 | case PageActionSet:\r | |
429 | case PageActionClear:\r | |
430 | break;\r | |
431 | }\r | |
432 | }\r | |
433 | if ((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED) != 0) {\r | |
434 | if ((Attributes & EFI_MEMORY_XP) != 0) {\r | |
435 | switch (PageAction) {\r | |
436 | case PageActionAssign:\r | |
437 | case PageActionSet:\r | |
438 | NewPageEntry |= IA32_PG_NX;\r | |
439 | break;\r | |
440 | case PageActionClear:\r | |
441 | NewPageEntry &= ~IA32_PG_NX;\r | |
442 | break;\r | |
443 | }\r | |
444 | } else {\r | |
445 | switch (PageAction) {\r | |
446 | case PageActionAssign:\r | |
447 | NewPageEntry &= ~IA32_PG_NX;\r | |
448 | break;\r | |
449 | case PageActionSet:\r | |
450 | case PageActionClear:\r | |
451 | break;\r | |
452 | }\r | |
453 | }\r | |
454 | }\r | |
455 | *PageEntry = NewPageEntry;\r | |
456 | if (CurrentPageEntry != NewPageEntry) {\r | |
457 | *IsModified = TRUE;\r | |
827330cc JW |
458 | DEBUG ((DEBUG_VERBOSE, "ConvertPageEntryAttribute 0x%lx", CurrentPageEntry));\r |
459 | DEBUG ((DEBUG_VERBOSE, "->0x%lx\n", NewPageEntry));\r | |
22292ed3 JY |
460 | } else {\r |
461 | *IsModified = FALSE;\r | |
462 | }\r | |
463 | }\r | |
464 | \r | |
465 | /**\r | |
466 | This function returns if there is need to split page entry.\r | |
467 | \r | |
468 | @param[in] BaseAddress The base address to be checked.\r | |
469 | @param[in] Length The length to be checked.\r | |
470 | @param[in] PageEntry The page entry to be checked.\r | |
471 | @param[in] PageAttribute The page attribute of the page entry.\r | |
472 | \r | |
473 | @retval SplitAttributes on if there is need to split page entry.\r | |
474 | **/\r | |
475 | PAGE_ATTRIBUTE\r | |
476 | NeedSplitPage (\r | |
477 | IN PHYSICAL_ADDRESS BaseAddress,\r | |
478 | IN UINT64 Length,\r | |
479 | IN UINT64 *PageEntry,\r | |
480 | IN PAGE_ATTRIBUTE PageAttribute\r | |
481 | )\r | |
482 | {\r | |
483 | UINT64 PageEntryLength;\r | |
484 | \r | |
485 | PageEntryLength = PageAttributeToLength (PageAttribute);\r | |
486 | \r | |
487 | if (((BaseAddress & (PageEntryLength - 1)) == 0) && (Length >= PageEntryLength)) {\r | |
488 | return PageNone;\r | |
489 | }\r | |
490 | \r | |
491 | if (((BaseAddress & PAGING_2M_MASK) != 0) || (Length < SIZE_2MB)) {\r | |
492 | return Page4K;\r | |
493 | }\r | |
494 | \r | |
495 | return Page2M;\r | |
496 | }\r | |
497 | \r | |
498 | /**\r | |
499 | This function splits one page entry to small page entries.\r | |
500 | \r | |
501 | @param[in] PageEntry The page entry to be splitted.\r | |
502 | @param[in] PageAttribute The page attribute of the page entry.\r | |
503 | @param[in] SplitAttribute How to split the page entry.\r | |
504 | @param[in] AllocatePagesFunc If page split is needed, this function is used to allocate more pages.\r | |
505 | \r | |
506 | @retval RETURN_SUCCESS The page entry is splitted.\r | |
507 | @retval RETURN_UNSUPPORTED The page entry does not support to be splitted.\r | |
508 | @retval RETURN_OUT_OF_RESOURCES No resource to split page entry.\r | |
509 | **/\r | |
510 | RETURN_STATUS\r | |
511 | SplitPage (\r | |
512 | IN UINT64 *PageEntry,\r | |
513 | IN PAGE_ATTRIBUTE PageAttribute,\r | |
514 | IN PAGE_ATTRIBUTE SplitAttribute,\r | |
515 | IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc\r | |
516 | )\r | |
517 | {\r | |
518 | UINT64 BaseAddress;\r | |
519 | UINT64 *NewPageEntry;\r | |
520 | UINTN Index;\r | |
627dcba3 | 521 | UINT64 AddressEncMask;\r |
22292ed3 JY |
522 | \r |
523 | ASSERT (PageAttribute == Page2M || PageAttribute == Page1G);\r | |
524 | \r | |
525 | ASSERT (AllocatePagesFunc != NULL);\r | |
526 | \r | |
627dcba3 LD |
527 | // Make sure AddressEncMask is contained to smallest supported address field.\r |
528 | //\r | |
529 | AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r | |
530 | \r | |
22292ed3 JY |
531 | if (PageAttribute == Page2M) {\r |
532 | //\r | |
533 | // Split 2M to 4K\r | |
534 | //\r | |
535 | ASSERT (SplitAttribute == Page4K);\r | |
536 | if (SplitAttribute == Page4K) {\r | |
537 | NewPageEntry = AllocatePagesFunc (1);\r | |
7c7c8190 | 538 | DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry));\r |
22292ed3 JY |
539 | if (NewPageEntry == NULL) {\r |
540 | return RETURN_OUT_OF_RESOURCES;\r | |
541 | }\r | |
627dcba3 | 542 | BaseAddress = *PageEntry & ~AddressEncMask & PAGING_2M_ADDRESS_MASK_64;\r |
22292ed3 | 543 | for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {\r |
627dcba3 | 544 | NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);\r |
22292ed3 | 545 | }\r |
fbe2c4b9 | 546 | (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS);\r |
22292ed3 JY |
547 | return RETURN_SUCCESS;\r |
548 | } else {\r | |
549 | return RETURN_UNSUPPORTED;\r | |
550 | }\r | |
551 | } else if (PageAttribute == Page1G) {\r | |
552 | //\r | |
553 | // Split 1G to 2M\r | |
554 | // No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table.\r | |
555 | //\r | |
556 | ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K);\r | |
557 | if ((SplitAttribute == Page2M || SplitAttribute == Page4K)) {\r | |
558 | NewPageEntry = AllocatePagesFunc (1);\r | |
7c7c8190 | 559 | DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry));\r |
22292ed3 JY |
560 | if (NewPageEntry == NULL) {\r |
561 | return RETURN_OUT_OF_RESOURCES;\r | |
562 | }\r | |
627dcba3 | 563 | BaseAddress = *PageEntry & ~AddressEncMask & PAGING_1G_ADDRESS_MASK_64;\r |
22292ed3 | 564 | for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {\r |
627dcba3 | 565 | NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | AddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS);\r |
22292ed3 | 566 | }\r |
fbe2c4b9 | 567 | (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS);\r |
22292ed3 JY |
568 | return RETURN_SUCCESS;\r |
569 | } else {\r | |
570 | return RETURN_UNSUPPORTED;\r | |
571 | }\r | |
572 | } else {\r | |
573 | return RETURN_UNSUPPORTED;\r | |
574 | }\r | |
575 | }\r | |
576 | \r | |
147fd35c JW |
577 | /**\r |
578 | Check the WP status in CR0 register. This bit is used to lock or unlock write\r | |
579 | access to pages marked as read-only.\r | |
580 | \r | |
581 | @retval TRUE Write protection is enabled.\r | |
582 | @retval FALSE Write protection is disabled.\r | |
583 | **/\r | |
584 | BOOLEAN\r | |
585 | IsReadOnlyPageWriteProtected (\r | |
586 | VOID\r | |
587 | )\r | |
588 | {\r | |
2a1408d1 JW |
589 | //\r |
590 | // To avoid unforseen consequences, don't touch paging settings in SMM mode\r | |
591 | // in this driver.\r | |
592 | //\r | |
593 | if (!IsInSmm ()) {\r | |
d106cf71 | 594 | return ((AsmReadCr0 () & CR0_WP) != 0);\r |
2a1408d1 JW |
595 | }\r |
596 | return FALSE;\r | |
147fd35c JW |
597 | }\r |
598 | \r | |
147fd35c JW |
599 | /**\r |
600 | Disable Write Protect on pages marked as read-only.\r | |
601 | **/\r | |
602 | VOID\r | |
603 | DisableReadOnlyPageWriteProtect (\r | |
604 | VOID\r | |
605 | )\r | |
606 | {\r | |
2a1408d1 JW |
607 | //\r |
608 | // To avoid unforseen consequences, don't touch paging settings in SMM mode\r | |
609 | // in this driver.\r | |
610 | //\r | |
611 | if (!IsInSmm ()) {\r | |
d106cf71 | 612 | AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);\r |
2a1408d1 | 613 | }\r |
147fd35c JW |
614 | }\r |
615 | \r | |
616 | /**\r | |
617 | Enable Write Protect on pages marked as read-only.\r | |
618 | **/\r | |
619 | VOID\r | |
620 | EnableReadOnlyPageWriteProtect (\r | |
621 | VOID\r | |
622 | )\r | |
623 | {\r | |
2a1408d1 JW |
624 | //\r |
625 | // To avoid unforseen consequences, don't touch paging settings in SMM mode\r | |
626 | // in this driver.\r | |
627 | //\r | |
628 | if (!IsInSmm ()) {\r | |
d106cf71 | 629 | AsmWriteCr0 (AsmReadCr0 () | CR0_WP);\r |
2a1408d1 | 630 | }\r |
147fd35c JW |
631 | }\r |
632 | \r | |
22292ed3 JY |
633 | /**\r |
634 | This function modifies the page attributes for the memory region specified by BaseAddress and\r | |
635 | Length from their current attributes to the attributes specified by Attributes.\r | |
636 | \r | |
637 | Caller should make sure BaseAddress and Length is at page boundary.\r | |
638 | \r | |
639 | @param[in] PagingContext The paging context. NULL means get page table from current CPU context.\r | |
640 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
641 | @param[in] Length The size in bytes of the memory region.\r | |
642 | @param[in] Attributes The bit mask of attributes to modify for the memory region.\r | |
643 | @param[in] PageAction The page action.\r | |
644 | @param[in] AllocatePagesFunc If page split is needed, this function is used to allocate more pages.\r | |
645 | NULL mean page split is unsupported.\r | |
646 | @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.\r | |
647 | @param[out] IsModified TRUE means page table modified. FALSE means page table not modified.\r | |
648 | \r | |
649 | @retval RETURN_SUCCESS The attributes were modified for the memory region.\r | |
650 | @retval RETURN_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
651 | BaseAddress and Length cannot be modified.\r | |
652 | @retval RETURN_INVALID_PARAMETER Length is zero.\r | |
653 | Attributes specified an illegal combination of attributes that\r | |
654 | cannot be set together.\r | |
655 | @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
656 | the memory resource range.\r | |
657 | @retval RETURN_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
658 | resource range specified by BaseAddress and Length.\r | |
659 | The bit mask of attributes is not support for the memory resource\r | |
660 | range specified by BaseAddress and Length.\r | |
661 | **/\r | |
662 | RETURN_STATUS\r | |
663 | ConvertMemoryPageAttributes (\r | |
664 | IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL,\r | |
665 | IN PHYSICAL_ADDRESS BaseAddress,\r | |
666 | IN UINT64 Length,\r | |
667 | IN UINT64 Attributes,\r | |
668 | IN PAGE_ACTION PageAction,\r | |
669 | IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL,\r | |
670 | OUT BOOLEAN *IsSplitted, OPTIONAL\r | |
671 | OUT BOOLEAN *IsModified OPTIONAL\r | |
672 | )\r | |
673 | {\r | |
674 | PAGE_TABLE_LIB_PAGING_CONTEXT CurrentPagingContext;\r | |
675 | UINT64 *PageEntry;\r | |
676 | PAGE_ATTRIBUTE PageAttribute;\r | |
677 | UINTN PageEntryLength;\r | |
678 | PAGE_ATTRIBUTE SplitAttribute;\r | |
679 | RETURN_STATUS Status;\r | |
680 | BOOLEAN IsEntryModified;\r | |
147fd35c | 681 | BOOLEAN IsWpEnabled;\r |
22292ed3 JY |
682 | \r |
683 | if ((BaseAddress & (SIZE_4KB - 1)) != 0) {\r | |
684 | DEBUG ((DEBUG_ERROR, "BaseAddress(0x%lx) is not aligned!\n", BaseAddress));\r | |
685 | return EFI_UNSUPPORTED;\r | |
686 | }\r | |
687 | if ((Length & (SIZE_4KB - 1)) != 0) {\r | |
688 | DEBUG ((DEBUG_ERROR, "Length(0x%lx) is not aligned!\n", Length));\r | |
689 | return EFI_UNSUPPORTED;\r | |
690 | }\r | |
691 | if (Length == 0) {\r | |
692 | DEBUG ((DEBUG_ERROR, "Length is 0!\n"));\r | |
693 | return RETURN_INVALID_PARAMETER;\r | |
694 | }\r | |
695 | \r | |
696 | if ((Attributes & ~(EFI_MEMORY_RP | EFI_MEMORY_RO | EFI_MEMORY_XP)) != 0) {\r | |
697 | DEBUG ((DEBUG_ERROR, "Attributes(0x%lx) has unsupported bit\n", Attributes));\r | |
698 | return EFI_UNSUPPORTED;\r | |
699 | }\r | |
700 | \r | |
701 | if (PagingContext == NULL) {\r | |
702 | GetCurrentPagingContext (&CurrentPagingContext);\r | |
703 | } else {\r | |
704 | CopyMem (&CurrentPagingContext, PagingContext, sizeof(CurrentPagingContext));\r | |
705 | }\r | |
706 | switch(CurrentPagingContext.MachineType) {\r | |
707 | case IMAGE_FILE_MACHINE_I386:\r | |
708 | if (CurrentPagingContext.ContextData.Ia32.PageTableBase == 0) {\r | |
22292ed3 JY |
709 | if (Attributes == 0) {\r |
710 | return EFI_SUCCESS;\r | |
711 | } else {\r | |
c5719579 | 712 | DEBUG ((DEBUG_ERROR, "PageTable is 0!\n"));\r |
22292ed3 JY |
713 | return EFI_UNSUPPORTED;\r |
714 | }\r | |
715 | }\r | |
716 | if ((CurrentPagingContext.ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) == 0) {\r | |
717 | DEBUG ((DEBUG_ERROR, "Non-PAE Paging!\n"));\r | |
718 | return EFI_UNSUPPORTED;\r | |
719 | }\r | |
4f10654e JW |
720 | if ((BaseAddress + Length) > BASE_4GB) {\r |
721 | DEBUG ((DEBUG_ERROR, "Beyond 4GB memory in 32-bit mode!\n"));\r | |
722 | return EFI_UNSUPPORTED;\r | |
723 | }\r | |
22292ed3 JY |
724 | break;\r |
725 | case IMAGE_FILE_MACHINE_X64:\r | |
726 | ASSERT (CurrentPagingContext.ContextData.X64.PageTableBase != 0);\r | |
727 | break;\r | |
728 | default:\r | |
729 | ASSERT(FALSE);\r | |
730 | return EFI_UNSUPPORTED;\r | |
731 | break;\r | |
732 | }\r | |
733 | \r | |
734 | // DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes));\r | |
735 | \r | |
736 | if (IsSplitted != NULL) {\r | |
737 | *IsSplitted = FALSE;\r | |
738 | }\r | |
739 | if (IsModified != NULL) {\r | |
740 | *IsModified = FALSE;\r | |
741 | }\r | |
147fd35c JW |
742 | if (AllocatePagesFunc == NULL) {\r |
743 | AllocatePagesFunc = AllocatePageTableMemory;\r | |
744 | }\r | |
745 | \r | |
746 | //\r | |
747 | // Make sure that the page table is changeable.\r | |
748 | //\r | |
749 | IsWpEnabled = IsReadOnlyPageWriteProtected ();\r | |
750 | if (IsWpEnabled) {\r | |
751 | DisableReadOnlyPageWriteProtect ();\r | |
752 | }\r | |
22292ed3 JY |
753 | \r |
754 | //\r | |
755 | // Below logic is to check 2M/4K page to make sure we donot waist memory.\r | |
756 | //\r | |
147fd35c | 757 | Status = EFI_SUCCESS;\r |
22292ed3 JY |
758 | while (Length != 0) {\r |
759 | PageEntry = GetPageTableEntry (&CurrentPagingContext, BaseAddress, &PageAttribute);\r | |
760 | if (PageEntry == NULL) {\r | |
147fd35c JW |
761 | Status = RETURN_UNSUPPORTED;\r |
762 | goto Done;\r | |
22292ed3 JY |
763 | }\r |
764 | PageEntryLength = PageAttributeToLength (PageAttribute);\r | |
765 | SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute);\r | |
766 | if (SplitAttribute == PageNone) {\r | |
767 | ConvertPageEntryAttribute (&CurrentPagingContext, PageEntry, Attributes, PageAction, &IsEntryModified);\r | |
768 | if (IsEntryModified) {\r | |
769 | if (IsModified != NULL) {\r | |
770 | *IsModified = TRUE;\r | |
771 | }\r | |
772 | }\r | |
773 | //\r | |
774 | // Convert success, move to next\r | |
775 | //\r | |
776 | BaseAddress += PageEntryLength;\r | |
777 | Length -= PageEntryLength;\r | |
778 | } else {\r | |
779 | if (AllocatePagesFunc == NULL) {\r | |
147fd35c JW |
780 | Status = RETURN_UNSUPPORTED;\r |
781 | goto Done;\r | |
22292ed3 JY |
782 | }\r |
783 | Status = SplitPage (PageEntry, PageAttribute, SplitAttribute, AllocatePagesFunc);\r | |
784 | if (RETURN_ERROR (Status)) {\r | |
147fd35c JW |
785 | Status = RETURN_UNSUPPORTED;\r |
786 | goto Done;\r | |
22292ed3 JY |
787 | }\r |
788 | if (IsSplitted != NULL) {\r | |
789 | *IsSplitted = TRUE;\r | |
790 | }\r | |
791 | if (IsModified != NULL) {\r | |
792 | *IsModified = TRUE;\r | |
793 | }\r | |
794 | //\r | |
795 | // Just split current page\r | |
796 | // Convert success in next around\r | |
797 | //\r | |
798 | }\r | |
799 | }\r | |
800 | \r | |
147fd35c JW |
801 | Done:\r |
802 | //\r | |
803 | // Restore page table write protection, if any.\r | |
804 | //\r | |
805 | if (IsWpEnabled) {\r | |
806 | EnableReadOnlyPageWriteProtect ();\r | |
807 | }\r | |
808 | return Status;\r | |
22292ed3 JY |
809 | }\r |
810 | \r | |
811 | /**\r | |
812 | This function assigns the page attributes for the memory region specified by BaseAddress and\r | |
813 | Length from their current attributes to the attributes specified by Attributes.\r | |
814 | \r | |
815 | Caller should make sure BaseAddress and Length is at page boundary.\r | |
816 | \r | |
817 | Caller need guarentee the TPL <= TPL_NOTIFY, if there is split page request.\r | |
818 | \r | |
819 | @param[in] PagingContext The paging context. NULL means get page table from current CPU context.\r | |
820 | @param[in] BaseAddress The physical address that is the start address of a memory region.\r | |
821 | @param[in] Length The size in bytes of the memory region.\r | |
822 | @param[in] Attributes The bit mask of attributes to set for the memory region.\r | |
823 | @param[in] AllocatePagesFunc If page split is needed, this function is used to allocate more pages.\r | |
824 | NULL mean page split is unsupported.\r | |
825 | \r | |
826 | @retval RETURN_SUCCESS The attributes were cleared for the memory region.\r | |
827 | @retval RETURN_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
828 | BaseAddress and Length cannot be modified.\r | |
829 | @retval RETURN_INVALID_PARAMETER Length is zero.\r | |
830 | Attributes specified an illegal combination of attributes that\r | |
831 | cannot be set together.\r | |
832 | @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
833 | the memory resource range.\r | |
834 | @retval RETURN_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
835 | resource range specified by BaseAddress and Length.\r | |
836 | The bit mask of attributes is not support for the memory resource\r | |
837 | range specified by BaseAddress and Length.\r | |
838 | **/\r | |
839 | RETURN_STATUS\r | |
840 | EFIAPI\r | |
841 | AssignMemoryPageAttributes (\r | |
842 | IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL,\r | |
843 | IN PHYSICAL_ADDRESS BaseAddress,\r | |
844 | IN UINT64 Length,\r | |
845 | IN UINT64 Attributes,\r | |
846 | IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL\r | |
847 | )\r | |
848 | {\r | |
849 | RETURN_STATUS Status;\r | |
850 | BOOLEAN IsModified;\r | |
851 | BOOLEAN IsSplitted;\r | |
852 | \r | |
853 | // DEBUG((DEBUG_INFO, "AssignMemoryPageAttributes: 0x%lx - 0x%lx (0x%lx)\n", BaseAddress, Length, Attributes));\r | |
854 | Status = ConvertMemoryPageAttributes (PagingContext, BaseAddress, Length, Attributes, PageActionAssign, AllocatePagesFunc, &IsSplitted, &IsModified);\r | |
855 | if (!EFI_ERROR(Status)) {\r | |
856 | if ((PagingContext == NULL) && IsModified) {\r | |
857 | //\r | |
41a9c3fd JW |
858 | // Flush TLB as last step.\r |
859 | //\r | |
860 | // Note: Since APs will always init CR3 register in HLT loop mode or do\r | |
861 | // TLB flush in MWAIT loop mode, there's no need to flush TLB for them\r | |
862 | // here.\r | |
22292ed3 JY |
863 | //\r |
864 | CpuFlushTlb();\r | |
22292ed3 JY |
865 | }\r |
866 | }\r | |
867 | \r | |
868 | return Status;\r | |
869 | }\r | |
870 | \r | |
768bd967 JW |
871 | /**\r |
872 | Check if Execute Disable feature is enabled or not.\r | |
873 | **/\r | |
874 | BOOLEAN\r | |
875 | IsExecuteDisableEnabled (\r | |
876 | VOID\r | |
877 | )\r | |
878 | {\r | |
879 | MSR_CORE_IA32_EFER_REGISTER MsrEfer;\r | |
880 | \r | |
881 | MsrEfer.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r | |
882 | return (MsrEfer.Bits.NXE == 1);\r | |
883 | }\r | |
884 | \r | |
c1cab54c JW |
885 | /**\r |
886 | Update GCD memory space attributes according to current page table setup.\r | |
887 | **/\r | |
888 | VOID\r | |
889 | RefreshGcdMemoryAttributesFromPaging (\r | |
890 | VOID\r | |
891 | )\r | |
892 | {\r | |
893 | EFI_STATUS Status;\r | |
894 | UINTN NumberOfDescriptors;\r | |
895 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r | |
896 | PAGE_TABLE_LIB_PAGING_CONTEXT PagingContext;\r | |
897 | PAGE_ATTRIBUTE PageAttribute;\r | |
898 | UINT64 *PageEntry;\r | |
899 | UINT64 PageLength;\r | |
900 | UINT64 MemorySpaceLength;\r | |
901 | UINT64 Length;\r | |
902 | UINT64 BaseAddress;\r | |
903 | UINT64 PageStartAddress;\r | |
904 | UINT64 Attributes;\r | |
905 | UINT64 Capabilities;\r | |
768bd967 | 906 | UINT64 NewAttributes;\r |
c1cab54c JW |
907 | UINTN Index;\r |
908 | \r | |
909 | //\r | |
910 | // Assuming that memory space map returned is sorted already; otherwise sort\r | |
911 | // them in the order of lowest address to highest address.\r | |
912 | //\r | |
913 | Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r | |
914 | ASSERT_EFI_ERROR (Status);\r | |
915 | \r | |
916 | GetCurrentPagingContext (&PagingContext);\r | |
917 | \r | |
768bd967 JW |
918 | Attributes = 0;\r |
919 | NewAttributes = 0;\r | |
920 | BaseAddress = 0;\r | |
921 | PageLength = 0;\r | |
922 | \r | |
923 | if (IsExecuteDisableEnabled ()) {\r | |
924 | Capabilities = EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_XP;\r | |
925 | } else {\r | |
926 | Capabilities = EFI_MEMORY_RO | EFI_MEMORY_RP;\r | |
927 | }\r | |
96207191 | 928 | \r |
c1cab54c JW |
929 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r |
930 | if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r | |
931 | continue;\r | |
932 | }\r | |
933 | \r | |
768bd967 JW |
934 | //\r |
935 | // Sync the actual paging related capabilities back to GCD service first.\r | |
936 | // As a side effect (good one), this can also help to avoid unnecessary\r | |
937 | // memory map entries due to the different capabilities of the same type\r | |
938 | // memory, such as multiple RT_CODE and RT_DATA entries in memory map,\r | |
939 | // which could cause boot failure of some old Linux distro (before v4.3).\r | |
940 | //\r | |
941 | Status = gDS->SetMemorySpaceCapabilities (\r | |
942 | MemorySpaceMap[Index].BaseAddress,\r | |
943 | MemorySpaceMap[Index].Length,\r | |
944 | MemorySpaceMap[Index].Capabilities | Capabilities\r | |
945 | );\r | |
946 | if (EFI_ERROR (Status)) {\r | |
947 | //\r | |
948 | // If we cannot udpate the capabilities, we cannot update its\r | |
949 | // attributes either. So just simply skip current block of memory.\r | |
950 | //\r | |
951 | DEBUG ((\r | |
952 | DEBUG_WARN,\r | |
953 | "Failed to update capability: [%lu] %016lx - %016lx (%016lx -> %016lx)\r\n",\r | |
954 | (UINT64)Index, MemorySpaceMap[Index].BaseAddress,\r | |
955 | MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - 1,\r | |
956 | MemorySpaceMap[Index].Capabilities,\r | |
957 | MemorySpaceMap[Index].Capabilities | Capabilities\r | |
958 | ));\r | |
959 | continue;\r | |
960 | }\r | |
961 | \r | |
c1cab54c JW |
962 | if (MemorySpaceMap[Index].BaseAddress >= (BaseAddress + PageLength)) {\r |
963 | //\r | |
964 | // Current memory space starts at a new page. Resetting PageLength will\r | |
965 | // trigger a retrieval of page attributes at new address.\r | |
966 | //\r | |
967 | PageLength = 0;\r | |
968 | } else {\r | |
969 | //\r | |
970 | // In case current memory space is not adjacent to last one\r | |
971 | //\r | |
972 | PageLength -= (MemorySpaceMap[Index].BaseAddress - BaseAddress);\r | |
973 | }\r | |
974 | \r | |
768bd967 JW |
975 | //\r |
976 | // Sync actual page attributes to GCD\r | |
977 | //\r | |
c1cab54c JW |
978 | BaseAddress = MemorySpaceMap[Index].BaseAddress;\r |
979 | MemorySpaceLength = MemorySpaceMap[Index].Length;\r | |
980 | while (MemorySpaceLength > 0) {\r | |
981 | if (PageLength == 0) {\r | |
982 | PageEntry = GetPageTableEntry (&PagingContext, BaseAddress, &PageAttribute);\r | |
983 | if (PageEntry == NULL) {\r | |
984 | break;\r | |
985 | }\r | |
986 | \r | |
987 | //\r | |
988 | // Note current memory space might start in the middle of a page\r | |
989 | //\r | |
990 | PageStartAddress = (*PageEntry) & (UINT64)PageAttributeToMask(PageAttribute);\r | |
991 | PageLength = PageAttributeToLength (PageAttribute) - (BaseAddress - PageStartAddress);\r | |
992 | Attributes = GetAttributesFromPageEntry (PageEntry);\r | |
c1cab54c JW |
993 | }\r |
994 | \r | |
995 | Length = MIN (PageLength, MemorySpaceLength);\r | |
768bd967 JW |
996 | if (Attributes != (MemorySpaceMap[Index].Attributes &\r |
997 | EFI_MEMORY_PAGETYPE_MASK)) {\r | |
998 | NewAttributes = (MemorySpaceMap[Index].Attributes &\r | |
999 | ~EFI_MEMORY_PAGETYPE_MASK) | Attributes;\r | |
1000 | Status = gDS->SetMemorySpaceAttributes (\r | |
1001 | BaseAddress,\r | |
1002 | Length,\r | |
1003 | NewAttributes\r | |
1004 | );\r | |
1005 | ASSERT_EFI_ERROR (Status);\r | |
1006 | DEBUG ((\r | |
fbe2c4b9 | 1007 | DEBUG_VERBOSE,\r |
768bd967 JW |
1008 | "Updated memory space attribute: [%lu] %016lx - %016lx (%016lx -> %016lx)\r\n",\r |
1009 | (UINT64)Index, BaseAddress, BaseAddress + Length - 1,\r | |
1010 | MemorySpaceMap[Index].Attributes,\r | |
1011 | NewAttributes\r | |
1012 | ));\r | |
c1cab54c JW |
1013 | }\r |
1014 | \r | |
1015 | PageLength -= Length;\r | |
1016 | MemorySpaceLength -= Length;\r | |
1017 | BaseAddress += Length;\r | |
1018 | }\r | |
1019 | }\r | |
1020 | \r | |
1021 | FreePool (MemorySpaceMap);\r | |
1022 | }\r | |
1023 | \r | |
147fd35c JW |
1024 | /**\r |
1025 | Initialize a buffer pool for page table use only.\r | |
1026 | \r | |
1027 | To reduce the potential split operation on page table, the pages reserved for\r | |
1028 | page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGES and\r | |
1029 | at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always\r | |
1030 | initialized with number of pages greater than or equal to the given PoolPages.\r | |
1031 | \r | |
1032 | Once the pages in the pool are used up, this method should be called again to\r | |
1033 | reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. Usually this won't happen\r | |
1034 | often in practice.\r | |
1035 | \r | |
1036 | @param[in] PoolPages The least page number of the pool to be created.\r | |
1037 | \r | |
1038 | @retval TRUE The pool is initialized successfully.\r | |
1039 | @retval FALSE The memory is out of resource.\r | |
1040 | **/\r | |
1041 | BOOLEAN\r | |
1042 | InitializePageTablePool (\r | |
1043 | IN UINTN PoolPages\r | |
1044 | )\r | |
1045 | {\r | |
1046 | VOID *Buffer;\r | |
1047 | BOOLEAN IsModified;\r | |
1048 | \r | |
1049 | //\r | |
1050 | // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for\r | |
1051 | // header.\r | |
1052 | //\r | |
1053 | PoolPages += 1; // Add one page for header.\r | |
1054 | PoolPages = ((PoolPages - 1) / PAGE_TABLE_POOL_UNIT_PAGES + 1) *\r | |
1055 | PAGE_TABLE_POOL_UNIT_PAGES;\r | |
1056 | Buffer = AllocateAlignedPages (PoolPages, PAGE_TABLE_POOL_ALIGNMENT);\r | |
1057 | if (Buffer == NULL) {\r | |
1058 | DEBUG ((DEBUG_ERROR, "ERROR: Out of aligned pages\r\n"));\r | |
1059 | return FALSE;\r | |
1060 | }\r | |
1061 | \r | |
1062 | //\r | |
1063 | // Link all pools into a list for easier track later.\r | |
1064 | //\r | |
1065 | if (mPageTablePool == NULL) {\r | |
1066 | mPageTablePool = Buffer;\r | |
1067 | mPageTablePool->NextPool = mPageTablePool;\r | |
1068 | } else {\r | |
1069 | ((PAGE_TABLE_POOL *)Buffer)->NextPool = mPageTablePool->NextPool;\r | |
1070 | mPageTablePool->NextPool = Buffer;\r | |
1071 | mPageTablePool = Buffer;\r | |
1072 | }\r | |
1073 | \r | |
1074 | //\r | |
1075 | // Reserve one page for pool header.\r | |
1076 | //\r | |
1077 | mPageTablePool->FreePages = PoolPages - 1;\r | |
1078 | mPageTablePool->Offset = EFI_PAGES_TO_SIZE (1);\r | |
1079 | \r | |
1080 | //\r | |
1081 | // Mark the whole pool pages as read-only.\r | |
1082 | //\r | |
1083 | ConvertMemoryPageAttributes (\r | |
1084 | NULL,\r | |
1085 | (PHYSICAL_ADDRESS)(UINTN)Buffer,\r | |
1086 | EFI_PAGES_TO_SIZE (PoolPages),\r | |
1087 | EFI_MEMORY_RO,\r | |
1088 | PageActionSet,\r | |
1089 | AllocatePageTableMemory,\r | |
1090 | NULL,\r | |
1091 | &IsModified\r | |
1092 | );\r | |
1093 | ASSERT (IsModified == TRUE);\r | |
1094 | \r | |
1095 | return TRUE;\r | |
1096 | }\r | |
1097 | \r | |
1098 | /**\r | |
1099 | This API provides a way to allocate memory for page table.\r | |
1100 | \r | |
1101 | This API can be called more than once to allocate memory for page tables.\r | |
1102 | \r | |
1103 | Allocates the number of 4KB pages and returns a pointer to the allocated\r | |
1104 | buffer. The buffer returned is aligned on a 4KB boundary.\r | |
1105 | \r | |
1106 | If Pages is 0, then NULL is returned.\r | |
1107 | If there is not enough memory remaining to satisfy the request, then NULL is\r | |
1108 | returned.\r | |
1109 | \r | |
1110 | @param Pages The number of 4 KB pages to allocate.\r | |
1111 | \r | |
1112 | @return A pointer to the allocated buffer or NULL if allocation fails.\r | |
1113 | \r | |
1114 | **/\r | |
1115 | VOID *\r | |
1116 | EFIAPI\r | |
1117 | AllocatePageTableMemory (\r | |
1118 | IN UINTN Pages\r | |
1119 | )\r | |
1120 | {\r | |
1121 | VOID *Buffer;\r | |
1122 | \r | |
1123 | if (Pages == 0) {\r | |
1124 | return NULL;\r | |
1125 | }\r | |
1126 | \r | |
1127 | //\r | |
1128 | // Renew the pool if necessary.\r | |
1129 | //\r | |
1130 | if (mPageTablePool == NULL ||\r | |
1131 | Pages > mPageTablePool->FreePages) {\r | |
1132 | if (!InitializePageTablePool (Pages)) {\r | |
1133 | return NULL;\r | |
1134 | }\r | |
1135 | }\r | |
1136 | \r | |
1137 | Buffer = (UINT8 *)mPageTablePool + mPageTablePool->Offset;\r | |
1138 | \r | |
1139 | mPageTablePool->Offset += EFI_PAGES_TO_SIZE (Pages);\r | |
1140 | mPageTablePool->FreePages -= Pages;\r | |
1141 | \r | |
1142 | return Buffer;\r | |
1143 | }\r | |
1144 | \r | |
dcc02621 JW |
1145 | /**\r |
1146 | Special handler for #DB exception, which will restore the page attributes\r | |
1147 | (not-present). It should work with #PF handler which will set pages to\r | |
1148 | 'present'.\r | |
1149 | \r | |
1150 | @param ExceptionType Exception type.\r | |
1151 | @param SystemContext Pointer to EFI_SYSTEM_CONTEXT.\r | |
1152 | \r | |
1153 | **/\r | |
1154 | VOID\r | |
1155 | EFIAPI\r | |
1156 | DebugExceptionHandler (\r | |
1157 | IN EFI_EXCEPTION_TYPE ExceptionType,\r | |
1158 | IN EFI_SYSTEM_CONTEXT SystemContext\r | |
1159 | )\r | |
1160 | {\r | |
1161 | UINTN CpuIndex;\r | |
1162 | UINTN PFEntry;\r | |
1163 | BOOLEAN IsWpEnabled;\r | |
1164 | \r | |
1165 | MpInitLibWhoAmI (&CpuIndex);\r | |
1166 | \r | |
1167 | //\r | |
1168 | // Clear last PF entries\r | |
1169 | //\r | |
1170 | IsWpEnabled = IsReadOnlyPageWriteProtected ();\r | |
1171 | if (IsWpEnabled) {\r | |
1172 | DisableReadOnlyPageWriteProtect ();\r | |
1173 | }\r | |
1174 | \r | |
1175 | for (PFEntry = 0; PFEntry < mPFEntryCount[CpuIndex]; PFEntry++) {\r | |
1176 | if (mLastPFEntryPointer[CpuIndex][PFEntry] != NULL) {\r | |
8e2018f9 | 1177 | *mLastPFEntryPointer[CpuIndex][PFEntry] &= ~(UINT64)IA32_PG_P;\r |
dcc02621 JW |
1178 | }\r |
1179 | }\r | |
1180 | \r | |
1181 | if (IsWpEnabled) {\r | |
1182 | EnableReadOnlyPageWriteProtect ();\r | |
1183 | }\r | |
1184 | \r | |
1185 | //\r | |
1186 | // Reset page fault exception count for next page fault.\r | |
1187 | //\r | |
1188 | mPFEntryCount[CpuIndex] = 0;\r | |
1189 | \r | |
1190 | //\r | |
1191 | // Flush TLB\r | |
1192 | //\r | |
1193 | CpuFlushTlb ();\r | |
1194 | \r | |
1195 | //\r | |
1196 | // Clear TF in EFLAGS\r | |
1197 | //\r | |
1198 | if (mPagingContext.MachineType == IMAGE_FILE_MACHINE_I386) {\r | |
1199 | SystemContext.SystemContextIa32->Eflags &= (UINT32)~BIT8;\r | |
1200 | } else {\r | |
1201 | SystemContext.SystemContextX64->Rflags &= (UINT64)~BIT8;\r | |
1202 | }\r | |
1203 | }\r | |
1204 | \r | |
1205 | /**\r | |
1206 | Special handler for #PF exception, which will set the pages which caused\r | |
1207 | #PF to be 'present'. The attribute of those pages should be restored in\r | |
1208 | the subsequent #DB handler.\r | |
1209 | \r | |
1210 | @param ExceptionType Exception type.\r | |
1211 | @param SystemContext Pointer to EFI_SYSTEM_CONTEXT.\r | |
1212 | \r | |
1213 | **/\r | |
1214 | VOID\r | |
1215 | EFIAPI\r | |
1216 | PageFaultExceptionHandler (\r | |
1217 | IN EFI_EXCEPTION_TYPE ExceptionType,\r | |
1218 | IN EFI_SYSTEM_CONTEXT SystemContext\r | |
1219 | )\r | |
1220 | {\r | |
1221 | EFI_STATUS Status;\r | |
1222 | UINT64 PFAddress;\r | |
1223 | PAGE_TABLE_LIB_PAGING_CONTEXT PagingContext;\r | |
1224 | PAGE_ATTRIBUTE PageAttribute;\r | |
1225 | UINT64 Attributes;\r | |
1226 | UINT64 *PageEntry;\r | |
1227 | UINTN Index;\r | |
1228 | UINTN CpuIndex;\r | |
1229 | UINTN PageNumber;\r | |
1230 | BOOLEAN NonStopMode;\r | |
1231 | \r | |
1232 | PFAddress = AsmReadCr2 () & ~EFI_PAGE_MASK;\r | |
1233 | if (PFAddress < BASE_4KB) {\r | |
1234 | NonStopMode = NULL_DETECTION_NONSTOP_MODE ? TRUE : FALSE;\r | |
1235 | } else {\r | |
1236 | NonStopMode = HEAP_GUARD_NONSTOP_MODE ? TRUE : FALSE;\r | |
1237 | }\r | |
1238 | \r | |
1239 | if (NonStopMode) {\r | |
1240 | MpInitLibWhoAmI (&CpuIndex);\r | |
1241 | GetCurrentPagingContext (&PagingContext);\r | |
1242 | //\r | |
1243 | // Memory operation cross page boundary, like "rep mov" instruction, will\r | |
1244 | // cause infinite loop between this and Debug Trap handler. We have to make\r | |
1245 | // sure that current page and the page followed are both in PRESENT state.\r | |
1246 | //\r | |
1247 | PageNumber = 2;\r | |
1248 | while (PageNumber > 0) {\r | |
1249 | PageEntry = GetPageTableEntry (&PagingContext, PFAddress, &PageAttribute);\r | |
1250 | ASSERT(PageEntry != NULL);\r | |
1251 | \r | |
1252 | if (PageEntry != NULL) {\r | |
1253 | Attributes = GetAttributesFromPageEntry (PageEntry);\r | |
1254 | if ((Attributes & EFI_MEMORY_RP) != 0) {\r | |
1255 | Attributes &= ~EFI_MEMORY_RP;\r | |
1256 | Status = AssignMemoryPageAttributes (&PagingContext, PFAddress,\r | |
1257 | EFI_PAGE_SIZE, Attributes, NULL);\r | |
1258 | if (!EFI_ERROR(Status)) {\r | |
1259 | Index = mPFEntryCount[CpuIndex];\r | |
1260 | //\r | |
1261 | // Re-retrieve page entry because above calling might update page\r | |
1262 | // table due to table split.\r | |
1263 | //\r | |
1264 | PageEntry = GetPageTableEntry (&PagingContext, PFAddress, &PageAttribute);\r | |
1265 | mLastPFEntryPointer[CpuIndex][Index++] = PageEntry;\r | |
1266 | mPFEntryCount[CpuIndex] = Index;\r | |
1267 | }\r | |
1268 | }\r | |
1269 | }\r | |
1270 | \r | |
1271 | PFAddress += EFI_PAGE_SIZE;\r | |
1272 | --PageNumber;\r | |
1273 | }\r | |
1274 | }\r | |
1275 | \r | |
1276 | //\r | |
1277 | // Initialize the serial port before dumping.\r | |
1278 | //\r | |
1279 | SerialPortInitialize ();\r | |
1280 | //\r | |
1281 | // Display ExceptionType, CPU information and Image information\r | |
1282 | //\r | |
1283 | DumpCpuContext (ExceptionType, SystemContext);\r | |
1284 | if (!NonStopMode) {\r | |
1285 | CpuDeadLoop ();\r | |
1286 | }\r | |
1287 | }\r | |
1288 | \r | |
22292ed3 JY |
1289 | /**\r |
1290 | Initialize the Page Table lib.\r | |
1291 | **/\r | |
1292 | VOID\r | |
1293 | InitializePageTableLib (\r | |
1294 | VOID\r | |
1295 | )\r | |
1296 | {\r | |
1297 | PAGE_TABLE_LIB_PAGING_CONTEXT CurrentPagingContext;\r | |
1298 | \r | |
1299 | GetCurrentPagingContext (&CurrentPagingContext);\r | |
147fd35c JW |
1300 | \r |
1301 | //\r | |
1302 | // Reserve memory of page tables for future uses, if paging is enabled.\r | |
1303 | //\r | |
1304 | if (CurrentPagingContext.ContextData.X64.PageTableBase != 0 &&\r | |
1305 | (CurrentPagingContext.ContextData.Ia32.Attributes &\r | |
1306 | PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0) {\r | |
1307 | DisableReadOnlyPageWriteProtect ();\r | |
1308 | InitializePageTablePool (1);\r | |
1309 | EnableReadOnlyPageWriteProtect ();\r | |
1310 | }\r | |
1311 | \r | |
dcc02621 JW |
1312 | if (HEAP_GUARD_NONSTOP_MODE || NULL_DETECTION_NONSTOP_MODE) {\r |
1313 | mPFEntryCount = (UINTN *)AllocateZeroPool (sizeof (UINTN) * mNumberOfProcessors);\r | |
1314 | ASSERT (mPFEntryCount != NULL);\r | |
1315 | \r | |
1316 | mLastPFEntryPointer = (UINT64 *(*)[MAX_PF_ENTRY_COUNT])\r | |
1317 | AllocateZeroPool (sizeof (mLastPFEntryPointer[0]) * mNumberOfProcessors);\r | |
1318 | ASSERT (mLastPFEntryPointer != NULL);\r | |
1319 | }\r | |
1320 | \r | |
22292ed3 JY |
1321 | DEBUG ((DEBUG_INFO, "CurrentPagingContext:\n", CurrentPagingContext.MachineType));\r |
1322 | DEBUG ((DEBUG_INFO, " MachineType - 0x%x\n", CurrentPagingContext.MachineType));\r | |
1323 | DEBUG ((DEBUG_INFO, " PageTableBase - 0x%x\n", CurrentPagingContext.ContextData.X64.PageTableBase));\r | |
1324 | DEBUG ((DEBUG_INFO, " Attributes - 0x%x\n", CurrentPagingContext.ContextData.X64.Attributes));\r | |
1325 | \r | |
1326 | return ;\r | |
1327 | }\r | |
1328 | \r |