]>
Commit | Line | Data |
---|---|---|
430fbbe0 | 1 | /** @file\r |
2 | Internal include file for the CPU I/O 2 Protocol.\r | |
3 | \r | |
7367cc6c | 4 | Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
430fbbe0 | 6 | \r |
7 | **/\r | |
8 | \r | |
9 | #ifndef _CPU_IO2_DXE_H_\r | |
10 | #define _CPU_IO2_DXE_H_\r | |
11 | \r | |
12 | #include <PiDxe.h>\r | |
13 | \r | |
14 | #include <Protocol/CpuIo2.h>\r | |
15 | \r | |
16 | #include <Library/BaseLib.h>\r | |
17 | #include <Library/DebugLib.h>\r | |
18 | #include <Library/IoLib.h>\r | |
19 | #include <Library/UefiBootServicesTableLib.h>\r | |
20 | \r | |
21 | #define MAX_IO_PORT_ADDRESS 0xFFFF\r | |
22 | \r | |
23 | /**\r | |
24 | Reads memory-mapped registers.\r | |
25 | \r | |
7367cc6c LG |
26 | The I/O operations are carried out exactly as requested. The caller is responsible\r |
27 | for satisfying any alignment and I/O width restrictions that a PI System on a\r | |
28 | platform might require. For example on some platforms, width requests of\r | |
29 | EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r | |
430fbbe0 | 30 | be handled by the driver.\r |
7367cc6c LG |
31 | \r |
32 | If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r | |
33 | or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r | |
430fbbe0 | 34 | each of the Count operations that is performed.\r |
7367cc6c LG |
35 | \r |
36 | If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r | |
37 | EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r | |
38 | incremented for each of the Count operations that is performed. The read or\r | |
430fbbe0 | 39 | write operation is performed Count times on the same Address.\r |
7367cc6c LG |
40 | \r |
41 | If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r | |
42 | EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r | |
43 | incremented for each of the Count operations that is performed. The read or\r | |
430fbbe0 | 44 | write operation is performed Count times from the first element of Buffer.\r |
7367cc6c | 45 | \r |
430fbbe0 | 46 | @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r |
47 | @param[in] Width Signifies the width of the I/O or Memory operation.\r | |
7367cc6c LG |
48 | @param[in] Address The base address of the I/O operation.\r |
49 | @param[in] Count The number of I/O operations to perform. The number of\r | |
430fbbe0 | 50 | bytes moved is Width size * Count, starting at Address.\r |
51 | @param[out] Buffer For read operations, the destination buffer to store the results.\r | |
52 | For write operations, the source buffer from which to write data.\r | |
53 | \r | |
54 | @retval EFI_SUCCESS The data was read from or written to the PI system.\r | |
55 | @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r | |
56 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
57 | @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r | |
7367cc6c | 58 | @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r |
430fbbe0 | 59 | and Count is not valid for this PI system.\r |
60 | \r | |
61 | **/\r | |
62 | EFI_STATUS\r | |
63 | EFIAPI\r | |
64 | CpuMemoryServiceRead (\r | |
65 | IN EFI_CPU_IO2_PROTOCOL *This,\r | |
66 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
67 | IN UINT64 Address,\r | |
68 | IN UINTN Count,\r | |
69 | OUT VOID *Buffer\r | |
70 | );\r | |
71 | \r | |
72 | /**\r | |
73 | Writes memory-mapped registers.\r | |
74 | \r | |
7367cc6c LG |
75 | The I/O operations are carried out exactly as requested. The caller is responsible\r |
76 | for satisfying any alignment and I/O width restrictions that a PI System on a\r | |
77 | platform might require. For example on some platforms, width requests of\r | |
78 | EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r | |
430fbbe0 | 79 | be handled by the driver.\r |
7367cc6c LG |
80 | \r |
81 | If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r | |
82 | or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r | |
430fbbe0 | 83 | each of the Count operations that is performed.\r |
7367cc6c LG |
84 | \r |
85 | If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r | |
86 | EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r | |
87 | incremented for each of the Count operations that is performed. The read or\r | |
430fbbe0 | 88 | write operation is performed Count times on the same Address.\r |
7367cc6c LG |
89 | \r |
90 | If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r | |
91 | EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r | |
92 | incremented for each of the Count operations that is performed. The read or\r | |
430fbbe0 | 93 | write operation is performed Count times from the first element of Buffer.\r |
7367cc6c | 94 | \r |
430fbbe0 | 95 | @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r |
96 | @param[in] Width Signifies the width of the I/O or Memory operation.\r | |
7367cc6c LG |
97 | @param[in] Address The base address of the I/O operation.\r |
98 | @param[in] Count The number of I/O operations to perform. The number of\r | |
430fbbe0 | 99 | bytes moved is Width size * Count, starting at Address.\r |
100 | @param[in] Buffer For read operations, the destination buffer to store the results.\r | |
101 | For write operations, the source buffer from which to write data.\r | |
102 | \r | |
103 | @retval EFI_SUCCESS The data was read from or written to the PI system.\r | |
104 | @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r | |
105 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
106 | @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r | |
7367cc6c | 107 | @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r |
430fbbe0 | 108 | and Count is not valid for this PI system.\r |
109 | \r | |
110 | **/\r | |
111 | EFI_STATUS\r | |
112 | EFIAPI\r | |
113 | CpuMemoryServiceWrite (\r | |
114 | IN EFI_CPU_IO2_PROTOCOL *This,\r | |
115 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
116 | IN UINT64 Address,\r | |
117 | IN UINTN Count,\r | |
118 | IN VOID *Buffer\r | |
119 | );\r | |
120 | \r | |
121 | /**\r | |
122 | Reads I/O registers.\r | |
123 | \r | |
7367cc6c LG |
124 | The I/O operations are carried out exactly as requested. The caller is responsible\r |
125 | for satisfying any alignment and I/O width restrictions that a PI System on a\r | |
126 | platform might require. For example on some platforms, width requests of\r | |
127 | EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r | |
430fbbe0 | 128 | be handled by the driver.\r |
7367cc6c LG |
129 | \r |
130 | If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r | |
131 | or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r | |
430fbbe0 | 132 | each of the Count operations that is performed.\r |
7367cc6c LG |
133 | \r |
134 | If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r | |
135 | EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r | |
136 | incremented for each of the Count operations that is performed. The read or\r | |
430fbbe0 | 137 | write operation is performed Count times on the same Address.\r |
7367cc6c LG |
138 | \r |
139 | If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r | |
140 | EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r | |
141 | incremented for each of the Count operations that is performed. The read or\r | |
430fbbe0 | 142 | write operation is performed Count times from the first element of Buffer.\r |
7367cc6c | 143 | \r |
430fbbe0 | 144 | @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r |
145 | @param[in] Width Signifies the width of the I/O or Memory operation.\r | |
7367cc6c LG |
146 | @param[in] Address The base address of the I/O operation.\r |
147 | @param[in] Count The number of I/O operations to perform. The number of\r | |
430fbbe0 | 148 | bytes moved is Width size * Count, starting at Address.\r |
149 | @param[out] Buffer For read operations, the destination buffer to store the results.\r | |
150 | For write operations, the source buffer from which to write data.\r | |
151 | \r | |
152 | @retval EFI_SUCCESS The data was read from or written to the PI system.\r | |
153 | @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r | |
154 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
155 | @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r | |
7367cc6c | 156 | @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r |
430fbbe0 | 157 | and Count is not valid for this PI system.\r |
158 | \r | |
159 | **/\r | |
160 | EFI_STATUS\r | |
161 | EFIAPI\r | |
162 | CpuIoServiceRead (\r | |
163 | IN EFI_CPU_IO2_PROTOCOL *This,\r | |
164 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
165 | IN UINT64 Address,\r | |
166 | IN UINTN Count,\r | |
167 | OUT VOID *Buffer\r | |
168 | );\r | |
169 | \r | |
170 | /**\r | |
171 | Write I/O registers.\r | |
172 | \r | |
7367cc6c LG |
173 | The I/O operations are carried out exactly as requested. The caller is responsible\r |
174 | for satisfying any alignment and I/O width restrictions that a PI System on a\r | |
175 | platform might require. For example on some platforms, width requests of\r | |
176 | EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r | |
430fbbe0 | 177 | be handled by the driver.\r |
7367cc6c LG |
178 | \r |
179 | If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r | |
180 | or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r | |
430fbbe0 | 181 | each of the Count operations that is performed.\r |
7367cc6c LG |
182 | \r |
183 | If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r | |
184 | EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r | |
185 | incremented for each of the Count operations that is performed. The read or\r | |
430fbbe0 | 186 | write operation is performed Count times on the same Address.\r |
7367cc6c LG |
187 | \r |
188 | If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r | |
189 | EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r | |
190 | incremented for each of the Count operations that is performed. The read or\r | |
430fbbe0 | 191 | write operation is performed Count times from the first element of Buffer.\r |
7367cc6c | 192 | \r |
430fbbe0 | 193 | @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r |
194 | @param[in] Width Signifies the width of the I/O or Memory operation.\r | |
7367cc6c LG |
195 | @param[in] Address The base address of the I/O operation.\r |
196 | @param[in] Count The number of I/O operations to perform. The number of\r | |
430fbbe0 | 197 | bytes moved is Width size * Count, starting at Address.\r |
198 | @param[in] Buffer For read operations, the destination buffer to store the results.\r | |
199 | For write operations, the source buffer from which to write data.\r | |
200 | \r | |
201 | @retval EFI_SUCCESS The data was read from or written to the PI system.\r | |
202 | @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r | |
203 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
204 | @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r | |
7367cc6c | 205 | @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r |
430fbbe0 | 206 | and Count is not valid for this PI system.\r |
7367cc6c | 207 | \r |
430fbbe0 | 208 | **/\r |
209 | EFI_STATUS\r | |
210 | EFIAPI\r | |
211 | CpuIoServiceWrite (\r | |
212 | IN EFI_CPU_IO2_PROTOCOL *This,\r | |
213 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
214 | IN UINT64 Address,\r | |
215 | IN UINTN Count,\r | |
216 | IN VOID *Buffer\r | |
217 | );\r | |
218 | \r | |
219 | #endif\r |