]>
Commit | Line | Data |
---|---|---|
430fbbe0 | 1 | /** @file\r |
2 | Internal include file for the CPU I/O 2 Protocol.\r | |
3 | \r | |
4 | Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r | |
5 | This program and the accompanying materials \r | |
6 | are licensed and made available under the terms and conditions of the BSD License \r | |
7 | which accompanies this distribution. The full text of the license may be found at \r | |
8 | http://opensource.org/licenses/bsd-license.php \r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef _CPU_IO2_DXE_H_\r | |
16 | #define _CPU_IO2_DXE_H_\r | |
17 | \r | |
18 | #include <PiDxe.h>\r | |
19 | \r | |
20 | #include <Protocol/CpuIo2.h>\r | |
21 | \r | |
22 | #include <Library/BaseLib.h>\r | |
23 | #include <Library/DebugLib.h>\r | |
24 | #include <Library/IoLib.h>\r | |
25 | #include <Library/UefiBootServicesTableLib.h>\r | |
26 | \r | |
27 | #define MAX_IO_PORT_ADDRESS 0xFFFF\r | |
28 | \r | |
29 | /**\r | |
30 | Reads memory-mapped registers.\r | |
31 | \r | |
32 | The I/O operations are carried out exactly as requested. The caller is responsible \r | |
33 | for satisfying any alignment and I/O width restrictions that a PI System on a \r | |
34 | platform might require. For example on some platforms, width requests of \r | |
35 | EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r | |
36 | be handled by the driver.\r | |
37 | \r | |
38 | If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r | |
39 | or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r | |
40 | each of the Count operations that is performed.\r | |
41 | \r | |
42 | If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r | |
43 | EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r | |
44 | incremented for each of the Count operations that is performed. The read or \r | |
45 | write operation is performed Count times on the same Address.\r | |
46 | \r | |
47 | If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r | |
48 | EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r | |
49 | incremented for each of the Count operations that is performed. The read or \r | |
50 | write operation is performed Count times from the first element of Buffer.\r | |
51 | \r | |
52 | @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r | |
53 | @param[in] Width Signifies the width of the I/O or Memory operation.\r | |
54 | @param[in] Address The base address of the I/O operation. \r | |
55 | @param[in] Count The number of I/O operations to perform. The number of \r | |
56 | bytes moved is Width size * Count, starting at Address.\r | |
57 | @param[out] Buffer For read operations, the destination buffer to store the results.\r | |
58 | For write operations, the source buffer from which to write data.\r | |
59 | \r | |
60 | @retval EFI_SUCCESS The data was read from or written to the PI system.\r | |
61 | @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r | |
62 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
63 | @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r | |
64 | @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r | |
65 | and Count is not valid for this PI system.\r | |
66 | \r | |
67 | **/\r | |
68 | EFI_STATUS\r | |
69 | EFIAPI\r | |
70 | CpuMemoryServiceRead (\r | |
71 | IN EFI_CPU_IO2_PROTOCOL *This,\r | |
72 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
73 | IN UINT64 Address,\r | |
74 | IN UINTN Count,\r | |
75 | OUT VOID *Buffer\r | |
76 | );\r | |
77 | \r | |
78 | /**\r | |
79 | Writes memory-mapped registers.\r | |
80 | \r | |
81 | The I/O operations are carried out exactly as requested. The caller is responsible \r | |
82 | for satisfying any alignment and I/O width restrictions that a PI System on a \r | |
83 | platform might require. For example on some platforms, width requests of \r | |
84 | EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r | |
85 | be handled by the driver.\r | |
86 | \r | |
87 | If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r | |
88 | or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r | |
89 | each of the Count operations that is performed.\r | |
90 | \r | |
91 | If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r | |
92 | EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r | |
93 | incremented for each of the Count operations that is performed. The read or \r | |
94 | write operation is performed Count times on the same Address.\r | |
95 | \r | |
96 | If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r | |
97 | EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r | |
98 | incremented for each of the Count operations that is performed. The read or \r | |
99 | write operation is performed Count times from the first element of Buffer.\r | |
100 | \r | |
101 | @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r | |
102 | @param[in] Width Signifies the width of the I/O or Memory operation.\r | |
103 | @param[in] Address The base address of the I/O operation. \r | |
104 | @param[in] Count The number of I/O operations to perform. The number of \r | |
105 | bytes moved is Width size * Count, starting at Address.\r | |
106 | @param[in] Buffer For read operations, the destination buffer to store the results.\r | |
107 | For write operations, the source buffer from which to write data.\r | |
108 | \r | |
109 | @retval EFI_SUCCESS The data was read from or written to the PI system.\r | |
110 | @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r | |
111 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
112 | @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r | |
113 | @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r | |
114 | and Count is not valid for this PI system.\r | |
115 | \r | |
116 | **/\r | |
117 | EFI_STATUS\r | |
118 | EFIAPI\r | |
119 | CpuMemoryServiceWrite (\r | |
120 | IN EFI_CPU_IO2_PROTOCOL *This,\r | |
121 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
122 | IN UINT64 Address,\r | |
123 | IN UINTN Count,\r | |
124 | IN VOID *Buffer\r | |
125 | );\r | |
126 | \r | |
127 | /**\r | |
128 | Reads I/O registers.\r | |
129 | \r | |
130 | The I/O operations are carried out exactly as requested. The caller is responsible \r | |
131 | for satisfying any alignment and I/O width restrictions that a PI System on a \r | |
132 | platform might require. For example on some platforms, width requests of \r | |
133 | EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r | |
134 | be handled by the driver.\r | |
135 | \r | |
136 | If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r | |
137 | or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r | |
138 | each of the Count operations that is performed.\r | |
139 | \r | |
140 | If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r | |
141 | EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r | |
142 | incremented for each of the Count operations that is performed. The read or \r | |
143 | write operation is performed Count times on the same Address.\r | |
144 | \r | |
145 | If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r | |
146 | EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r | |
147 | incremented for each of the Count operations that is performed. The read or \r | |
148 | write operation is performed Count times from the first element of Buffer.\r | |
149 | \r | |
150 | @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r | |
151 | @param[in] Width Signifies the width of the I/O or Memory operation.\r | |
152 | @param[in] Address The base address of the I/O operation. \r | |
153 | @param[in] Count The number of I/O operations to perform. The number of \r | |
154 | bytes moved is Width size * Count, starting at Address.\r | |
155 | @param[out] Buffer For read operations, the destination buffer to store the results.\r | |
156 | For write operations, the source buffer from which to write data.\r | |
157 | \r | |
158 | @retval EFI_SUCCESS The data was read from or written to the PI system.\r | |
159 | @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r | |
160 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
161 | @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r | |
162 | @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r | |
163 | and Count is not valid for this PI system.\r | |
164 | \r | |
165 | **/\r | |
166 | EFI_STATUS\r | |
167 | EFIAPI\r | |
168 | CpuIoServiceRead (\r | |
169 | IN EFI_CPU_IO2_PROTOCOL *This,\r | |
170 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
171 | IN UINT64 Address,\r | |
172 | IN UINTN Count,\r | |
173 | OUT VOID *Buffer\r | |
174 | );\r | |
175 | \r | |
176 | /**\r | |
177 | Write I/O registers.\r | |
178 | \r | |
179 | The I/O operations are carried out exactly as requested. The caller is responsible \r | |
180 | for satisfying any alignment and I/O width restrictions that a PI System on a \r | |
181 | platform might require. For example on some platforms, width requests of \r | |
182 | EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r | |
183 | be handled by the driver.\r | |
184 | \r | |
185 | If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r | |
186 | or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r | |
187 | each of the Count operations that is performed.\r | |
188 | \r | |
189 | If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r | |
190 | EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r | |
191 | incremented for each of the Count operations that is performed. The read or \r | |
192 | write operation is performed Count times on the same Address.\r | |
193 | \r | |
194 | If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r | |
195 | EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r | |
196 | incremented for each of the Count operations that is performed. The read or \r | |
197 | write operation is performed Count times from the first element of Buffer.\r | |
198 | \r | |
199 | @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r | |
200 | @param[in] Width Signifies the width of the I/O or Memory operation.\r | |
201 | @param[in] Address The base address of the I/O operation. \r | |
202 | @param[in] Count The number of I/O operations to perform. The number of \r | |
203 | bytes moved is Width size * Count, starting at Address.\r | |
204 | @param[in] Buffer For read operations, the destination buffer to store the results.\r | |
205 | For write operations, the source buffer from which to write data.\r | |
206 | \r | |
207 | @retval EFI_SUCCESS The data was read from or written to the PI system.\r | |
208 | @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r | |
209 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
210 | @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r | |
211 | @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r | |
212 | and Count is not valid for this PI system.\r | |
213 | \r | |
214 | **/\r | |
215 | EFI_STATUS\r | |
216 | EFIAPI\r | |
217 | CpuIoServiceWrite (\r | |
218 | IN EFI_CPU_IO2_PROTOCOL *This,\r | |
219 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
220 | IN UINT64 Address,\r | |
221 | IN UINTN Count,\r | |
222 | IN VOID *Buffer\r | |
223 | );\r | |
224 | \r | |
225 | #endif\r |