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ea0f431c | 1 | ;------------------------------------------------------------------------------ ;\r |
249ed12e | 2 | ; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r |
ea0f431c JF |
3 | ; This program and the accompanying materials\r |
4 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
5 | ; which accompanies this distribution. The full text of the license may be found at\r | |
6 | ; http://opensource.org/licenses/bsd-license.php.\r | |
7 | ;\r | |
8 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
9 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
10 | ;\r | |
11 | ; Module Name:\r | |
12 | ;\r | |
13 | ; MpFuncs.nasm\r | |
14 | ;\r | |
15 | ; Abstract:\r | |
16 | ;\r | |
17 | ; This is the assembly code for MP support\r | |
18 | ;\r | |
19 | ;-------------------------------------------------------------------------------\r | |
20 | \r | |
21 | %include "MpEqu.inc"\r | |
22 | extern ASM_PFX(InitializeFloatingPointUnits)\r | |
23 | \r | |
24 | DEFAULT REL\r | |
25 | \r | |
26 | SECTION .text\r | |
27 | \r | |
28 | ;-------------------------------------------------------------------------------------\r | |
29 | ;RendezvousFunnelProc procedure follows. All APs execute their procedure. This\r | |
30 | ;procedure serializes all the AP processors through an Init sequence. It must be\r | |
31 | ;noted that APs arrive here very raw...ie: real mode, no stack.\r | |
32 | ;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r | |
33 | ;IS IN MACHINE CODE.\r | |
34 | ;-------------------------------------------------------------------------------------\r | |
35 | global ASM_PFX(RendezvousFunnelProc)\r | |
36 | ASM_PFX(RendezvousFunnelProc):\r | |
37 | RendezvousFunnelProcStart:\r | |
38 | ; At this point CS = 0x(vv00) and ip= 0x0.\r | |
39 | ; Save BIST information to ebp firstly\r | |
ea0f431c | 40 | \r |
249ed12e JF |
41 | BITS 16\r |
42 | mov ebp, eax ; Save BIST information\r | |
ea0f431c JF |
43 | \r |
44 | mov ax, cs\r | |
45 | mov ds, ax\r | |
46 | mov es, ax\r | |
47 | mov ss, ax\r | |
48 | xor ax, ax\r | |
49 | mov fs, ax\r | |
50 | mov gs, ax\r | |
51 | \r | |
52 | mov si, BufferStartLocation\r | |
53 | mov ebx, [si]\r | |
54 | \r | |
d1471c01 | 55 | mov di, LmodeOffsetLocation\r |
ea0f431c | 56 | mov eax, [di]\r |
d1471c01 JF |
57 | mov di, CodeSegmentLocation\r |
58 | mov edx, [di]\r | |
ea0f431c | 59 | mov di, ax\r |
d1471c01 JF |
60 | sub di, 02h \r |
61 | mov [di],dx ; Patch long mode CS\r | |
62 | sub di, 04h\r | |
ea0f431c | 63 | add eax, ebx\r |
d1471c01 | 64 | mov [di],eax ; Patch address\r |
ea0f431c JF |
65 | \r |
66 | mov si, GdtrLocation\r | |
67 | o32 lgdt [cs:si]\r | |
68 | \r | |
69 | mov si, IdtrLocation\r | |
70 | o32 lidt [cs:si]\r | |
71 | \r | |
72 | \r | |
d1471c01 JF |
73 | mov di, DataSegmentLocation\r |
74 | mov edi, [di] ; Save long mode DS in edi\r | |
75 | \r | |
76 | mov si, Cr3Location ; Save CR3 in ecx\r | |
77 | mov ecx, [si]\r | |
78 | \r | |
ea0f431c | 79 | xor ax, ax\r |
d1471c01 | 80 | mov ds, ax ; Clear data segment\r |
ea0f431c | 81 | \r |
d1471c01 JF |
82 | mov eax, cr0 ; Get control register 0\r |
83 | or eax, 000000003h ; Set PE bit (bit #0) & MP\r | |
ea0f431c JF |
84 | mov cr0, eax\r |
85 | \r | |
ea0f431c JF |
86 | mov eax, cr4\r |
87 | bts eax, 5\r | |
88 | mov cr4, eax\r | |
89 | \r | |
d1471c01 | 90 | mov cr3, ecx ; Load CR3\r |
ea0f431c | 91 | \r |
d1471c01 JF |
92 | mov ecx, 0c0000080h ; EFER MSR number\r |
93 | rdmsr ; Read EFER\r | |
94 | bts eax, 8 ; Set LME=1\r | |
95 | wrmsr ; Write EFER\r | |
ea0f431c | 96 | \r |
d1471c01 JF |
97 | mov eax, cr0 ; Read CR0\r |
98 | bts eax, 31 ; Set PG=1\r | |
99 | mov cr0, eax ; Write CR0\r | |
ea0f431c | 100 | \r |
d1471c01 | 101 | jmp 0:strict dword 0 ; far jump to long mode\r |
ea0f431c JF |
102 | BITS 64\r |
103 | LongModeStart:\r | |
d1471c01 | 104 | mov eax, edi\r |
ea0f431c JF |
105 | mov ds, ax\r |
106 | mov es, ax\r | |
107 | mov ss, ax\r | |
108 | \r | |
109 | mov esi, ebx\r | |
110 | mov edi, esi\r | |
111 | add edi, LockLocation\r | |
112 | mov rax, NotVacantFlag\r | |
113 | \r | |
114 | TestLock:\r | |
115 | xchg qword [edi], rax\r | |
116 | cmp rax, NotVacantFlag\r | |
117 | jz TestLock\r | |
118 | \r | |
119 | mov edi, esi\r | |
120 | add edi, NumApsExecutingLoction\r | |
121 | inc dword [edi]\r | |
122 | mov ebx, [edi]\r | |
123 | \r | |
124 | ProgramStack:\r | |
125 | mov edi, esi\r | |
126 | add edi, StackSizeLocation\r | |
127 | mov rax, qword [edi]\r | |
128 | mov edi, esi\r | |
129 | add edi, StackStartAddressLocation\r | |
130 | add rax, qword [edi]\r | |
131 | mov rsp, rax\r | |
132 | mov qword [edi], rax\r | |
133 | \r | |
134 | Releaselock:\r | |
135 | mov rax, VacantFlag\r | |
136 | mov edi, esi\r | |
137 | add edi, LockLocation\r | |
138 | xchg qword [edi], rax\r | |
139 | \r | |
140 | CProcedureInvoke:\r | |
141 | push rbp ; push BIST data at top of AP stack\r | |
142 | xor rbp, rbp ; clear ebp for call stack trace\r | |
143 | push rbp\r | |
144 | mov rbp, rsp\r | |
145 | \r | |
146 | mov rax, ASM_PFX(InitializeFloatingPointUnits)\r | |
147 | sub rsp, 20h\r | |
148 | call rax ; Call assembly function to initialize FPU per UEFI spec\r | |
149 | add rsp, 20h\r | |
150 | \r | |
151 | mov edx, ebx ; edx is NumApsExecuting\r | |
152 | mov ecx, esi\r | |
153 | add ecx, LockLocation ; rcx is address of exchange info data buffer\r | |
154 | \r | |
155 | mov edi, esi\r | |
156 | add edi, ApProcedureLocation\r | |
157 | mov rax, qword [edi]\r | |
158 | \r | |
159 | sub rsp, 20h\r | |
160 | call rax ; invoke C function\r | |
161 | add rsp, 20h\r | |
d1471c01 | 162 | jmp $\r |
ea0f431c JF |
163 | \r |
164 | RendezvousFunnelProcEnd:\r | |
165 | \r | |
ea0f431c JF |
166 | ;-------------------------------------------------------------------------------------\r |
167 | ; AsmGetAddressMap (&AddressMap);\r | |
168 | ;-------------------------------------------------------------------------------------\r | |
169 | global ASM_PFX(AsmGetAddressMap)\r | |
170 | ASM_PFX(AsmGetAddressMap):\r | |
171 | mov rax, ASM_PFX(RendezvousFunnelProc)\r | |
172 | mov qword [rcx], rax\r | |
d1471c01 | 173 | mov qword [rcx + 8h], 0\r |
ea0f431c JF |
174 | mov qword [rcx + 10h], LongModeStart - RendezvousFunnelProcStart\r |
175 | mov qword [rcx + 18h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r | |
176 | ret\r | |
177 | \r | |
178 | ;-------------------------------------------------------------------------------------\r | |
179 | ;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r | |
180 | ;about to become an AP. It switches it'stack with the current AP.\r | |
181 | ;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);\r | |
182 | ;-------------------------------------------------------------------------------------\r | |
183 | global ASM_PFX(AsmExchangeRole)\r | |
184 | ASM_PFX(AsmExchangeRole):\r | |
185 | ; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r | |
186 | ; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r | |
187 | \r | |
188 | push rax\r | |
189 | push rbx\r | |
190 | push rcx\r | |
191 | push rdx\r | |
192 | push rsi\r | |
193 | push rdi\r | |
194 | push rbp\r | |
195 | push r8\r | |
196 | push r9\r | |
197 | push r10\r | |
198 | push r11\r | |
199 | push r12\r | |
200 | push r13\r | |
201 | push r14\r | |
202 | push r15\r | |
203 | \r | |
204 | mov rax, cr0\r | |
205 | push rax\r | |
206 | \r | |
207 | mov rax, cr4\r | |
208 | push rax\r | |
209 | \r | |
210 | ; rsi contains MyInfo pointer\r | |
211 | mov rsi, rcx\r | |
212 | \r | |
213 | ; rdi contains OthersInfo pointer\r | |
214 | mov rdi, rdx\r | |
215 | \r | |
216 | ;Store EFLAGS, GDTR and IDTR regiter to stack\r | |
217 | pushfq\r | |
218 | sgdt [rsi + 16]\r | |
219 | sidt [rsi + 26]\r | |
220 | \r | |
221 | ; Store the its StackPointer\r | |
222 | mov [rsi + 8], rsp\r | |
223 | \r | |
224 | ; update its switch state to STORED\r | |
225 | mov byte [rsi], CPU_SWITCH_STATE_STORED\r | |
226 | \r | |
227 | WaitForOtherStored:\r | |
228 | ; wait until the other CPU finish storing its state\r | |
229 | cmp byte [rdi], CPU_SWITCH_STATE_STORED\r | |
230 | jz OtherStored\r | |
231 | pause\r | |
232 | jmp WaitForOtherStored\r | |
233 | \r | |
234 | OtherStored:\r | |
235 | ; Since another CPU already stored its state, load them\r | |
236 | ; load GDTR value\r | |
237 | lgdt [rdi + 16]\r | |
238 | \r | |
239 | ; load IDTR value\r | |
240 | lidt [rdi + 26]\r | |
241 | \r | |
242 | ; load its future StackPointer\r | |
243 | mov rsp, [rdi + 8]\r | |
244 | \r | |
245 | ; update the other CPU's switch state to LOADED\r | |
246 | mov byte [rdi], CPU_SWITCH_STATE_LOADED\r | |
247 | \r | |
248 | WaitForOtherLoaded:\r | |
249 | ; wait until the other CPU finish loading new state,\r | |
250 | ; otherwise the data in stack may corrupt\r | |
251 | cmp byte [rsi], CPU_SWITCH_STATE_LOADED\r | |
252 | jz OtherLoaded\r | |
253 | pause\r | |
254 | jmp WaitForOtherLoaded\r | |
255 | \r | |
256 | OtherLoaded:\r | |
257 | ; since the other CPU already get the data it want, leave this procedure\r | |
258 | popfq\r | |
259 | \r | |
260 | pop rax\r | |
261 | mov cr4, rax\r | |
262 | \r | |
263 | pop rax\r | |
264 | mov cr0, rax\r | |
265 | \r | |
266 | pop r15\r | |
267 | pop r14\r | |
268 | pop r13\r | |
269 | pop r12\r | |
270 | pop r11\r | |
271 | pop r10\r | |
272 | pop r9\r | |
273 | pop r8\r | |
274 | pop rbp\r | |
275 | pop rdi\r | |
276 | pop rsi\r | |
277 | pop rdx\r | |
278 | pop rcx\r | |
279 | pop rbx\r | |
280 | pop rax\r | |
281 | \r | |
282 | ret\r |