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1c27f926 MK |
1 | /** @file\r |
2 | Definitions for CPU S3 data.\r | |
3 | \r | |
010753b7 | 4 | Copyright (c) 2013 - 2021, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1c27f926 MK |
6 | \r |
7 | **/\r | |
8 | \r | |
9 | #ifndef _ACPI_CPU_DATA_H_\r | |
10 | #define _ACPI_CPU_DATA_H_\r | |
11 | \r | |
010753b7 LY |
12 | //\r |
13 | // This macro definition is used to fix incompatibility issue caused by\r | |
14 | // ACPI_CPU_DATA structure update. It will be removed after all the platform\r | |
15 | // code uses new ACPI_CPU_DATA structure.\r | |
16 | //\r | |
17 | #define ACPI_CPU_DATA_STRUCTURE_UPDATE\r | |
18 | \r | |
1c27f926 MK |
19 | //\r |
20 | // Register types in register table\r | |
21 | //\r | |
af381fda | 22 | typedef enum {\r |
1c27f926 MK |
23 | Msr,\r |
24 | ControlRegister,\r | |
25 | MemoryMapped,\r | |
d5aa2078 ED |
26 | CacheControl,\r |
27 | \r | |
28 | //\r | |
29 | // Semaphore type used to control the execute sequence of the Msr.\r | |
30 | // It will be insert between two Msr which has execute dependence.\r | |
31 | //\r | |
32 | Semaphore,\r | |
33 | InvalidReg\r | |
1c27f926 MK |
34 | } REGISTER_TYPE;\r |
35 | \r | |
d5aa2078 ED |
36 | //\r |
37 | // Describe the dependency type for different features.\r | |
38 | // The value set to CPU_REGISTER_TABLE_ENTRY.Value when the REGISTER_TYPE is Semaphore.\r | |
39 | //\r | |
40 | typedef enum {\r | |
41 | NoneDepType,\r | |
42 | ThreadDepType,\r | |
43 | CoreDepType,\r | |
44 | PackageDepType,\r | |
45 | InvalidDepType\r | |
46 | } CPU_FEATURE_DEPENDENCE_TYPE;\r | |
47 | \r | |
48 | //\r | |
49 | // CPU information.\r | |
50 | //\r | |
51 | typedef struct {\r | |
52 | //\r | |
53 | // Record the package count in this CPU.\r | |
54 | //\r | |
053e878b | 55 | UINT32 PackageCount;\r |
d5aa2078 ED |
56 | //\r |
57 | // Record the max core count in this CPU.\r | |
58 | // Different packages may have different core count, this value\r | |
59 | // save the max core count in all the packages.\r | |
60 | //\r | |
053e878b | 61 | UINT32 MaxCoreCount;\r |
d5aa2078 ED |
62 | //\r |
63 | // Record the max thread count in this CPU.\r | |
64 | // Different cores may have different thread count, this value\r | |
65 | // save the max thread count in all the cores.\r | |
66 | //\r | |
053e878b | 67 | UINT32 MaxThreadCount;\r |
d5aa2078 ED |
68 | //\r |
69 | // This field points to an array.\r | |
6af76adb | 70 | // This array saves thread count (type UINT32) of each package.\r |
d5aa2078 ED |
71 | // The array has PackageCount elements.\r |
72 | //\r | |
73 | // If the platform does not support MSR setting at S3 resume, and\r | |
74 | // therefore it doesn't need the dependency semaphores, it should set\r | |
75 | // this field to 0.\r | |
76 | //\r | |
053e878b | 77 | EFI_PHYSICAL_ADDRESS ThreadCountPerPackage;\r |
6af76adb RN |
78 | //\r |
79 | // This field points to an array.\r | |
80 | // This array saves thread count (type UINT8) of each core.\r | |
81 | // The array has PackageCount * MaxCoreCount elements.\r | |
82 | //\r | |
83 | // If the platform does not support MSR setting at S3 resume, and\r | |
84 | // therefore it doesn't need the dependency semaphores, it should set\r | |
85 | // this field to 0.\r | |
86 | //\r | |
053e878b | 87 | EFI_PHYSICAL_ADDRESS ThreadCountPerCore;\r |
d5aa2078 ED |
88 | } CPU_STATUS_INFORMATION;\r |
89 | \r | |
1c27f926 MK |
90 | //\r |
91 | // Element of register table entry\r | |
92 | //\r | |
93 | typedef struct {\r | |
053e878b MK |
94 | REGISTER_TYPE RegisterType; // offset 0 - 3\r |
95 | UINT32 Index; // offset 4 - 7\r | |
96 | UINT8 ValidBitStart; // offset 8\r | |
97 | UINT8 ValidBitLength; // offset 9\r | |
98 | BOOLEAN TestThenWrite; // offset 10\r | |
99 | UINT8 Reserved1; // offset 11\r | |
100 | UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped\r | |
101 | UINT64 Value; // offset 16-23\r | |
1c27f926 MK |
102 | } CPU_REGISTER_TABLE_ENTRY;\r |
103 | \r | |
104 | //\r | |
105 | // Register table definition, including current table length,\r | |
106 | // allocated size of this table, and pointer to the list of table entries.\r | |
107 | //\r | |
108 | typedef struct {\r | |
af381fda MK |
109 | //\r |
110 | // The number of valid entries in the RegisterTableEntry buffer\r | |
111 | //\r | |
053e878b MK |
112 | UINT32 TableLength;\r |
113 | UINT32 NumberBeforeReset;\r | |
af381fda MK |
114 | //\r |
115 | // The size, in bytes, of the RegisterTableEntry buffer\r | |
116 | //\r | |
053e878b | 117 | UINT32 AllocatedSize;\r |
af381fda MK |
118 | //\r |
119 | // The initial APIC ID of the CPU this register table applies to\r | |
120 | //\r | |
053e878b | 121 | UINT32 InitialApicId;\r |
af381fda | 122 | //\r |
fcd92f16 | 123 | // Physical address of CPU_REGISTER_TABLE_ENTRY structures.\r |
af381fda | 124 | //\r |
053e878b | 125 | EFI_PHYSICAL_ADDRESS RegisterTableEntry;\r |
1c27f926 MK |
126 | } CPU_REGISTER_TABLE;\r |
127 | \r | |
010753b7 LY |
128 | //\r |
129 | // Data structure that is used for CPU feature initialization during ACPI S3\r | |
130 | // resume.\r | |
131 | //\r | |
132 | typedef struct {\r | |
133 | //\r | |
134 | // Physical address of an array of CPU_REGISTER_TABLE structures, with\r | |
135 | // NumberOfCpus entries. If a register table is not required, then the\r | |
136 | // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.\r | |
137 | // If TableLength is > 0, then elements of RegisterTableEntry are used to\r | |
138 | // initialize the CPU that matches InitialApicId, during an ACPI S3 resume,\r | |
139 | // before SMBASE relocation is performed.\r | |
140 | // If a register table is not required for any one of the CPUs, then\r | |
141 | // PreSmmInitRegisterTable may be set to 0.\r | |
142 | //\r | |
143 | EFI_PHYSICAL_ADDRESS PreSmmInitRegisterTable;\r | |
144 | //\r | |
145 | // Physical address of an array of CPU_REGISTER_TABLE structures, with\r | |
146 | // NumberOfCpus entries. If a register table is not required, then the\r | |
147 | // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.\r | |
148 | // If TableLength is > 0, then elements of RegisterTableEntry are used to\r | |
149 | // initialize the CPU that matches InitialApicId, during an ACPI S3 resume,\r | |
150 | // after SMBASE relocation is performed.\r | |
151 | // If a register table is not required for any one of the CPUs, then\r | |
152 | // RegisterTable may be set to 0.\r | |
153 | //\r | |
053e878b | 154 | EFI_PHYSICAL_ADDRESS RegisterTable;\r |
010753b7 LY |
155 | //\r |
156 | // CPU information which is required when set the register table.\r | |
157 | //\r | |
053e878b | 158 | CPU_STATUS_INFORMATION CpuStatus;\r |
010753b7 LY |
159 | //\r |
160 | // Location info for each AP.\r | |
161 | // It points to an array which saves all APs location info.\r | |
162 | // The array count is the AP count in this CPU.\r | |
163 | //\r | |
164 | // If the platform does not support MSR setting at S3 resume, and\r | |
165 | // therefore it doesn't need the dependency semaphores, it should set\r | |
166 | // this field to 0.\r | |
167 | //\r | |
168 | EFI_PHYSICAL_ADDRESS ApLocation;\r | |
169 | } CPU_FEATURE_INIT_DATA;\r | |
170 | \r | |
af381fda | 171 | //\r |
fcd92f16 | 172 | // Data structure that is required for ACPI S3 resume. The PCD\r |
af381fda MK |
173 | // PcdCpuS3DataAddress must be set to the physical address where this structure\r |
174 | // is allocated\r | |
175 | //\r | |
1c27f926 | 176 | typedef struct {\r |
af381fda MK |
177 | //\r |
178 | // Physical address of 4KB buffer allocated below 1MB from memory of type\r | |
179 | // EfiReservedMemoryType. The buffer is not required to be initialized, but\r | |
180 | // it is recommended that the buffer be zero-filled. This buffer is used to\r | |
181 | // wake APs during an ACPI S3 resume.\r | |
182 | //\r | |
053e878b | 183 | EFI_PHYSICAL_ADDRESS StartupVector;\r |
af381fda | 184 | //\r |
fcd92f16 | 185 | // Physical address of structure of type IA32_DESCRIPTOR. The\r |
af381fda | 186 | // IA32_DESCRIPTOR structure provides the base address and length of a GDT\r |
fcd92f16 | 187 | // The GDT must be filled in with the GDT contents that are\r |
af381fda MK |
188 | // used during an ACPI S3 resume. This is typically the contents of the GDT\r |
189 | // used by the boot processor when the platform is booted.\r | |
190 | //\r | |
053e878b | 191 | EFI_PHYSICAL_ADDRESS GdtrProfile;\r |
af381fda | 192 | //\r |
fcd92f16 | 193 | // Physical address of structure of type IA32_DESCRIPTOR. The\r |
af381fda | 194 | // IA32_DESCRIPTOR structure provides the base address and length of an IDT.\r |
fcd92f16 | 195 | // The IDT must be filled in with the IDT contents that are\r |
af381fda MK |
196 | // used during an ACPI S3 resume. This is typically the contents of the IDT\r |
197 | // used by the boot processor when the platform is booted.\r | |
198 | //\r | |
053e878b | 199 | EFI_PHYSICAL_ADDRESS IdtrProfile;\r |
af381fda MK |
200 | //\r |
201 | // Physical address of a buffer that is used as stacks during ACPI S3 resume.\r | |
202 | // The total size of this buffer, in bytes, is NumberOfCpus * StackSize. This\r | |
fcd92f16 | 203 | // structure must be allocated from memory of type EfiACPIMemoryNVS.\r |
af381fda | 204 | //\r |
053e878b | 205 | EFI_PHYSICAL_ADDRESS StackAddress;\r |
af381fda MK |
206 | //\r |
207 | // The size, in bytes, of the stack provided to each CPU during ACPI S3 resume.\r | |
208 | //\r | |
053e878b | 209 | UINT32 StackSize;\r |
af381fda MK |
210 | //\r |
211 | // The number of CPUs. If a platform does not support hot plug CPUs, then\r | |
212 | // this is the number of CPUs detected when the platform is booted, regardless\r | |
213 | // of being enabled or disabled. If a platform does support hot plug CPUs,\r | |
214 | // then this is the maximum number of CPUs that the platform supports.\r | |
215 | //\r | |
053e878b | 216 | UINT32 NumberOfCpus;\r |
af381fda MK |
217 | //\r |
218 | // Physical address of structure of type MTRR_SETTINGS that contains a copy\r | |
219 | // of the MTRR settings that are compatible with the MTRR settings used by\r | |
220 | // the boot processor when the platform was booted. These MTRR settings are\r | |
fcd92f16 | 221 | // used during an ACPI S3 resume.\r |
af381fda | 222 | //\r |
053e878b | 223 | EFI_PHYSICAL_ADDRESS MtrrTable;\r |
1c27f926 | 224 | //\r |
af381fda | 225 | // Physical address of a buffer that contains the machine check handler that\r |
fcd92f16 | 226 | // is used during an ACPI S3 Resume. In order for this machine check\r |
af381fda MK |
227 | // handler to be active on an AP during an ACPI S3 resume, the machine check\r |
228 | // vector in the IDT provided by IdtrProfile must be initialized to transfer\r | |
229 | // control to this physical address.\r | |
230 | //\r | |
053e878b | 231 | EFI_PHYSICAL_ADDRESS ApMachineCheckHandlerBase;\r |
af381fda MK |
232 | //\r |
233 | // The size, in bytes, of the machine check handler that is used during an\r | |
234 | // ACPI S3 Resume. If this field is 0, then a machine check handler is not\r | |
235 | // provided.\r | |
236 | //\r | |
053e878b | 237 | UINT32 ApMachineCheckHandlerSize;\r |
d5aa2078 | 238 | //\r |
010753b7 LY |
239 | // Data structure that is used for CPU feature initialization during ACPI S3\r |
240 | // resume.\r | |
d5aa2078 | 241 | //\r |
053e878b | 242 | CPU_FEATURE_INIT_DATA CpuFeatureInitData;\r |
1c27f926 MK |
243 | } ACPI_CPU_DATA;\r |
244 | \r | |
245 | #endif\r |