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1 | /** @file\r |
2 | The Smm Base HOB is used to store the information of:\r | |
3 | * The relocated SmBase address in array for each processor.\r | |
4 | \r | |
5 | The default Smbase for the x86 processor is 0x30000. When SMI happens, processor\r | |
6 | runs the SMI handler at Smbase+0x8000. Also, the SMM save state area is within\r | |
7 | Smbase+0x10000. Since it's the start address to store the processor save state\r | |
8 | and code for the SMI entry point, those info are tiled within an SMRAM allocated\r | |
9 | or reserved buffer. This tile size shall be enough to cover 3 parts:\r | |
10 | 1. Processor SMRAM Save State Map starts at Smbase + 0xfc00\r | |
11 | 2. Extra processor specific context start starts at Smbase + 0xfb00\r | |
12 | 3. SMI entry point starts at Smbase + 0x8000.\r | |
13 | Besides, This size should be rounded up to nearest power of 2. The Smm Base HOB\r | |
14 | producer should be responsible for reserving enough size.\r | |
15 | \r | |
16 | One of the SMM initialization from processor perspective is to relocate and program\r | |
17 | the new Smbase (in TSEG range) for each processor thread. When the Smbase relocation\r | |
18 | happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB database\r | |
19 | which tells the PiSmmCpuDxeSmm driver (which runs at a later phase) about the new\r | |
20 | Smbase for each processor. PiSmmCpuDxeSmm driver installs the SMI handler at the\r | |
21 | SMM_BASE_HOB.Smbase[Index]+0x8000 for processor index. When the HOB doesn't exist,\r | |
22 | PiSmmCpuDxeSmm driver shall relocate and program the new Smbase itself.\r | |
23 | \r | |
24 | Note:\r | |
25 | 1. Smbase relocation process needs to program the vender specific hardware\r | |
26 | interface to set Smbase, it might be in the thread scope. It's doable to\r | |
27 | program the hardware interface using DXE MP service protocol in PiSmmCpuDxeSmm\r | |
28 | entry point. But, considering the standalone MM environment where the CpuMm\r | |
29 | driver runs in a isolated environment and it cannot invoke any DXE or PEI MP\r | |
30 | service, we recommend to put the hardware interface programming in a separate\r | |
31 | PEI module instead of in the PiSmmCpuDxeSmm driver.\r | |
32 | \r | |
33 | 2. There is the hard requirement that SMI Entry Size <= 0x1000, data Size <=\r | |
34 | 0x1000 in PiSmmCpuDxeSmm. So, this require the allocated or reserved buffer in\r | |
35 | SMRAM should be >= 0x2000.\r | |
36 | \r | |
37 | Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>\r | |
38 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
39 | \r | |
40 | **/\r | |
41 | \r | |
42 | #ifndef SMM_BASE_HOB_H_\r | |
43 | #define SMM_BASE_HOB_H_\r | |
44 | \r | |
45 | #define SMM_BASE_HOB_DATA_GUID \\r | |
46 | { \\r | |
47 | 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73} \\r | |
48 | }\r | |
49 | \r | |
50 | #pragma pack(1)\r | |
51 | typedef struct {\r | |
52 | ///\r | |
53 | /// ProcessorIndex tells which processor range this specific HOB instance described.\r | |
54 | /// If ProcessorIndex is set to 0, it indicats the HOB describes the processor from\r | |
55 | /// 0 to NumberOfProcessors - 1. The HOB list may contains multiple this HOB\r | |
56 | /// instances. Each HOB instances describe the information for processor from\r | |
57 | /// ProcessorIndex to ProcessorIndex + NumberOfProcessors - 1. The instance order in\r | |
58 | /// the HOB list is random so consumer can not assume the ProcessorIndex of first\r | |
59 | /// instance is 0.\r | |
60 | ///\r | |
61 | UINT32 ProcessorIndex;\r | |
62 | ///\r | |
63 | /// Describes the Number of all max supported processors.\r | |
64 | ///\r | |
65 | UINT32 NumberOfProcessors;\r | |
66 | ///\r | |
67 | /// Pointer to SmBase address for each processor.\r | |
68 | ///\r | |
69 | UINT64 SmBase[];\r | |
70 | } SMM_BASE_HOB_DATA;\r | |
71 | #pragma pack()\r | |
72 | \r | |
73 | extern EFI_GUID gSmmBaseHobGuid;\r | |
74 | \r | |
75 | #endif\r |