UefiCpuPkg: Create CpuPageTableLib for manipulating X86 paging structs

[mirror_edk2.git] / UefiCpuPkg / Include / Library / CpuPageTableLib.h

/** @file\r
  Public include file for PageTableLib library.\r
\r
  Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef PAGE_TABLE_LIB_H_\r
#define PAGE_TABLE_LIB_H_\r
\r
typedef union {\r
  struct {\r
    UINT64    Present              : 1; // 0 = Not present in memory, 1 = Present in memory\r
    UINT64    ReadWrite            : 1; // 0 = Read-Only, 1= Read/Write\r
    UINT64    UserSupervisor       : 1; // 0 = Supervisor, 1=User\r
    UINT64    WriteThrough         : 1; // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64    CacheDisabled        : 1; // 0 = Cached, 1=Non-Cached\r
    UINT64    Accessed             : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64    Dirty                : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)\r
    UINT64    Pat                  : 1; // PAT\r
\r
    UINT64    Global               : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)\r
    UINT64    Reserved1            : 3; // Ignored\r
\r
    UINT64    PageTableBaseAddress : 40; // Page Table Base Address\r
    UINT64    Reserved2            : 7;  // Ignored\r
    UINT64    ProtectionKey        : 4;  // Protection key\r
    UINT64    Nx                   : 1;  // No Execute bit\r
  } Bits;\r
  UINT64    Uint64;\r
} IA32_MAP_ATTRIBUTE;\r
\r
#define IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK  0xFFFFFFFFFF000ull\r
#define IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS(pa)  ((pa)->Uint64 & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK)\r
#define IA32_MAP_ATTRIBUTE_ATTRIBUTES(pa)               ((pa)->Uint64 & ~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK)\r
\r
//\r
// Below enum follows "4.1.1 Four Paging Modes" in Chapter 4 Paging of SDM Volume 3.\r
// Page1GB is only supported in 4-level and 5-level.\r
//\r
typedef enum {\r
  Paging32bit,\r
\r
  //\r
  // High byte in paging mode indicates the max levels of the page table.\r
  // Low byte in paging mode indicates the max level that can be a leaf entry.\r
  //\r
  PagingPae = 0x0302,\r
\r
  Paging4Level    = 0x0402,\r
  Paging4Level1GB = 0x0403,\r
\r
  Paging5Level    = 0x0502,\r
  Paging5Level1GB = 0x0503,\r
\r
  PagingModeMax\r
} PAGING_MODE;\r
\r
/**\r
  Create or update page table to map [LinearAddress, LinearAddress + Length) with specified attribute.\r
\r
  @param[in, out] PageTable      The pointer to the page table to update, or pointer to NULL if a new page table is to be created.\r
  @param[in]      PagingMode     The paging mode.\r
  @param[in]      Buffer         The free buffer to be used for page table creation/updating.\r
  @param[in, out] BufferSize     The buffer size.\r
                                 On return, the remaining buffer size.\r
                                 The free buffer is used from the end so caller can supply the same Buffer pointer with an updated\r
                                 BufferSize in the second call to this API.\r
  @param[in]      LinearAddress  The start of the linear address range.\r
  @param[in]      Length         The length of the linear address range.\r
  @param[in]      Attribute      The attribute of the linear address range.\r
                                 All non-reserved fields in IA32_MAP_ATTRIBUTE are supported to set in the page table.\r
                                 Page table entries that map the linear address range are reset to 0 before set to the new attribute\r
                                 when a new physical base address is set.\r
  @param[in]      Mask           The mask used for attribute. The corresponding field in Attribute is ignored if that in Mask is 0.\r
\r
  @retval RETURN_UNSUPPORTED        PagingMode is not supported.\r
  @retval RETURN_INVALID_PARAMETER  PageTable, BufferSize, Attribute or Mask is NULL.\r
  @retval RETURN_INVALID_PARAMETER  *BufferSize is not multiple of 4KB.\r
  @retval RETURN_BUFFER_TOO_SMALL   The buffer is too small for page table creation/updating.\r
                                    BufferSize is updated to indicate the expected buffer size.\r
                                    Caller may still get RETURN_BUFFER_TOO_SMALL with the new BufferSize.\r
  @retval RETURN_SUCCESS            PageTable is created/updated successfully.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PageTableMap (\r
  IN OUT UINTN               *PageTable  OPTIONAL,\r
  IN     PAGING_MODE         PagingMode,\r
  IN     VOID                *Buffer,\r
  IN OUT UINTN               *BufferSize,\r
  IN     UINT64              LinearAddress,\r
  IN     UINT64              Length,\r
  IN     IA32_MAP_ATTRIBUTE  *Attribute,\r
  IN     IA32_MAP_ATTRIBUTE  *Mask\r
  );\r
\r
typedef struct {\r
  UINT64                LinearAddress;\r
  UINT64                Length;\r
  IA32_MAP_ATTRIBUTE    Attribute;\r
} IA32_MAP_ENTRY;\r
\r
/**\r
  Parse page table.\r
\r
  @param[in]      PageTable  Pointer to the page table.\r
  @param[in]      PagingMode The paging mode.\r
  @param[out]     Map        Return an array that describes multiple linear address ranges.\r
  @param[in, out] MapCount   On input, the maximum number of entries that Map can hold.\r
                             On output, the number of entries in Map.\r
\r
  @retval RETURN_UNSUPPORTED       PageLevel is not 5 or 4.\r
  @retval RETURN_INVALID_PARAMETER MapCount is NULL.\r
  @retval RETURN_INVALID_PARAMETER *MapCount is not 0 but Map is NULL.\r
  @retval RETURN_BUFFER_TOO_SMALL  *MapCount is too small.\r
  @retval RETURN_SUCCESS           Page table is parsed successfully.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PageTableParse (\r
  IN     UINTN           PageTable,\r
  IN     PAGING_MODE     PagingMode,\r
  IN     IA32_MAP_ENTRY  *Map,\r
  IN OUT UINTN           *MapCount\r
  );\r
\r
#endif\r