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1 | /** @file\r |
2 | Public include file for PageTableLib library.\r | |
3 | \r | |
4 | Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>\r | |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
6 | \r | |
7 | **/\r | |
8 | \r | |
9 | #ifndef PAGE_TABLE_LIB_H_\r | |
10 | #define PAGE_TABLE_LIB_H_\r | |
11 | \r | |
12 | typedef union {\r | |
13 | struct {\r | |
14 | UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory\r | |
15 | UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write\r | |
16 | UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User\r | |
17 | UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
18 | UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached\r | |
19 | UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
20 | UINT64 Dirty : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)\r | |
21 | UINT64 Pat : 1; // PAT\r | |
22 | \r | |
23 | UINT64 Global : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)\r | |
24 | UINT64 Reserved1 : 3; // Ignored\r | |
25 | \r | |
26 | UINT64 PageTableBaseAddress : 40; // Page Table Base Address\r | |
27 | UINT64 Reserved2 : 7; // Ignored\r | |
28 | UINT64 ProtectionKey : 4; // Protection key\r | |
29 | UINT64 Nx : 1; // No Execute bit\r | |
30 | } Bits;\r | |
31 | UINT64 Uint64;\r | |
32 | } IA32_MAP_ATTRIBUTE;\r | |
33 | \r | |
34 | #define IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK 0xFFFFFFFFFF000ull\r | |
35 | #define IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK)\r | |
36 | #define IA32_MAP_ATTRIBUTE_ATTRIBUTES(pa) ((pa)->Uint64 & ~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK)\r | |
37 | \r | |
38 | //\r | |
39 | // Below enum follows "4.1.1 Four Paging Modes" in Chapter 4 Paging of SDM Volume 3.\r | |
40 | // Page1GB is only supported in 4-level and 5-level.\r | |
41 | //\r | |
42 | typedef enum {\r | |
43 | Paging32bit,\r | |
44 | \r | |
45 | //\r | |
46 | // High byte in paging mode indicates the max levels of the page table.\r | |
47 | // Low byte in paging mode indicates the max level that can be a leaf entry.\r | |
48 | //\r | |
49 | PagingPae = 0x0302,\r | |
50 | \r | |
51 | Paging4Level = 0x0402,\r | |
52 | Paging4Level1GB = 0x0403,\r | |
53 | \r | |
54 | Paging5Level = 0x0502,\r | |
55 | Paging5Level1GB = 0x0503,\r | |
56 | \r | |
57 | PagingModeMax\r | |
58 | } PAGING_MODE;\r | |
59 | \r | |
60 | /**\r | |
61 | Create or update page table to map [LinearAddress, LinearAddress + Length) with specified attribute.\r | |
62 | \r | |
63 | @param[in, out] PageTable The pointer to the page table to update, or pointer to NULL if a new page table is to be created.\r | |
64 | @param[in] PagingMode The paging mode.\r | |
65 | @param[in] Buffer The free buffer to be used for page table creation/updating.\r | |
66 | @param[in, out] BufferSize The buffer size.\r | |
67 | On return, the remaining buffer size.\r | |
68 | The free buffer is used from the end so caller can supply the same Buffer pointer with an updated\r | |
69 | BufferSize in the second call to this API.\r | |
70 | @param[in] LinearAddress The start of the linear address range.\r | |
71 | @param[in] Length The length of the linear address range.\r | |
72 | @param[in] Attribute The attribute of the linear address range.\r | |
73 | All non-reserved fields in IA32_MAP_ATTRIBUTE are supported to set in the page table.\r | |
74 | Page table entries that map the linear address range are reset to 0 before set to the new attribute\r | |
75 | when a new physical base address is set.\r | |
76 | @param[in] Mask The mask used for attribute. The corresponding field in Attribute is ignored if that in Mask is 0.\r | |
77 | \r | |
78 | @retval RETURN_UNSUPPORTED PagingMode is not supported.\r | |
79 | @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Mask is NULL.\r | |
80 | @retval RETURN_INVALID_PARAMETER *BufferSize is not multiple of 4KB.\r | |
81 | @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table creation/updating.\r | |
82 | BufferSize is updated to indicate the expected buffer size.\r | |
83 | Caller may still get RETURN_BUFFER_TOO_SMALL with the new BufferSize.\r | |
84 | @retval RETURN_SUCCESS PageTable is created/updated successfully.\r | |
85 | **/\r | |
86 | RETURN_STATUS\r | |
87 | EFIAPI\r | |
88 | PageTableMap (\r | |
89 | IN OUT UINTN *PageTable OPTIONAL,\r | |
90 | IN PAGING_MODE PagingMode,\r | |
91 | IN VOID *Buffer,\r | |
92 | IN OUT UINTN *BufferSize,\r | |
93 | IN UINT64 LinearAddress,\r | |
94 | IN UINT64 Length,\r | |
95 | IN IA32_MAP_ATTRIBUTE *Attribute,\r | |
96 | IN IA32_MAP_ATTRIBUTE *Mask\r | |
97 | );\r | |
98 | \r | |
99 | typedef struct {\r | |
100 | UINT64 LinearAddress;\r | |
101 | UINT64 Length;\r | |
102 | IA32_MAP_ATTRIBUTE Attribute;\r | |
103 | } IA32_MAP_ENTRY;\r | |
104 | \r | |
105 | /**\r | |
106 | Parse page table.\r | |
107 | \r | |
108 | @param[in] PageTable Pointer to the page table.\r | |
109 | @param[in] PagingMode The paging mode.\r | |
110 | @param[out] Map Return an array that describes multiple linear address ranges.\r | |
111 | @param[in, out] MapCount On input, the maximum number of entries that Map can hold.\r | |
112 | On output, the number of entries in Map.\r | |
113 | \r | |
114 | @retval RETURN_UNSUPPORTED PageLevel is not 5 or 4.\r | |
115 | @retval RETURN_INVALID_PARAMETER MapCount is NULL.\r | |
116 | @retval RETURN_INVALID_PARAMETER *MapCount is not 0 but Map is NULL.\r | |
117 | @retval RETURN_BUFFER_TOO_SMALL *MapCount is too small.\r | |
118 | @retval RETURN_SUCCESS Page table is parsed successfully.\r | |
119 | **/\r | |
120 | RETURN_STATUS\r | |
121 | EFIAPI\r | |
122 | PageTableParse (\r | |
123 | IN UINTN PageTable,\r | |
124 | IN PAGING_MODE PagingMode,\r | |
125 | IN IA32_MAP_ENTRY *Map,\r | |
126 | IN OUT UINTN *MapCount\r | |
127 | );\r | |
128 | \r | |
129 | #endif\r |