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bf73cc4b | 1 | /** @file\r |
2 | IA32 Local APIC Definitions.\r | |
3 | \r | |
d32c7f6c | 4 | Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r |
bf73cc4b | 5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef __LOCAL_APIC_H__\r | |
16 | #define __LOCAL_APIC_H__\r | |
17 | \r | |
18 | //\r | |
19 | // Definitions for IA32 architectural MSRs\r | |
20 | //\r | |
21 | #define MSR_IA32_APIC_BASE_ADDRESS 0x1B\r | |
22 | \r | |
bf73cc4b | 23 | //\r |
24 | // Definition for Local APIC registers and related values\r | |
25 | //\r | |
ae40aef1 | 26 | #define XAPIC_ID_OFFSET 0x20\r |
27 | #define XAPIC_VERSION_OFFSET 0x30\r | |
bf73cc4b | 28 | #define XAPIC_EOI_OFFSET 0x0b0\r |
29 | #define XAPIC_ICR_DFR_OFFSET 0x0e0\r | |
30 | #define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0\r | |
31 | #define XAPIC_ICR_LOW_OFFSET 0x300\r | |
32 | #define XAPIC_ICR_HIGH_OFFSET 0x310\r | |
33 | #define XAPIC_LVT_TIMER_OFFSET 0x320\r | |
ae40aef1 | 34 | #define XAPIC_LVT_LINT0_OFFSET 0x350\r |
35 | #define XAPIC_LVT_LINT1_OFFSET 0x360\r | |
bf73cc4b | 36 | #define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380\r |
37 | #define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390\r | |
38 | #define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0\r | |
39 | \r | |
40 | #define X2APIC_MSR_BASE_ADDRESS 0x800\r | |
41 | #define X2APIC_MSR_ICR_ADDRESS 0x830\r | |
42 | \r | |
43 | #define LOCAL_APIC_DELIVERY_MODE_FIXED 0\r | |
44 | #define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1\r | |
45 | #define LOCAL_APIC_DELIVERY_MODE_SMI 2\r | |
46 | #define LOCAL_APIC_DELIVERY_MODE_NMI 4\r | |
47 | #define LOCAL_APIC_DELIVERY_MODE_INIT 5\r | |
48 | #define LOCAL_APIC_DELIVERY_MODE_STARTUP 6\r | |
49 | #define LOCAL_APIC_DELIVERY_MODE_EXTINT 7\r | |
50 | \r | |
51 | #define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0\r | |
52 | #define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1\r | |
53 | #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r | |
54 | #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r | |
55 | \r | |
56 | typedef union {\r | |
57 | struct {\r | |
23394428 | 58 | UINT32 Reserved0:8; ///< Reserved.\r |
59 | UINT32 Bsp:1; ///< Processor is BSP.\r | |
60 | UINT32 Reserved1:1; ///< Reserved.\r | |
61 | UINT32 Extd:1; ///< Enable x2APIC mode.\r | |
62 | UINT32 En:1; ///< xAPIC global enable/disable.\r | |
63 | UINT32 ApicBaseLow:20; ///< APIC Base physical address. The actual field width depends on physical address width.\r | |
64 | UINT32 ApicBaseHigh:32;\r | |
bf73cc4b | 65 | } Bits;\r |
66 | UINT64 Uint64;\r | |
67 | } MSR_IA32_APIC_BASE;\r | |
68 | \r | |
ae40aef1 | 69 | //\r |
70 | // Local APIC Version Register.\r | |
71 | //\r | |
72 | typedef union {\r | |
73 | struct {\r | |
74 | UINT32 Version:8; ///< The version numbers of the local APIC.\r | |
75 | UINT32 Reserved0:8; ///< Reserved.\r | |
76 | UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.\r | |
77 | UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.\r | |
78 | UINT32 Reserved1:7; ///< Reserved.\r | |
79 | } Bits;\r | |
80 | UINT32 Uint32;\r | |
81 | } LOCAL_APIC_VERSION;\r | |
82 | \r | |
bf73cc4b | 83 | //\r |
84 | // Low half of Interrupt Command Register (ICR).\r | |
85 | //\r | |
86 | typedef union {\r | |
87 | struct {\r | |
88 | UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r | |
89 | UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.\r | |
90 | UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.\r | |
91 | UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.\r | |
92 | UINT32 Reserved0:1; ///< Reserved.\r | |
93 | UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.\r | |
94 | UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.\r | |
95 | UINT32 Reserved1:2; ///< Reserved.\r | |
96 | UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.\r | |
97 | UINT32 Reserved2:12; ///< Reserved.\r | |
98 | } Bits;\r | |
99 | UINT32 Uint32;\r | |
100 | } LOCAL_APIC_ICR_LOW;\r | |
101 | \r | |
102 | //\r | |
103 | // High half of Interrupt Command Register (ICR)\r | |
104 | //\r | |
105 | typedef union {\r | |
106 | struct {\r | |
107 | UINT32 Reserved0:24; ///< Reserved.\r | |
108 | UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.\r | |
109 | } Bits;\r | |
110 | UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.\r | |
111 | } LOCAL_APIC_ICR_HIGH;\r | |
112 | \r | |
113 | //\r | |
114 | // Spurious-Interrupt Vector Register (SVR)\r | |
115 | //\r | |
116 | typedef union {\r | |
117 | struct {\r | |
118 | UINT32 SpuriousVector:8; ///< Spurious Vector.\r | |
119 | UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.\r | |
120 | UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.\r | |
121 | UINT32 Reserved0:2; ///< Reserved.\r | |
122 | UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.\r | |
123 | UINT32 Reserved1:19; ///< Reserved.\r | |
124 | } Bits;\r | |
125 | UINT32 Uint32;\r | |
126 | } LOCAL_APIC_SVR;\r | |
127 | \r | |
128 | //\r | |
129 | // Divide Configuration Register (DCR)\r | |
130 | //\r | |
131 | typedef union {\r | |
132 | struct {\r | |
133 | UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.\r | |
134 | UINT32 Reserved0:1; ///< Always 0.\r | |
135 | UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.\r | |
136 | UINT32 Reserved1:28; ///< Reserved.\r | |
137 | } Bits;\r | |
138 | UINT32 Uint32;\r | |
139 | } LOCAL_APIC_DCR;\r | |
140 | \r | |
141 | //\r | |
142 | // LVT Timer Register\r | |
143 | //\r | |
144 | typedef union {\r | |
145 | struct {\r | |
146 | UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r | |
147 | UINT32 Reserved0:4; ///< Reserved.\r | |
148 | UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r | |
149 | UINT32 Reserved1:3; ///< Reserved.\r | |
150 | UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r | |
151 | UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.\r | |
152 | UINT32 Reserved2:14; ///< Reserved.\r | |
153 | } Bits;\r | |
154 | UINT32 Uint32;\r | |
155 | } LOCAL_APIC_LVT_TIMER;\r | |
156 | \r | |
157 | //\r | |
158 | // LVT LINT0/LINT1 Register\r | |
159 | //\r | |
160 | typedef union {\r | |
161 | struct {\r | |
162 | UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r | |
163 | UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r | |
164 | UINT32 Reserved0:1; ///< Reserved.\r | |
165 | UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r | |
166 | UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.\r | |
167 | UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.\r | |
168 | UINT32 TriggerMode:1; ///< 0:edge, 1:level.\r | |
169 | UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r | |
170 | UINT32 Reserved1:15; ///< Reserved.\r | |
171 | } Bits;\r | |
172 | UINT32 Uint32;\r | |
173 | } LOCAL_APIC_LVT_LINT;\r | |
174 | \r | |
5f867ad0 | 175 | //\r |
176 | // MSI Address Register\r | |
177 | //\r | |
178 | typedef union {\r | |
179 | struct {\r | |
180 | UINT32 Reserved0:2; ///< Reserved\r | |
181 | UINT32 DestinationMode:1; ///< Specifies the Destination Mode.\r | |
182 | UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.\r | |
183 | UINT32 Reserved1:8; ///< Reserved.\r | |
184 | UINT32 DestinationId:8; ///< Specifies the Destination ID.\r | |
185 | UINT32 BaseAddress:12; ///< Must be 0FEEH\r | |
186 | } Bits;\r | |
187 | UINT32 Uint32;\r | |
188 | } LOCAL_APIC_MSI_ADDRESS;\r | |
189 | \r | |
190 | //\r | |
191 | // MSI Address Register\r | |
192 | //\r | |
193 | typedef union {\r | |
194 | struct {\r | |
195 | UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH\r | |
196 | UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r | |
197 | UINT32 Reserved0:3; ///< Reserved.\r | |
198 | UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.\r | |
199 | UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.\r | |
200 | UINT32 Reserved1:16; ///< Reserved.\r | |
201 | UINT32 Reserved2:32; ///< Reserved.\r | |
202 | } Bits;\r | |
203 | UINT64 Uint64;\r | |
204 | } LOCAL_APIC_MSI_DATA;\r | |
205 | \r | |
bf73cc4b | 206 | #endif\r |
207 | \r |