projects / mirror_edk2.git / blame
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| 35fd9411 HW |
1 | /** @file\r |
| 2 | MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| ba1a2d11 | 9 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| 35fd9411 HW |
10 | This program and the accompanying materials\r |
| 11 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 12 | which accompanies this distribution. The full text of the license may be found at\r | |
| 13 | http://opensource.org/licenses/bsd-license.php\r | |
| 14 | \r | |
| 15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 17 | \r | |
| 18 | @par Specification Reference:\r | |
| ba1a2d11 ED |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
| 20 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
| 35fd9411 HW |
21 | \r |
| 22 | **/\r | |
| 23 | \r | |
| 24 | #ifndef __GOLDMONT_MSR_H__\r | |
| 25 | #define __GOLDMONT_MSR_H__\r | |
| 26 | \r | |
| 27 | #include <Register/ArchitecturalMsr.h>\r | |
| 28 | \r | |
| f4c982bf JF |
29 | /**\r |
| 30 | Is Intel Atom processors based on the Goldmont microarchitecture?\r | |
| 31 | \r | |
| 32 | @param DisplayFamily Display Family ID\r | |
| 33 | @param DisplayModel Display Model ID\r | |
| 34 | \r | |
| 35 | @retval TRUE Yes, it is.\r | |
| 36 | @retval FALSE No, it isn't.\r | |
| 37 | **/\r | |
| 38 | #define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
| 39 | (DisplayFamily == 0x06 && \\r | |
| 40 | ( \\r | |
| 41 | DisplayModel == 0x5C \\r | |
| 42 | ) \\r | |
| 43 | )\r | |
| 44 | \r | |
| 35fd9411 HW |
45 | /**\r |
| 46 | Core. Control Features in Intel 64Processor (R/W).\r | |
| 47 | \r | |
| 48 | @param ECX MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A)\r | |
| 49 | @param EAX Lower 32-bits of MSR value.\r | |
| 50 | Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.\r | |
| 51 | @param EDX Upper 32-bits of MSR value.\r | |
| 52 | Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.\r | |
| 53 | \r | |
| 54 | <b>Example usage</b>\r | |
| 55 | @code\r | |
| 56 | MSR_GOLDMONT_FEATURE_CONTROL_REGISTER Msr;\r | |
| 57 | \r | |
| 58 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_FEATURE_CONTROL);\r | |
| 59 | AsmWriteMsr64 (MSR_GOLDMONT_FEATURE_CONTROL, Msr.Uint64);\r | |
| 60 | @endcode\r | |
| 61 | @note MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r | |
| 62 | **/\r | |
| 63 | #define MSR_GOLDMONT_FEATURE_CONTROL 0x0000003A\r | |
| 64 | \r | |
| 65 | /**\r | |
| 66 | MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL\r | |
| 67 | **/\r | |
| 68 | typedef union {\r | |
| 69 | ///\r | |
| 70 | /// Individual bit fields\r | |
| 71 | ///\r | |
| 72 | struct {\r | |
| 73 | ///\r | |
| 74 | /// [Bit 0] Lock bit (R/WL)\r | |
| 75 | ///\r | |
| 76 | UINT32 Lock:1;\r | |
| 77 | ///\r | |
| 78 | /// [Bit 1] Enable VMX inside SMX operation (R/WL)\r | |
| 79 | ///\r | |
| 80 | UINT32 EnableVmxInsideSmx:1;\r | |
| 81 | ///\r | |
| 82 | /// [Bit 2] Enable VMX outside SMX operation (R/WL)\r | |
| 83 | ///\r | |
| 84 | UINT32 EnableVmxOutsideSmx:1;\r | |
| 85 | UINT32 Reserved1:5;\r | |
| 86 | ///\r | |
| 87 | /// [Bits 14:8] SENTER local function enables (R/WL)\r | |
| 88 | ///\r | |
| 89 | UINT32 SenterLocalFunctionEnables:7;\r | |
| 90 | ///\r | |
| 91 | /// [Bit 15] SENTER global functions enable (R/WL)\r | |
| 92 | ///\r | |
| 93 | UINT32 SenterGlobalEnable:1;\r | |
| 94 | UINT32 Reserved2:2;\r | |
| 95 | ///\r | |
| 96 | /// [Bit 18] SGX global functions enable (R/WL)\r | |
| 97 | ///\r | |
| 98 | UINT32 SgxEnable:1;\r | |
| 99 | UINT32 Reserved3:13;\r | |
| 100 | UINT32 Reserved4:32;\r | |
| 101 | } Bits;\r | |
| 102 | ///\r | |
| 103 | /// All bit fields as a 32-bit value\r | |
| 104 | ///\r | |
| 105 | UINT32 Uint32;\r | |
| 106 | ///\r | |
| 107 | /// All bit fields as a 64-bit value\r | |
| 108 | ///\r | |
| 109 | UINT64 Uint64;\r | |
| 110 | } MSR_GOLDMONT_FEATURE_CONTROL_REGISTER;\r | |
| 111 | \r | |
| 112 | \r | |
| 113 | /**\r | |
| 114 | Package. See http://biosbits.org.\r | |
| 115 | \r | |
| 116 | @param ECX MSR_GOLDMONT_PLATFORM_INFO (0x000000CE)\r | |
| 117 | @param EAX Lower 32-bits of MSR value.\r | |
| 118 | Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.\r | |
| 119 | @param EDX Upper 32-bits of MSR value.\r | |
| 120 | Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.\r | |
| 121 | \r | |
| 122 | <b>Example usage</b>\r | |
| 123 | @code\r | |
| 124 | MSR_GOLDMONT_PLATFORM_INFO_REGISTER Msr;\r | |
| 125 | \r | |
| 126 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLATFORM_INFO);\r | |
| 127 | AsmWriteMsr64 (MSR_GOLDMONT_PLATFORM_INFO, Msr.Uint64);\r | |
| 128 | @endcode\r | |
| 129 | @note MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r | |
| 130 | **/\r | |
| 131 | #define MSR_GOLDMONT_PLATFORM_INFO 0x000000CE\r | |
| 132 | \r | |
| 133 | /**\r | |
| 134 | MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO\r | |
| 135 | **/\r | |
| 136 | typedef union {\r | |
| 137 | ///\r | |
| 138 | /// Individual bit fields\r | |
| 139 | ///\r | |
| 140 | struct {\r | |
| 141 | UINT32 Reserved1:8;\r | |
| 142 | ///\r | |
| 143 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r | |
| 144 | /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r | |
| 145 | /// MHz.\r | |
| 146 | ///\r | |
| 147 | UINT32 MaximumNonTurboRatio:8;\r | |
| 148 | UINT32 Reserved2:12;\r | |
| 149 | ///\r | |
| 150 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r | |
| 151 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r | |
| 152 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r | |
| 153 | /// Turbo mode is disabled.\r | |
| 154 | ///\r | |
| 155 | UINT32 RatioLimit:1;\r | |
| 156 | ///\r | |
| 157 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r | |
| 158 | /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r | |
| 159 | /// and when set to 0, indicates TDP Limit for Turbo mode is not\r | |
| 160 | /// programmable.\r | |
| 161 | ///\r | |
| 162 | UINT32 TDPLimit:1;\r | |
| 163 | ///\r | |
| 164 | /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,\r | |
| 165 | /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r | |
| 166 | /// specify an temperature offset.\r | |
| 167 | ///\r | |
| 168 | UINT32 TJOFFSET:1;\r | |
| 169 | UINT32 Reserved3:1;\r | |
| 170 | UINT32 Reserved4:8;\r | |
| 171 | ///\r | |
| 172 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r | |
| 173 | /// minimum ratio (maximum efficiency) that the processor can operates, in\r | |
| 174 | /// units of 100MHz.\r | |
| 175 | ///\r | |
| 176 | UINT32 MaximumEfficiencyRatio:8;\r | |
| 177 | UINT32 Reserved5:16;\r | |
| 178 | } Bits;\r | |
| 179 | ///\r | |
| 180 | /// All bit fields as a 64-bit value\r | |
| 181 | ///\r | |
| 182 | UINT64 Uint64;\r | |
| 183 | } MSR_GOLDMONT_PLATFORM_INFO_REGISTER;\r | |
| 184 | \r | |
| 185 | \r | |
| 186 | /**\r | |
| 187 | Core. C-State Configuration Control (R/W) Note: C-state values are\r | |
| 188 | processor specific C-state code names, unrelated to MWAIT extension C-state\r | |
| 189 | parameters or ACPI CStates. See http://biosbits.org.\r | |
| 190 | \r | |
| 191 | @param ECX MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
| 192 | @param EAX Lower 32-bits of MSR value.\r | |
| 193 | Described by the type\r | |
| 194 | MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 195 | @param EDX Upper 32-bits of MSR value.\r | |
| 196 | Described by the type\r | |
| 197 | MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 198 | \r | |
| 199 | <b>Example usage</b>\r | |
| 200 | @code\r | |
| 201 | MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
| 202 | \r | |
| 203 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL);\r | |
| 204 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
| 205 | @endcode\r | |
| 206 | @note MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r | |
| 207 | **/\r | |
| 208 | #define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
| 209 | \r | |
| 210 | /**\r | |
| 211 | MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL\r | |
| 212 | **/\r | |
| 213 | typedef union {\r | |
| 214 | ///\r | |
| 215 | /// Individual bit fields\r | |
| 216 | ///\r | |
| 217 | struct {\r | |
| 218 | ///\r | |
| 219 | /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r | |
| 220 | /// processor-specific C-state code name (consuming the least power). for\r | |
| 221 | /// the package. The default is set as factory-configured package C-state\r | |
| 222 | /// limit. The following C-state code name encodings are supported: 0000b:\r | |
| 223 | /// No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8\r | |
| 224 | /// 0111b: C9 1000b: C10.\r | |
| 225 | ///\r | |
| 226 | UINT32 Limit:4;\r | |
| 227 | UINT32 Reserved1:6;\r | |
| 228 | ///\r | |
| 229 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r | |
| 230 | /// IO_read instructions sent to IO register specified by\r | |
| 231 | /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r | |
| 232 | ///\r | |
| 233 | UINT32 IO_MWAIT:1;\r | |
| 234 | UINT32 Reserved2:4;\r | |
| 235 | ///\r | |
| 236 | /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r | |
| 237 | /// until next reset.\r | |
| 238 | ///\r | |
| 239 | UINT32 CFGLock:1;\r | |
| 240 | UINT32 Reserved3:16;\r | |
| 241 | UINT32 Reserved4:32;\r | |
| 242 | } Bits;\r | |
| 243 | ///\r | |
| 244 | /// All bit fields as a 32-bit value\r | |
| 245 | ///\r | |
| 246 | UINT32 Uint32;\r | |
| 247 | ///\r | |
| 248 | /// All bit fields as a 64-bit value\r | |
| 249 | ///\r | |
| 250 | UINT64 Uint64;\r | |
| 251 | } MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
| 252 | \r | |
| 253 | \r | |
| 254 | /**\r | |
| 255 | Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement.\r | |
| 256 | Accessible only while in SMM.\r | |
| 257 | \r | |
| 258 | @param ECX MSR_GOLDMONT_SMM_MCA_CAP (0x0000017D)\r | |
| 259 | @param EAX Lower 32-bits of MSR value.\r | |
| 260 | Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.\r | |
| 261 | @param EDX Upper 32-bits of MSR value.\r | |
| 262 | Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.\r | |
| 263 | \r | |
| 264 | <b>Example usage</b>\r | |
| 265 | @code\r | |
| 266 | MSR_GOLDMONT_SMM_MCA_CAP_REGISTER Msr;\r | |
| 267 | \r | |
| 268 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_MCA_CAP);\r | |
| 269 | AsmWriteMsr64 (MSR_GOLDMONT_SMM_MCA_CAP, Msr.Uint64);\r | |
| 270 | @endcode\r | |
| 271 | @note MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r | |
| 272 | **/\r | |
| 273 | #define MSR_GOLDMONT_SMM_MCA_CAP 0x0000017D\r | |
| 274 | \r | |
| 275 | /**\r | |
| 276 | MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP\r | |
| 277 | **/\r | |
| 278 | typedef union {\r | |
| 279 | ///\r | |
| 280 | /// Individual bit fields\r | |
| 281 | ///\r | |
| 282 | struct {\r | |
| 283 | UINT32 Reserved1:32;\r | |
| 284 | UINT32 Reserved2:26;\r | |
| 285 | ///\r | |
| 286 | /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r | |
| 287 | /// SMM code access restriction is supported and the\r | |
| 288 | /// MSR_SMM_FEATURE_CONTROL is supported.\r | |
| 289 | ///\r | |
| 290 | UINT32 SMM_Code_Access_Chk:1;\r | |
| 291 | ///\r | |
| 292 | /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r | |
| 293 | /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is\r | |
| 294 | /// supported.\r | |
| 295 | ///\r | |
| 296 | UINT32 Long_Flow_Indication:1;\r | |
| 297 | UINT32 Reserved3:4;\r | |
| 298 | } Bits;\r | |
| 299 | ///\r | |
| 300 | /// All bit fields as a 64-bit value\r | |
| 301 | ///\r | |
| 302 | UINT64 Uint64;\r | |
| 303 | } MSR_GOLDMONT_SMM_MCA_CAP_REGISTER;\r | |
| 304 | \r | |
| 305 | \r | |
| 306 | /**\r | |
| 307 | Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
| 308 | functions to be enabled and disabled.\r | |
| 309 | \r | |
| 310 | @param ECX MSR_GOLDMONT_IA32_MISC_ENABLE (0x000001A0)\r | |
| 311 | @param EAX Lower 32-bits of MSR value.\r | |
| 312 | Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.\r | |
| 313 | @param EDX Upper 32-bits of MSR value.\r | |
| 314 | Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.\r | |
| 315 | \r | |
| 316 | <b>Example usage</b>\r | |
| 317 | @code\r | |
| 318 | MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER Msr;\r | |
| 319 | \r | |
| 320 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE);\r | |
| 321 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE, Msr.Uint64);\r | |
| 322 | @endcode\r | |
| 323 | @note MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r | |
| 324 | **/\r | |
| 325 | #define MSR_GOLDMONT_IA32_MISC_ENABLE 0x000001A0\r | |
| 326 | \r | |
| 327 | /**\r | |
| 328 | MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE\r | |
| 329 | **/\r | |
| 330 | typedef union {\r | |
| 331 | ///\r | |
| 332 | /// Individual bit fields\r | |
| 333 | ///\r | |
| 334 | struct {\r | |
| 335 | ///\r | |
| ba1a2d11 | 336 | /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.\r |
| 35fd9411 HW |
337 | ///\r |
| 338 | UINT32 FastStrings:1;\r | |
| 339 | UINT32 Reserved1:2;\r | |
| 340 | ///\r | |
| 341 | /// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See\r | |
| ba1a2d11 | 342 | /// Table 2-2. Default value is 1.\r |
| 35fd9411 HW |
343 | ///\r |
| 344 | UINT32 AutomaticThermalControlCircuit:1;\r | |
| 345 | UINT32 Reserved2:3;\r | |
| 346 | ///\r | |
| ba1a2d11 | 347 | /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.\r |
| 35fd9411 HW |
348 | ///\r |
| 349 | UINT32 PerformanceMonitoring:1;\r | |
| 350 | UINT32 Reserved3:3;\r | |
| 351 | ///\r | |
| ba1a2d11 | 352 | /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.\r |
| 35fd9411 HW |
353 | ///\r |
| 354 | UINT32 BTS:1;\r | |
| 355 | ///\r | |
| 356 | /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r | |
| ba1a2d11 | 357 | /// Table 2-2.\r |
| 35fd9411 HW |
358 | ///\r |
| 359 | UINT32 PEBS:1;\r | |
| 360 | UINT32 Reserved4:3;\r | |
| 361 | ///\r | |
| 362 | /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r | |
| ba1a2d11 | 363 | /// Table 2-2.\r |
| 35fd9411 HW |
364 | ///\r |
| 365 | UINT32 EIST:1;\r | |
| 366 | UINT32 Reserved5:1;\r | |
| 367 | ///\r | |
| ba1a2d11 | 368 | /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.\r |
| 35fd9411 HW |
369 | ///\r |
| 370 | UINT32 MONITOR:1;\r | |
| 371 | UINT32 Reserved6:3;\r | |
| 372 | ///\r | |
| ba1a2d11 | 373 | /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.\r |
| 35fd9411 HW |
374 | ///\r |
| 375 | UINT32 LimitCpuidMaxval:1;\r | |
| 376 | ///\r | |
| ba1a2d11 | 377 | /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.\r |
| 35fd9411 HW |
378 | ///\r |
| 379 | UINT32 xTPR_Message_Disable:1;\r | |
| 380 | UINT32 Reserved7:8;\r | |
| 381 | UINT32 Reserved8:2;\r | |
| 382 | ///\r | |
| ba1a2d11 | 383 | /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.\r |
| 35fd9411 HW |
384 | ///\r |
| 385 | UINT32 XD:1;\r | |
| 386 | UINT32 Reserved9:3;\r | |
| 387 | ///\r | |
| 388 | /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r | |
| 389 | /// that support Intel Turbo Boost Technology, the turbo mode feature is\r | |
| 390 | /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r | |
| 391 | /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r | |
| 392 | /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r | |
| 393 | /// the power-on default value is used by BIOS to detect hardware support\r | |
| 394 | /// of turbo mode. If power-on default value is 1, turbo mode is available\r | |
| 395 | /// in the processor. If power-on default value is 0, turbo mode is not\r | |
| 396 | /// available.\r | |
| 397 | ///\r | |
| 398 | UINT32 TurboModeDisable:1;\r | |
| 399 | UINT32 Reserved10:25;\r | |
| 400 | } Bits;\r | |
| 401 | ///\r | |
| 402 | /// All bit fields as a 64-bit value\r | |
| 403 | ///\r | |
| 404 | UINT64 Uint64;\r | |
| 405 | } MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER;\r | |
| 406 | \r | |
| 407 | \r | |
| 408 | /**\r | |
| 409 | Miscellaneous Feature Control (R/W).\r | |
| 410 | \r | |
| 411 | @param ECX MSR_GOLDMONT_MISC_FEATURE_CONTROL (0x000001A4)\r | |
| 412 | @param EAX Lower 32-bits of MSR value.\r | |
| 413 | Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.\r | |
| 414 | @param EDX Upper 32-bits of MSR value.\r | |
| 415 | Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.\r | |
| 416 | \r | |
| 417 | <b>Example usage</b>\r | |
| 418 | @code\r | |
| 419 | MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER Msr;\r | |
| 420 | \r | |
| 421 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL);\r | |
| 422 | AsmWriteMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL, Msr.Uint64);\r | |
| 423 | @endcode\r | |
| 424 | @note MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r | |
| 425 | **/\r | |
| 426 | #define MSR_GOLDMONT_MISC_FEATURE_CONTROL 0x000001A4\r | |
| 427 | \r | |
| 428 | /**\r | |
| 429 | MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL\r | |
| 430 | **/\r | |
| 431 | typedef union {\r | |
| 432 | ///\r | |
| 433 | /// Individual bit fields\r | |
| 434 | ///\r | |
| 435 | struct {\r | |
| 436 | ///\r | |
| 437 | /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r | |
| 438 | /// L2 hardware prefetcher, which fetches additional lines of code or data\r | |
| 439 | /// into the L2 cache.\r | |
| 440 | ///\r | |
| 441 | UINT32 L2HardwarePrefetcherDisable:1;\r | |
| 442 | UINT32 Reserved1:1;\r | |
| 443 | ///\r | |
| 444 | /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r | |
| 445 | /// the L1 data cache prefetcher, which fetches the next cache line into\r | |
| 446 | /// L1 data cache.\r | |
| 447 | ///\r | |
| 448 | UINT32 DCUHardwarePrefetcherDisable:1;\r | |
| 449 | UINT32 Reserved2:29;\r | |
| 450 | UINT32 Reserved3:32;\r | |
| 451 | } Bits;\r | |
| 452 | ///\r | |
| 453 | /// All bit fields as a 32-bit value\r | |
| 454 | ///\r | |
| 455 | UINT32 Uint32;\r | |
| 456 | ///\r | |
| 457 | /// All bit fields as a 64-bit value\r | |
| 458 | ///\r | |
| 459 | UINT64 Uint64;\r | |
| 460 | } MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER;\r | |
| 461 | \r | |
| 462 | \r | |
| 463 | /**\r | |
| 464 | Package. See http://biosbits.org.\r | |
| 465 | \r | |
| 466 | @param ECX MSR_GOLDMONT_MISC_PWR_MGMT (0x000001AA)\r | |
| 467 | @param EAX Lower 32-bits of MSR value.\r | |
| 468 | Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.\r | |
| 469 | @param EDX Upper 32-bits of MSR value.\r | |
| 470 | Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.\r | |
| 471 | \r | |
| 472 | <b>Example usage</b>\r | |
| 473 | @code\r | |
| 474 | MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER Msr;\r | |
| 475 | \r | |
| 476 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT);\r | |
| 477 | AsmWriteMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT, Msr.Uint64);\r | |
| 478 | @endcode\r | |
| 479 | @note MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r | |
| 480 | **/\r | |
| 481 | #define MSR_GOLDMONT_MISC_PWR_MGMT 0x000001AA\r | |
| 482 | \r | |
| 483 | /**\r | |
| 484 | MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT\r | |
| 485 | **/\r | |
| 486 | typedef union {\r | |
| 487 | ///\r | |
| 488 | /// Individual bit fields\r | |
| 489 | ///\r | |
| 490 | struct {\r | |
| 491 | ///\r | |
| 492 | /// [Bit 0] EIST Hardware Coordination Disable (R/W) When 0, enables\r | |
| 493 | /// hardware coordination of Enhanced Intel Speedstep Technology request\r | |
| 494 | /// from processor cores; When 1, disables hardware coordination of\r | |
| 495 | /// Enhanced Intel Speedstep Technology requests.\r | |
| 496 | ///\r | |
| 497 | UINT32 EISTHardwareCoordinationDisable:1;\r | |
| 498 | UINT32 Reserved1:21;\r | |
| 499 | ///\r | |
| 500 | /// [Bit 22] Thermal Interrupt Coordination Enable (R/W) If set, then\r | |
| 501 | /// thermal interrupt on one core is routed to all cores.\r | |
| 502 | ///\r | |
| 503 | UINT32 ThermalInterruptCoordinationEnable:1;\r | |
| 504 | UINT32 Reserved2:9;\r | |
| 505 | UINT32 Reserved3:32;\r | |
| 506 | } Bits;\r | |
| 507 | ///\r | |
| 508 | /// All bit fields as a 32-bit value\r | |
| 509 | ///\r | |
| 510 | UINT32 Uint32;\r | |
| 511 | ///\r | |
| 512 | /// All bit fields as a 64-bit value\r | |
| 513 | ///\r | |
| 514 | UINT64 Uint64;\r | |
| 515 | } MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER;\r | |
| 516 | \r | |
| 517 | \r | |
| 518 | /**\r | |
| 519 | Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies\r | |
| 520 | Maximum Ratio Limit for each Core Group. Max ratio for groups with more\r | |
| 521 | cores must decrease monotonically. For groups with less than 4 cores, the\r | |
| 522 | max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must\r | |
| 523 | be 22 or less. For groups with more than 5 cores, the max ratio must be 16\r | |
| 524 | or less..\r | |
| 525 | \r | |
| 526 | @param ECX MSR_GOLDMONT_TURBO_RATIO_LIMIT (0x000001AD)\r | |
| 527 | @param EAX Lower 32-bits of MSR value.\r | |
| 528 | Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 529 | @param EDX Upper 32-bits of MSR value.\r | |
| 530 | Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 531 | \r | |
| 532 | <b>Example usage</b>\r | |
| 533 | @code\r | |
| 534 | MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
| 535 | \r | |
| 536 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT);\r | |
| 537 | AsmWriteMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT, Msr.Uint64);\r | |
| 538 | @endcode\r | |
| 539 | @note MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r | |
| 540 | **/\r | |
| 541 | #define MSR_GOLDMONT_TURBO_RATIO_LIMIT 0x000001AD\r | |
| 542 | \r | |
| 543 | /**\r | |
| 544 | MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT\r | |
| 545 | **/\r | |
| 546 | typedef union {\r | |
| 547 | ///\r | |
| 548 | /// Individual bit fields\r | |
| 549 | ///\r | |
| 550 | struct {\r | |
| 551 | ///\r | |
| 552 | /// [Bits 7:0] Package. Maximum Ratio Limit for Active cores in Group 0\r | |
| 553 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
| 554 | /// to Group 0 threshold.\r | |
| 555 | ///\r | |
| 556 | UINT32 MaxRatioLimitGroup0:8;\r | |
| 557 | ///\r | |
| 558 | /// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1\r | |
| 559 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
| 560 | /// to Group 1 threshold and greater than Group 0 threshold.\r | |
| 561 | ///\r | |
| 562 | UINT32 MaxRatioLimitGroup1:8;\r | |
| 563 | ///\r | |
| 564 | /// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2\r | |
| 565 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
| 566 | /// to Group 2 threshold and greater than Group 1 threshold.\r | |
| 567 | ///\r | |
| 568 | UINT32 MaxRatioLimitGroup2:8;\r | |
| 569 | ///\r | |
| 570 | /// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3\r | |
| 571 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
| 572 | /// to Group 3 threshold and greater than Group 2 threshold.\r | |
| 573 | ///\r | |
| 574 | UINT32 MaxRatioLimitGroup3:8;\r | |
| 575 | ///\r | |
| 576 | /// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4\r | |
| 577 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
| 578 | /// to Group 4 threshold and greater than Group 3 threshold.\r | |
| 579 | ///\r | |
| 580 | UINT32 MaxRatioLimitGroup4:8;\r | |
| 581 | ///\r | |
| 582 | /// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5\r | |
| 583 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
| 584 | /// to Group 5 threshold and greater than Group 4 threshold.\r | |
| 585 | ///\r | |
| 586 | UINT32 MaxRatioLimitGroup5:8;\r | |
| 587 | ///\r | |
| 588 | /// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6\r | |
| 589 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
| 590 | /// to Group 6 threshold and greater than Group 5 threshold.\r | |
| 591 | ///\r | |
| 592 | UINT32 MaxRatioLimitGroup6:8;\r | |
| 593 | ///\r | |
| 594 | /// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7\r | |
| 595 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
| 596 | /// to Group 7 threshold and greater than Group 6 threshold.\r | |
| 597 | ///\r | |
| 598 | UINT32 MaxRatioLimitGroup7:8;\r | |
| 599 | } Bits;\r | |
| 600 | ///\r | |
| 601 | /// All bit fields as a 64-bit value\r | |
| 602 | ///\r | |
| 603 | UINT64 Uint64;\r | |
| 604 | } MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER;\r | |
| 605 | \r | |
| 606 | \r | |
| 607 | /**\r | |
| 608 | Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of\r | |
| 609 | 0 threshold is ignored.\r | |
| 610 | \r | |
| 611 | @param ECX MSR_GOLDMONT_TURBO_GROUP_CORECNT (0x000001AE)\r | |
| 612 | @param EAX Lower 32-bits of MSR value.\r | |
| 613 | Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.\r | |
| 614 | @param EDX Upper 32-bits of MSR value.\r | |
| 615 | Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.\r | |
| 616 | \r | |
| 617 | <b>Example usage</b>\r | |
| 618 | @code\r | |
| 619 | MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER Msr;\r | |
| 620 | \r | |
| 621 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT);\r | |
| 622 | AsmWriteMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT, Msr.Uint64);\r | |
| 623 | @endcode\r | |
| 624 | @note MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM.\r | |
| 625 | **/\r | |
| 626 | #define MSR_GOLDMONT_TURBO_GROUP_CORECNT 0x000001AE\r | |
| 627 | \r | |
| 628 | /**\r | |
| 629 | MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT\r | |
| 630 | **/\r | |
| 631 | typedef union {\r | |
| 632 | ///\r | |
| 633 | /// Individual bit fields\r | |
| 634 | ///\r | |
| 635 | struct {\r | |
| 636 | ///\r | |
| 637 | /// [Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of\r | |
| 638 | /// active cores to operate under Group 0 Max Turbo Ratio limit.\r | |
| 639 | ///\r | |
| 640 | UINT32 CoreCountThresholdGroup0:8;\r | |
| 641 | ///\r | |
| 642 | /// [Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of\r | |
| 643 | /// active cores to operate under Group 1 Max Turbo Ratio limit. Must be\r | |
| 644 | /// greater than Group 0 Core Count.\r | |
| 645 | ///\r | |
| 646 | UINT32 CoreCountThresholdGroup1:8;\r | |
| 647 | ///\r | |
| 648 | /// [Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of\r | |
| 649 | /// active cores to operate under Group 2 Max Turbo Ratio limit. Must be\r | |
| 650 | /// greater than Group 1 Core Count.\r | |
| 651 | ///\r | |
| 652 | UINT32 CoreCountThresholdGroup2:8;\r | |
| 653 | ///\r | |
| 654 | /// [Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of\r | |
| 655 | /// active cores to operate under Group 3 Max Turbo Ratio limit. Must be\r | |
| 656 | /// greater than Group 2 Core Count.\r | |
| 657 | ///\r | |
| 658 | UINT32 CoreCountThresholdGroup3:8;\r | |
| 659 | ///\r | |
| 660 | /// [Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of\r | |
| 661 | /// active cores to operate under Group 4 Max Turbo Ratio limit. Must be\r | |
| 662 | /// greater than Group 3 Core Count.\r | |
| 663 | ///\r | |
| 664 | UINT32 CoreCountThresholdGroup4:8;\r | |
| 665 | ///\r | |
| 666 | /// [Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of\r | |
| 667 | /// active cores to operate under Group 5 Max Turbo Ratio limit. Must be\r | |
| 668 | /// greater than Group 4 Core Count.\r | |
| 669 | ///\r | |
| 670 | UINT32 CoreCountThresholdGroup5:8;\r | |
| 671 | ///\r | |
| 672 | /// [Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of\r | |
| 673 | /// active cores to operate under Group 6 Max Turbo Ratio limit. Must be\r | |
| 674 | /// greater than Group 5 Core Count.\r | |
| 675 | ///\r | |
| 676 | UINT32 CoreCountThresholdGroup6:8;\r | |
| 677 | ///\r | |
| 678 | /// [Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of\r | |
| 679 | /// active cores to operate under Group 7 Max Turbo Ratio limit. Must be\r | |
| 680 | /// greater than Group 6 Core Count and not less than the total number of\r | |
| 681 | /// processor cores in the package. E.g. specify 255.\r | |
| 682 | ///\r | |
| 683 | UINT32 CoreCountThresholdGroup7:8;\r | |
| 684 | } Bits;\r | |
| 685 | ///\r | |
| 686 | /// All bit fields as a 64-bit value\r | |
| 687 | ///\r | |
| 688 | UINT64 Uint64;\r | |
| 689 | } MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER;\r | |
| 690 | \r | |
| 691 | \r | |
| 692 | /**\r | |
| ba1a2d11 ED |
693 | Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r |
| 694 | "Filtering of Last Branch Records.".\r | |
| 35fd9411 HW |
695 | \r |
| 696 | @param ECX MSR_GOLDMONT_LBR_SELECT (0x000001C8)\r | |
| 697 | @param EAX Lower 32-bits of MSR value.\r | |
| 698 | Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.\r | |
| 699 | @param EDX Upper 32-bits of MSR value.\r | |
| 700 | Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.\r | |
| 701 | \r | |
| 702 | <b>Example usage</b>\r | |
| 703 | @code\r | |
| 704 | MSR_GOLDMONT_LBR_SELECT_REGISTER Msr;\r | |
| 705 | \r | |
| 706 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LBR_SELECT);\r | |
| 707 | AsmWriteMsr64 (MSR_GOLDMONT_LBR_SELECT, Msr.Uint64);\r | |
| 708 | @endcode\r | |
| 709 | @note MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r | |
| 710 | **/\r | |
| 711 | #define MSR_GOLDMONT_LBR_SELECT 0x000001C8\r | |
| 712 | \r | |
| 713 | /**\r | |
| 714 | MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT\r | |
| 715 | **/\r | |
| 716 | typedef union {\r | |
| 717 | ///\r | |
| 718 | /// Individual bit fields\r | |
| 719 | ///\r | |
| 720 | struct {\r | |
| 721 | ///\r | |
| 722 | /// [Bit 0] CPL_EQ_0.\r | |
| 723 | ///\r | |
| 724 | UINT32 CPL_EQ_0:1;\r | |
| 725 | ///\r | |
| 726 | /// [Bit 1] CPL_NEQ_0.\r | |
| 727 | ///\r | |
| 728 | UINT32 CPL_NEQ_0:1;\r | |
| 729 | ///\r | |
| 730 | /// [Bit 2] JCC.\r | |
| 731 | ///\r | |
| 732 | UINT32 JCC:1;\r | |
| 733 | ///\r | |
| 734 | /// [Bit 3] NEAR_REL_CALL.\r | |
| 735 | ///\r | |
| 736 | UINT32 NEAR_REL_CALL:1;\r | |
| 737 | ///\r | |
| 738 | /// [Bit 4] NEAR_IND_CALL.\r | |
| 739 | ///\r | |
| 740 | UINT32 NEAR_IND_CALL:1;\r | |
| 741 | ///\r | |
| 742 | /// [Bit 5] NEAR_RET.\r | |
| 743 | ///\r | |
| 744 | UINT32 NEAR_RET:1;\r | |
| 745 | ///\r | |
| 746 | /// [Bit 6] NEAR_IND_JMP.\r | |
| 747 | ///\r | |
| 748 | UINT32 NEAR_IND_JMP:1;\r | |
| 749 | ///\r | |
| 750 | /// [Bit 7] NEAR_REL_JMP.\r | |
| 751 | ///\r | |
| 752 | UINT32 NEAR_REL_JMP:1;\r | |
| 753 | ///\r | |
| 754 | /// [Bit 8] FAR_BRANCH.\r | |
| 755 | ///\r | |
| 756 | UINT32 FAR_BRANCH:1;\r | |
| 757 | ///\r | |
| 758 | /// [Bit 9] EN_CALL_STACK.\r | |
| 759 | ///\r | |
| 760 | UINT32 EN_CALL_STACK:1;\r | |
| 761 | UINT32 Reserved1:22;\r | |
| 762 | UINT32 Reserved2:32;\r | |
| 763 | } Bits;\r | |
| 764 | ///\r | |
| 765 | /// All bit fields as a 32-bit value\r | |
| 766 | ///\r | |
| 767 | UINT32 Uint32;\r | |
| 768 | ///\r | |
| 769 | /// All bit fields as a 64-bit value\r | |
| 770 | ///\r | |
| 771 | UINT64 Uint64;\r | |
| 772 | } MSR_GOLDMONT_LBR_SELECT_REGISTER;\r | |
| 773 | \r | |
| 774 | \r | |
| 775 | /**\r | |
| 776 | Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that\r | |
| 777 | points to the MSR containing the most recent branch record. See\r | |
| 778 | MSR_LASTBRANCH_0_FROM_IP.\r | |
| 779 | \r | |
| 780 | @param ECX MSR_GOLDMONT_LASTBRANCH_TOS (0x000001C9)\r | |
| 781 | @param EAX Lower 32-bits of MSR value.\r | |
| 782 | @param EDX Upper 32-bits of MSR value.\r | |
| 783 | \r | |
| 784 | <b>Example usage</b>\r | |
| 785 | @code\r | |
| 786 | UINT64 Msr;\r | |
| 787 | \r | |
| 788 | Msr = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS);\r | |
| 789 | AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS, Msr);\r | |
| 790 | @endcode\r | |
| 791 | @note MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r | |
| 792 | **/\r | |
| 793 | #define MSR_GOLDMONT_LASTBRANCH_TOS 0x000001C9\r | |
| 794 | \r | |
| 795 | \r | |
| 796 | /**\r | |
| 797 | Core. Power Control Register. See http://biosbits.org.\r | |
| 798 | \r | |
| 799 | @param ECX MSR_GOLDMONT_POWER_CTL (0x000001FC)\r | |
| 800 | @param EAX Lower 32-bits of MSR value.\r | |
| 801 | Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.\r | |
| 802 | @param EDX Upper 32-bits of MSR value.\r | |
| 803 | Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.\r | |
| 804 | \r | |
| 805 | <b>Example usage</b>\r | |
| 806 | @code\r | |
| 807 | MSR_GOLDMONT_POWER_CTL_REGISTER Msr;\r | |
| 808 | \r | |
| 809 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_POWER_CTL);\r | |
| 810 | AsmWriteMsr64 (MSR_GOLDMONT_POWER_CTL, Msr.Uint64);\r | |
| 811 | @endcode\r | |
| 812 | @note MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r | |
| 813 | **/\r | |
| 814 | #define MSR_GOLDMONT_POWER_CTL 0x000001FC\r | |
| 815 | \r | |
| 816 | /**\r | |
| 817 | MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL\r | |
| 818 | **/\r | |
| 819 | typedef union {\r | |
| 820 | ///\r | |
| 821 | /// Individual bit fields\r | |
| 822 | ///\r | |
| 823 | struct {\r | |
| 824 | UINT32 Reserved1:1;\r | |
| 825 | ///\r | |
| 826 | /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the\r | |
| 827 | /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology\r | |
| 828 | /// operating point when all execution cores enter MWAIT (C1).\r | |
| 829 | ///\r | |
| 830 | UINT32 C1EEnable:1;\r | |
| 831 | UINT32 Reserved2:30;\r | |
| 832 | UINT32 Reserved3:32;\r | |
| 833 | } Bits;\r | |
| 834 | ///\r | |
| 835 | /// All bit fields as a 32-bit value\r | |
| 836 | ///\r | |
| 837 | UINT32 Uint32;\r | |
| 838 | ///\r | |
| 839 | /// All bit fields as a 64-bit value\r | |
| 840 | ///\r | |
| 841 | UINT64 Uint64;\r | |
| 842 | } MSR_GOLDMONT_POWER_CTL_REGISTER;\r | |
| 843 | \r | |
| 844 | \r | |
| 845 | /**\r | |
| 140d7131 ED |
846 | Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r |
| 847 | CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r | |
| 848 | the package. Lower 64 bits of an 128-bit external entropy value for key\r | |
| 849 | derivation of an enclave.\r | |
| 35fd9411 | 850 | \r |
| 140d7131 | 851 | @param ECX MSR_GOLDMONT_SGXOWNEREPOCH0 (0x00000300)\r |
| 35fd9411 HW |
852 | @param EAX Lower 32-bits of MSR value.\r |
| 853 | @param EDX Upper 32-bits of MSR value.\r | |
| 854 | \r | |
| 855 | <b>Example usage</b>\r | |
| 856 | @code\r | |
| 857 | UINT64 Msr;\r | |
| 858 | \r | |
| 140d7131 | 859 | Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0);\r |
| 35fd9411 | 860 | @endcode\r |
| 140d7131 | 861 | @note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.\r |
| 35fd9411 | 862 | **/\r |
| 140d7131 ED |
863 | #define MSR_GOLDMONT_SGXOWNEREPOCH0 0x00000300\r |
| 864 | \r | |
| 865 | \r | |
| 866 | //\r | |
| 867 | // Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM.\r | |
| 868 | //\r | |
| 869 | #define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0\r | |
| 35fd9411 HW |
870 | \r |
| 871 | \r | |
| 872 | /**\r | |
| 873 | Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of\r | |
| 874 | an 128-bit external entropy value for key derivation of an enclave.\r | |
| 875 | \r | |
| 140d7131 | 876 | @param ECX MSR_GOLDMONT_SGXOWNEREPOCH1 (0x00000301)\r |
| 35fd9411 HW |
877 | @param EAX Lower 32-bits of MSR value.\r |
| 878 | @param EDX Upper 32-bits of MSR value.\r | |
| 879 | \r | |
| 880 | <b>Example usage</b>\r | |
| 881 | @code\r | |
| 882 | UINT64 Msr;\r | |
| 883 | \r | |
| 140d7131 | 884 | Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1);\r |
| 35fd9411 | 885 | @endcode\r |
| 140d7131 | 886 | @note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.\r |
| 35fd9411 | 887 | **/\r |
| 140d7131 ED |
888 | #define MSR_GOLDMONT_SGXOWNEREPOCH1 0x00000301\r |
| 889 | \r | |
| 890 | \r | |
| 891 | //\r | |
| 892 | // Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM.\r | |
| 893 | //\r | |
| 894 | #define MSR_GOLDMONT_SGXOWNER1 MSR_GOLDMONT_SGXOWNEREPOCH1\r | |
| 35fd9411 HW |
895 | \r |
| 896 | \r | |
| 897 | /**\r | |
| ba1a2d11 | 898 | Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r |
| 35fd9411 HW |
899 | Monitoring Version 4.".\r |
| 900 | \r | |
| 901 | @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r | |
| 902 | @param EAX Lower 32-bits of MSR value.\r | |
| 903 | Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
| 904 | @param EDX Upper 32-bits of MSR value.\r | |
| 905 | Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
| 906 | \r | |
| 907 | <b>Example usage</b>\r | |
| 908 | @code\r | |
| 909 | MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r | |
| 910 | \r | |
| 911 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET);\r | |
| 912 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r | |
| 913 | @endcode\r | |
| 914 | @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r | |
| 915 | **/\r | |
| 916 | #define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r | |
| 917 | \r | |
| 918 | /**\r | |
| 919 | MSR information returned for MSR index\r | |
| 920 | #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET\r | |
| 921 | **/\r | |
| 922 | typedef union {\r | |
| 923 | ///\r | |
| 924 | /// Individual bit fields\r | |
| 925 | ///\r | |
| 926 | struct {\r | |
| 927 | ///\r | |
| 928 | /// [Bit 0] Set 1 to clear Ovf_PMC0.\r | |
| 929 | ///\r | |
| 930 | UINT32 Ovf_PMC0:1;\r | |
| 931 | ///\r | |
| 932 | /// [Bit 1] Set 1 to clear Ovf_PMC1.\r | |
| 933 | ///\r | |
| 934 | UINT32 Ovf_PMC1:1;\r | |
| 935 | ///\r | |
| 936 | /// [Bit 2] Set 1 to clear Ovf_PMC2.\r | |
| 937 | ///\r | |
| 938 | UINT32 Ovf_PMC2:1;\r | |
| 939 | ///\r | |
| 940 | /// [Bit 3] Set 1 to clear Ovf_PMC3.\r | |
| 941 | ///\r | |
| 942 | UINT32 Ovf_PMC3:1;\r | |
| 943 | UINT32 Reserved1:28;\r | |
| 944 | ///\r | |
| 945 | /// [Bit 32] Set 1 to clear Ovf_FixedCtr0.\r | |
| 946 | ///\r | |
| 947 | UINT32 Ovf_FixedCtr0:1;\r | |
| 948 | ///\r | |
| 949 | /// [Bit 33] Set 1 to clear Ovf_FixedCtr1.\r | |
| 950 | ///\r | |
| 951 | UINT32 Ovf_FixedCtr1:1;\r | |
| 952 | ///\r | |
| 953 | /// [Bit 34] Set 1 to clear Ovf_FixedCtr2.\r | |
| 954 | ///\r | |
| 955 | UINT32 Ovf_FixedCtr2:1;\r | |
| 956 | UINT32 Reserved2:20;\r | |
| 957 | ///\r | |
| 958 | /// [Bit 55] Set 1 to clear Trace_ToPA_PMI.\r | |
| 959 | ///\r | |
| 960 | UINT32 Trace_ToPA_PMI:1;\r | |
| 961 | UINT32 Reserved3:2;\r | |
| 962 | ///\r | |
| 963 | /// [Bit 58] Set 1 to clear LBR_Frz.\r | |
| 964 | ///\r | |
| 965 | UINT32 LBR_Frz:1;\r | |
| 966 | ///\r | |
| 967 | /// [Bit 59] Set 1 to clear CTR_Frz.\r | |
| 968 | ///\r | |
| 969 | UINT32 CTR_Frz:1;\r | |
| 970 | ///\r | |
| 971 | /// [Bit 60] Set 1 to clear ASCI.\r | |
| 972 | ///\r | |
| 973 | UINT32 ASCI:1;\r | |
| 974 | ///\r | |
| 975 | /// [Bit 61] Set 1 to clear Ovf_Uncore.\r | |
| 976 | ///\r | |
| 977 | UINT32 Ovf_Uncore:1;\r | |
| 978 | ///\r | |
| 979 | /// [Bit 62] Set 1 to clear Ovf_BufDSSAVE.\r | |
| 980 | ///\r | |
| 981 | UINT32 Ovf_BufDSSAVE:1;\r | |
| 982 | ///\r | |
| 983 | /// [Bit 63] Set 1 to clear CondChgd.\r | |
| 984 | ///\r | |
| 985 | UINT32 CondChgd:1;\r | |
| 986 | } Bits;\r | |
| 987 | ///\r | |
| 988 | /// All bit fields as a 64-bit value\r | |
| 989 | ///\r | |
| 990 | UINT64 Uint64;\r | |
| 991 | } MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r | |
| 992 | \r | |
| 993 | \r | |
| 994 | /**\r | |
| ba1a2d11 | 995 | Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r |
| 35fd9411 HW |
996 | Monitoring Version 4.".\r |
| 997 | \r | |
| 998 | @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r | |
| 999 | @param EAX Lower 32-bits of MSR value.\r | |
| 1000 | Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
| 1001 | @param EDX Upper 32-bits of MSR value.\r | |
| 1002 | Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
| 1003 | \r | |
| 1004 | <b>Example usage</b>\r | |
| 1005 | @code\r | |
| 1006 | MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r | |
| 1007 | \r | |
| 1008 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET);\r | |
| 1009 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r | |
| 1010 | @endcode\r | |
| 1011 | @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r | |
| 1012 | **/\r | |
| 1013 | #define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r | |
| 1014 | \r | |
| 1015 | /**\r | |
| 1016 | MSR information returned for MSR index\r | |
| 1017 | #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET\r | |
| 1018 | **/\r | |
| 1019 | typedef union {\r | |
| 1020 | ///\r | |
| 1021 | /// Individual bit fields\r | |
| 1022 | ///\r | |
| 1023 | struct {\r | |
| 1024 | ///\r | |
| 1025 | /// [Bit 0] Set 1 to cause Ovf_PMC0 = 1.\r | |
| 1026 | ///\r | |
| 1027 | UINT32 Ovf_PMC0:1;\r | |
| 1028 | ///\r | |
| 1029 | /// [Bit 1] Set 1 to cause Ovf_PMC1 = 1.\r | |
| 1030 | ///\r | |
| 1031 | UINT32 Ovf_PMC1:1;\r | |
| 1032 | ///\r | |
| 1033 | /// [Bit 2] Set 1 to cause Ovf_PMC2 = 1.\r | |
| 1034 | ///\r | |
| 1035 | UINT32 Ovf_PMC2:1;\r | |
| 1036 | ///\r | |
| 1037 | /// [Bit 3] Set 1 to cause Ovf_PMC3 = 1.\r | |
| 1038 | ///\r | |
| 1039 | UINT32 Ovf_PMC3:1;\r | |
| 1040 | UINT32 Reserved1:28;\r | |
| 1041 | ///\r | |
| 1042 | /// [Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1.\r | |
| 1043 | ///\r | |
| 1044 | UINT32 Ovf_FixedCtr0:1;\r | |
| 1045 | ///\r | |
| 1046 | /// [Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1.\r | |
| 1047 | ///\r | |
| 1048 | UINT32 Ovf_FixedCtr1:1;\r | |
| 1049 | ///\r | |
| 1050 | /// [Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1.\r | |
| 1051 | ///\r | |
| 1052 | UINT32 Ovf_FixedCtr2:1;\r | |
| 1053 | UINT32 Reserved2:20;\r | |
| 1054 | ///\r | |
| 1055 | /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1.\r | |
| 1056 | ///\r | |
| 1057 | UINT32 Trace_ToPA_PMI:1;\r | |
| 1058 | UINT32 Reserved3:2;\r | |
| 1059 | ///\r | |
| 1060 | /// [Bit 58] Set 1 to cause LBR_Frz = 1.\r | |
| 1061 | ///\r | |
| 1062 | UINT32 LBR_Frz:1;\r | |
| 1063 | ///\r | |
| 1064 | /// [Bit 59] Set 1 to cause CTR_Frz = 1.\r | |
| 1065 | ///\r | |
| 1066 | UINT32 CTR_Frz:1;\r | |
| 1067 | ///\r | |
| 1068 | /// [Bit 60] Set 1 to cause ASCI = 1.\r | |
| 1069 | ///\r | |
| 1070 | UINT32 ASCI:1;\r | |
| 1071 | ///\r | |
| 1072 | /// [Bit 61] Set 1 to cause Ovf_Uncore.\r | |
| 1073 | ///\r | |
| 1074 | UINT32 Ovf_Uncore:1;\r | |
| 1075 | ///\r | |
| 1076 | /// [Bit 62] Set 1 to cause Ovf_BufDSSAVE.\r | |
| 1077 | ///\r | |
| 1078 | UINT32 Ovf_BufDSSAVE:1;\r | |
| 1079 | UINT32 Reserved4:1;\r | |
| 1080 | } Bits;\r | |
| 1081 | ///\r | |
| 1082 | /// All bit fields as a 64-bit value\r | |
| 1083 | ///\r | |
| 1084 | UINT64 Uint64;\r | |
| 1085 | } MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r | |
| 1086 | \r | |
| 1087 | \r | |
| 1088 | /**\r | |
| ba1a2d11 | 1089 | Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r |
| 35fd9411 HW |
1090 | (PEBS).".\r |
| 1091 | \r | |
| 1092 | @param ECX MSR_GOLDMONT_PEBS_ENABLE (0x000003F1)\r | |
| 1093 | @param EAX Lower 32-bits of MSR value.\r | |
| 1094 | Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.\r | |
| 1095 | @param EDX Upper 32-bits of MSR value.\r | |
| 1096 | Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.\r | |
| 1097 | \r | |
| 1098 | <b>Example usage</b>\r | |
| 1099 | @code\r | |
| 1100 | MSR_GOLDMONT_PEBS_ENABLE_REGISTER Msr;\r | |
| 1101 | \r | |
| 1102 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PEBS_ENABLE);\r | |
| 1103 | AsmWriteMsr64 (MSR_GOLDMONT_PEBS_ENABLE, Msr.Uint64);\r | |
| 1104 | @endcode\r | |
| 1105 | @note MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r | |
| 1106 | **/\r | |
| 1107 | #define MSR_GOLDMONT_PEBS_ENABLE 0x000003F1\r | |
| 1108 | \r | |
| 1109 | /**\r | |
| 1110 | MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE\r | |
| 1111 | **/\r | |
| 1112 | typedef union {\r | |
| 1113 | ///\r | |
| 1114 | /// Individual bit fields\r | |
| 1115 | ///\r | |
| 1116 | struct {\r | |
| 1117 | ///\r | |
| 1118 | /// [Bit 0] Enable PEBS trigger and recording for the programmed event\r | |
| 1119 | /// (precise or otherwise) on IA32_PMC0. (R/W).\r | |
| 1120 | ///\r | |
| 1121 | UINT32 Enable:1;\r | |
| 1122 | UINT32 Reserved1:31;\r | |
| 1123 | UINT32 Reserved2:32;\r | |
| 1124 | } Bits;\r | |
| 1125 | ///\r | |
| 1126 | /// All bit fields as a 32-bit value\r | |
| 1127 | ///\r | |
| 1128 | UINT32 Uint32;\r | |
| 1129 | ///\r | |
| 1130 | /// All bit fields as a 64-bit value\r | |
| 1131 | ///\r | |
| 1132 | UINT64 Uint64;\r | |
| 1133 | } MSR_GOLDMONT_PEBS_ENABLE_REGISTER;\r | |
| 1134 | \r | |
| 1135 | \r | |
| 1136 | /**\r | |
| 1137 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 1138 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r | |
| 1139 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
| 1140 | processor-specific C3 states. Count at the same frequency as the TSC.\r | |
| 1141 | \r | |
| 1142 | @param ECX MSR_GOLDMONT_PKG_C3_RESIDENCY (0x000003F8)\r | |
| 1143 | @param EAX Lower 32-bits of MSR value.\r | |
| 1144 | @param EDX Upper 32-bits of MSR value.\r | |
| 1145 | \r | |
| 1146 | <b>Example usage</b>\r | |
| 1147 | @code\r | |
| 1148 | UINT64 Msr;\r | |
| 1149 | \r | |
| 1150 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY);\r | |
| 1151 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY, Msr);\r | |
| 1152 | @endcode\r | |
| 1153 | @note MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r | |
| 1154 | **/\r | |
| 1155 | #define MSR_GOLDMONT_PKG_C3_RESIDENCY 0x000003F8\r | |
| 1156 | \r | |
| 1157 | \r | |
| 1158 | /**\r | |
| 1159 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 1160 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r | |
| 1161 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
| 1162 | processor-specific C6 states. Count at the same frequency as the TSC.\r | |
| 1163 | \r | |
| 1164 | @param ECX MSR_GOLDMONT_PKG_C6_RESIDENCY (0x000003F9)\r | |
| 1165 | @param EAX Lower 32-bits of MSR value.\r | |
| 1166 | @param EDX Upper 32-bits of MSR value.\r | |
| 1167 | \r | |
| 1168 | <b>Example usage</b>\r | |
| 1169 | @code\r | |
| 1170 | UINT64 Msr;\r | |
| 1171 | \r | |
| 1172 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY);\r | |
| 1173 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY, Msr);\r | |
| 1174 | @endcode\r | |
| 1175 | @note MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r | |
| 1176 | **/\r | |
| 1177 | #define MSR_GOLDMONT_PKG_C6_RESIDENCY 0x000003F9\r | |
| 1178 | \r | |
| 1179 | \r | |
| 1180 | /**\r | |
| 1181 | Core. Note: C-state values are processor specific C-state code names,\r | |
| 1182 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r | |
| 1183 | Residency Counter. (R/O) Value since last reset that this core is in\r | |
| 1184 | processor-specific C3 states. Count at the same frequency as the TSC.\r | |
| 1185 | \r | |
| 1186 | @param ECX MSR_GOLDMONT_CORE_C3_RESIDENCY (0x000003FC)\r | |
| 1187 | @param EAX Lower 32-bits of MSR value.\r | |
| 1188 | @param EDX Upper 32-bits of MSR value.\r | |
| 1189 | \r | |
| 1190 | <b>Example usage</b>\r | |
| 1191 | @code\r | |
| 1192 | UINT64 Msr;\r | |
| 1193 | \r | |
| 1194 | Msr = AsmReadMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY);\r | |
| 1195 | AsmWriteMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY, Msr);\r | |
| 1196 | @endcode\r | |
| 1197 | @note MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r | |
| 1198 | **/\r | |
| 1199 | #define MSR_GOLDMONT_CORE_C3_RESIDENCY 0x000003FC\r | |
| 1200 | \r | |
| 1201 | \r | |
| 1202 | /**\r | |
| 1203 | Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability\r | |
| 1204 | Enhancement. Accessible only while in SMM.\r | |
| 1205 | \r | |
| 1206 | @param ECX MSR_GOLDMONT_SMM_FEATURE_CONTROL (0x000004E0)\r | |
| 1207 | @param EAX Lower 32-bits of MSR value.\r | |
| 1208 | Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.\r | |
| 1209 | @param EDX Upper 32-bits of MSR value.\r | |
| 1210 | Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.\r | |
| 1211 | \r | |
| 1212 | <b>Example usage</b>\r | |
| 1213 | @code\r | |
| 1214 | MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER Msr;\r | |
| 1215 | \r | |
| 1216 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL);\r | |
| 1217 | AsmWriteMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL, Msr.Uint64);\r | |
| 1218 | @endcode\r | |
| 1219 | @note MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.\r | |
| 1220 | **/\r | |
| 1221 | #define MSR_GOLDMONT_SMM_FEATURE_CONTROL 0x000004E0\r | |
| 1222 | \r | |
| 1223 | /**\r | |
| 1224 | MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL\r | |
| 1225 | **/\r | |
| 1226 | typedef union {\r | |
| 1227 | ///\r | |
| 1228 | /// Individual bit fields\r | |
| 1229 | ///\r | |
| 1230 | struct {\r | |
| 1231 | ///\r | |
| 1232 | /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from\r | |
| 1233 | /// further changes.\r | |
| 1234 | ///\r | |
| 1235 | UINT32 Lock:1;\r | |
| 1236 | UINT32 Reserved1:1;\r | |
| 1237 | ///\r | |
| 1238 | /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if\r | |
| 1239 | /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the\r | |
| 1240 | /// logical processors are prevented from executing SMM code outside the\r | |
| 1241 | /// ranges defined by the SMRR. When set to '1' any logical processor in\r | |
| 1242 | /// the package that attempts to execute SMM code not within the ranges\r | |
| 1243 | /// defined by the SMRR will assert an unrecoverable MCE.\r | |
| 1244 | ///\r | |
| 1245 | UINT32 SMM_Code_Chk_En:1;\r | |
| 1246 | UINT32 Reserved2:29;\r | |
| 1247 | UINT32 Reserved3:32;\r | |
| 1248 | } Bits;\r | |
| 1249 | ///\r | |
| 1250 | /// All bit fields as a 32-bit value\r | |
| 1251 | ///\r | |
| 1252 | UINT32 Uint32;\r | |
| 1253 | ///\r | |
| 1254 | /// All bit fields as a 64-bit value\r | |
| 1255 | ///\r | |
| 1256 | UINT64 Uint64;\r | |
| 1257 | } MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER;\r | |
| 1258 | \r | |
| 1259 | \r | |
| 1260 | /**\r | |
| 1261 | Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical\r | |
| 1262 | processors in the package. Available only while in SMM and\r | |
| 1263 | MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.\r | |
| 1264 | \r | |
| 1265 | @param ECX MSR_GOLDMONT_SMM_DELAYED (0x000004E2)\r | |
| 1266 | @param EAX Lower 32-bits of MSR value.\r | |
| 1267 | Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.\r | |
| 1268 | @param EDX Upper 32-bits of MSR value.\r | |
| 1269 | Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.\r | |
| 1270 | \r | |
| 1271 | <b>Example usage</b>\r | |
| 1272 | @code\r | |
| 1273 | MSR_GOLDMONT_SMM_DELAYED_REGISTER Msr;\r | |
| 1274 | \r | |
| 1275 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_DELAYED);\r | |
| 1276 | AsmWriteMsr64 (MSR_GOLDMONT_SMM_DELAYED, Msr.Uint64);\r | |
| 1277 | @endcode\r | |
| 1278 | @note MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.\r | |
| 1279 | **/\r | |
| 1280 | #define MSR_GOLDMONT_SMM_DELAYED 0x000004E2\r | |
| 1281 | \r | |
| 1282 | \r | |
| 1283 | /**\r | |
| 1284 | Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical\r | |
| 1285 | processors in the package. Available only while in SMM.\r | |
| 1286 | \r | |
| 1287 | @param ECX MSR_GOLDMONT_SMM_BLOCKED (0x000004E3)\r | |
| 1288 | @param EAX Lower 32-bits of MSR value.\r | |
| 1289 | Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.\r | |
| 1290 | @param EDX Upper 32-bits of MSR value.\r | |
| 1291 | Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.\r | |
| 1292 | \r | |
| 1293 | <b>Example usage</b>\r | |
| 1294 | @code\r | |
| 1295 | MSR_GOLDMONT_SMM_BLOCKED_REGISTER Msr;\r | |
| 1296 | \r | |
| 1297 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_BLOCKED);\r | |
| 1298 | AsmWriteMsr64 (MSR_GOLDMONT_SMM_BLOCKED, Msr.Uint64);\r | |
| 1299 | @endcode\r | |
| 1300 | @note MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.\r | |
| 1301 | **/\r | |
| 1302 | #define MSR_GOLDMONT_SMM_BLOCKED 0x000004E3\r | |
| 1303 | \r | |
| 1304 | \r | |
| 1305 | /**\r | |
| 1306 | Core. Trace Control Register (R/W).\r | |
| 1307 | \r | |
| 1308 | @param ECX MSR_GOLDMONT_IA32_RTIT_CTL (0x00000570)\r | |
| 1309 | @param EAX Lower 32-bits of MSR value.\r | |
| 1310 | Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.\r | |
| 1311 | @param EDX Upper 32-bits of MSR value.\r | |
| 1312 | Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.\r | |
| 1313 | \r | |
| 1314 | <b>Example usage</b>\r | |
| 1315 | @code\r | |
| 1316 | MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER Msr;\r | |
| 1317 | \r | |
| 1318 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL);\r | |
| 1319 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL, Msr.Uint64);\r | |
| 1320 | @endcode\r | |
| 1321 | @note MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r | |
| 1322 | **/\r | |
| 1323 | #define MSR_IA32_RTIT_CTL 0x00000570\r | |
| 1324 | \r | |
| 1325 | /**\r | |
| 1326 | MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r | |
| 1327 | **/\r | |
| 1328 | typedef union {\r | |
| 1329 | ///\r | |
| 1330 | /// Individual bit fields\r | |
| 1331 | ///\r | |
| 1332 | struct {\r | |
| 1333 | ///\r | |
| 1334 | /// [Bit 0] TraceEn.\r | |
| 1335 | ///\r | |
| 1336 | UINT32 TraceEn:1;\r | |
| 1337 | ///\r | |
| 1338 | /// [Bit 1] CYCEn.\r | |
| 1339 | ///\r | |
| 1340 | UINT32 CYCEn:1;\r | |
| 1341 | ///\r | |
| 1342 | /// [Bit 2] OS.\r | |
| 1343 | ///\r | |
| 1344 | UINT32 OS:1;\r | |
| 1345 | ///\r | |
| 1346 | /// [Bit 3] User.\r | |
| 1347 | ///\r | |
| 1348 | UINT32 User:1;\r | |
| 1349 | UINT32 Reserved1:3;\r | |
| 1350 | ///\r | |
| 1351 | /// [Bit 7] CR3 filter.\r | |
| 1352 | ///\r | |
| 1353 | UINT32 CR3:1;\r | |
| 1354 | ///\r | |
| 1355 | /// [Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn.\r | |
| 1356 | ///\r | |
| 1357 | UINT32 ToPA:1;\r | |
| 1358 | ///\r | |
| 1359 | /// [Bit 9] MTCEn.\r | |
| 1360 | ///\r | |
| 1361 | UINT32 MTCEn:1;\r | |
| 1362 | ///\r | |
| 1363 | /// [Bit 10] TSCEn.\r | |
| 1364 | ///\r | |
| 1365 | UINT32 TSCEn:1;\r | |
| 1366 | ///\r | |
| 1367 | /// [Bit 11] DisRETC.\r | |
| 1368 | ///\r | |
| 1369 | UINT32 DisRETC:1;\r | |
| 1370 | UINT32 Reserved2:1;\r | |
| 1371 | ///\r | |
| 1372 | /// [Bit 13] BranchEn.\r | |
| 1373 | ///\r | |
| 1374 | UINT32 BranchEn:1;\r | |
| 1375 | ///\r | |
| 1376 | /// [Bits 17:14] MTCFreq.\r | |
| 1377 | ///\r | |
| 1378 | UINT32 MTCFreq:4;\r | |
| 1379 | UINT32 Reserved3:1;\r | |
| 1380 | ///\r | |
| 1381 | /// [Bits 22:19] CYCThresh.\r | |
| 1382 | ///\r | |
| 1383 | UINT32 CYCThresh:4;\r | |
| 1384 | UINT32 Reserved4:1;\r | |
| 1385 | ///\r | |
| 1386 | /// [Bits 27:24] PSBFreq.\r | |
| 1387 | ///\r | |
| 1388 | UINT32 PSBFreq:4;\r | |
| 1389 | UINT32 Reserved5:4;\r | |
| 1390 | ///\r | |
| 1391 | /// [Bits 35:32] ADDR0_CFG.\r | |
| 1392 | ///\r | |
| 1393 | UINT32 ADDR0_CFG:4;\r | |
| 1394 | ///\r | |
| 1395 | /// [Bits 39:36] ADDR1_CFG.\r | |
| 1396 | ///\r | |
| 1397 | UINT32 ADDR1_CFG:4;\r | |
| 1398 | UINT32 Reserved6:24;\r | |
| 1399 | } Bits;\r | |
| 1400 | ///\r | |
| 1401 | /// All bit fields as a 64-bit value\r | |
| 1402 | ///\r | |
| 1403 | UINT64 Uint64;\r | |
| 1404 | } MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER;\r | |
| 1405 | \r | |
| 1406 | \r | |
| 1407 | /**\r | |
| 1408 | Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r | |
| 1409 | "RAPL Interfaces.".\r | |
| 1410 | \r | |
| 1411 | @param ECX MSR_GOLDMONT_RAPL_POWER_UNIT (0x00000606)\r | |
| 1412 | @param EAX Lower 32-bits of MSR value.\r | |
| 1413 | Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.\r | |
| 1414 | @param EDX Upper 32-bits of MSR value.\r | |
| 1415 | Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.\r | |
| 1416 | \r | |
| 1417 | <b>Example usage</b>\r | |
| 1418 | @code\r | |
| 1419 | MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER Msr;\r | |
| 1420 | \r | |
| 1421 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_RAPL_POWER_UNIT);\r | |
| 1422 | @endcode\r | |
| 1423 | @note MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r | |
| 1424 | **/\r | |
| 1425 | #define MSR_GOLDMONT_RAPL_POWER_UNIT 0x00000606\r | |
| 1426 | \r | |
| 1427 | /**\r | |
| 1428 | MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT\r | |
| 1429 | **/\r | |
| 1430 | typedef union {\r | |
| 1431 | ///\r | |
| 1432 | /// Individual bit fields\r | |
| 1433 | ///\r | |
| 1434 | struct {\r | |
| 1435 | ///\r | |
| 1436 | /// [Bits 3:0] Power Units. Power related information (in Watts) is in\r | |
| 1437 | /// unit of, 1W/2^PU; where PU is an unsigned integer represented by bits\r | |
| 1438 | /// 3:0. Default value is 1000b, indicating power unit is in 3.9\r | |
| 1439 | /// milliWatts increment.\r | |
| 1440 | ///\r | |
| 1441 | UINT32 PowerUnits:4;\r | |
| 1442 | UINT32 Reserved1:4;\r | |
| 1443 | ///\r | |
| 1444 | /// [Bits 12:8] Energy Status Units. Energy related information (in\r | |
| 1445 | /// Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned\r | |
| 1446 | /// integer represented by bits 12:8. Default value is 01110b, indicating\r | |
| 1447 | /// energy unit is in 61 microJoules.\r | |
| 1448 | ///\r | |
| 1449 | UINT32 EnergyStatusUnits:5;\r | |
| 1450 | UINT32 Reserved2:3;\r | |
| 1451 | ///\r | |
| 1452 | /// [Bits 19:16] Time Unit. Time related information (in seconds) is in\r | |
| 1453 | /// unit of, 1S/2^TU; where TU is an unsigned integer represented by bits\r | |
| 1454 | /// 19:16. Default value is 1010b, indicating power unit is in 0.977\r | |
| 1455 | /// millisecond.\r | |
| 1456 | ///\r | |
| 1457 | UINT32 TimeUnit:4;\r | |
| 1458 | UINT32 Reserved3:12;\r | |
| 1459 | UINT32 Reserved4:32;\r | |
| 1460 | } Bits;\r | |
| 1461 | ///\r | |
| 1462 | /// All bit fields as a 32-bit value\r | |
| 1463 | ///\r | |
| 1464 | UINT32 Uint32;\r | |
| 1465 | ///\r | |
| 1466 | /// All bit fields as a 64-bit value\r | |
| 1467 | ///\r | |
| 1468 | UINT64 Uint64;\r | |
| 1469 | } MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER;\r | |
| 1470 | \r | |
| 1471 | \r | |
| 1472 | /**\r | |
| 1473 | Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are\r | |
| 1474 | processor specific C-state code names, unrelated to MWAIT extension C-state\r | |
| 1475 | parameters or ACPI CStates.\r | |
| 1476 | \r | |
| 1477 | @param ECX MSR_GOLDMONT_PKGC3_IRTL (0x0000060A)\r | |
| 1478 | @param EAX Lower 32-bits of MSR value.\r | |
| 1479 | Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.\r | |
| 1480 | @param EDX Upper 32-bits of MSR value.\r | |
| 1481 | Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.\r | |
| 1482 | \r | |
| 1483 | <b>Example usage</b>\r | |
| 1484 | @code\r | |
| 1485 | MSR_GOLDMONT_PKGC3_IRTL_REGISTER Msr;\r | |
| 1486 | \r | |
| 1487 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC3_IRTL);\r | |
| 1488 | AsmWriteMsr64 (MSR_GOLDMONT_PKGC3_IRTL, Msr.Uint64);\r | |
| 1489 | @endcode\r | |
| 1490 | @note MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.\r | |
| 1491 | **/\r | |
| 1492 | #define MSR_GOLDMONT_PKGC3_IRTL 0x0000060A\r | |
| 1493 | \r | |
| 1494 | /**\r | |
| 1495 | MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL\r | |
| 1496 | **/\r | |
| 1497 | typedef union {\r | |
| 1498 | ///\r | |
| 1499 | /// Individual bit fields\r | |
| 1500 | ///\r | |
| 1501 | struct {\r | |
| 1502 | ///\r | |
| 1503 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r | |
| 1504 | /// that should be used to decide if the package should be put into a\r | |
| 1505 | /// package C3 state.\r | |
| 1506 | ///\r | |
| 1507 | UINT32 InterruptResponseTimeLimit:10;\r | |
| 1508 | ///\r | |
| ba1a2d11 ED |
1509 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r |
| 1510 | /// of the interrupt response time limit. See Table 2-19 for supported\r | |
| 1511 | /// time unit encodings.\r | |
| 35fd9411 HW |
1512 | ///\r |
| 1513 | UINT32 TimeUnit:3;\r | |
| 1514 | UINT32 Reserved1:2;\r | |
| 1515 | ///\r | |
| 1516 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r | |
| 1517 | /// valid and can be used by the processor for package C-sate management.\r | |
| 1518 | ///\r | |
| 1519 | UINT32 Valid:1;\r | |
| 1520 | UINT32 Reserved2:16;\r | |
| 1521 | UINT32 Reserved3:32;\r | |
| 1522 | } Bits;\r | |
| 1523 | ///\r | |
| 1524 | /// All bit fields as a 32-bit value\r | |
| 1525 | ///\r | |
| 1526 | UINT32 Uint32;\r | |
| 1527 | ///\r | |
| 1528 | /// All bit fields as a 64-bit value\r | |
| 1529 | ///\r | |
| 1530 | UINT64 Uint64;\r | |
| 1531 | } MSR_GOLDMONT_PKGC3_IRTL_REGISTER;\r | |
| 1532 | \r | |
| 1533 | \r | |
| 1534 | /**\r | |
| 1535 | Package. Package C6/C7S Interrupt Response Limit 1 (R/W) This MSR defines\r | |
| 1536 | the interrupt response time limit used by the processor to manage transition\r | |
| 1537 | to package C6 or C7S state. Note: C-state values are processor specific\r | |
| 1538 | C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r | |
| 1539 | CStates.\r | |
| 1540 | \r | |
| 1541 | @param ECX MSR_GOLDMONT_PKGC_IRTL1 (0x0000060B)\r | |
| 1542 | @param EAX Lower 32-bits of MSR value.\r | |
| 1543 | Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.\r | |
| 1544 | @param EDX Upper 32-bits of MSR value.\r | |
| 1545 | Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.\r | |
| 1546 | \r | |
| 1547 | <b>Example usage</b>\r | |
| 1548 | @code\r | |
| 1549 | MSR_GOLDMONT_PKGC_IRTL1_REGISTER Msr;\r | |
| 1550 | \r | |
| 1551 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL1);\r | |
| 1552 | AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL1, Msr.Uint64);\r | |
| 1553 | @endcode\r | |
| 1554 | @note MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.\r | |
| 1555 | **/\r | |
| 1556 | #define MSR_GOLDMONT_PKGC_IRTL1 0x0000060B\r | |
| 1557 | \r | |
| 1558 | /**\r | |
| 1559 | MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1\r | |
| 1560 | **/\r | |
| 1561 | typedef union {\r | |
| 1562 | ///\r | |
| 1563 | /// Individual bit fields\r | |
| 1564 | ///\r | |
| 1565 | struct {\r | |
| 1566 | ///\r | |
| 1567 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r | |
| 1568 | /// that should be used to decide if the package should be put into a\r | |
| 1569 | /// package C6 or C7S state.\r | |
| 1570 | ///\r | |
| 1571 | UINT32 InterruptResponseTimeLimit:10;\r | |
| 1572 | ///\r | |
| ba1a2d11 ED |
1573 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r |
| 1574 | /// of the interrupt response time limit. See Table 2-19 for supported\r | |
| 1575 | /// time unit encodings.\r | |
| 35fd9411 HW |
1576 | ///\r |
| 1577 | UINT32 TimeUnit:3;\r | |
| 1578 | UINT32 Reserved1:2;\r | |
| 1579 | ///\r | |
| 1580 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r | |
| 1581 | /// valid and can be used by the processor for package C-sate management.\r | |
| 1582 | ///\r | |
| 1583 | UINT32 Valid:1;\r | |
| 1584 | UINT32 Reserved2:16;\r | |
| 1585 | UINT32 Reserved3:32;\r | |
| 1586 | } Bits;\r | |
| 1587 | ///\r | |
| 1588 | /// All bit fields as a 32-bit value\r | |
| 1589 | ///\r | |
| 1590 | UINT32 Uint32;\r | |
| 1591 | ///\r | |
| 1592 | /// All bit fields as a 64-bit value\r | |
| 1593 | ///\r | |
| 1594 | UINT64 Uint64;\r | |
| 1595 | } MSR_GOLDMONT_PKGC_IRTL1_REGISTER;\r | |
| 1596 | \r | |
| 1597 | \r | |
| 1598 | /**\r | |
| 1599 | Package. Package C7 Interrupt Response Limit 2 (R/W) This MSR defines the\r | |
| 1600 | interrupt response time limit used by the processor to manage transition to\r | |
| 1601 | package C7 state. Note: C-state values are processor specific C-state code\r | |
| 1602 | names, unrelated to MWAIT extension C-state parameters or ACPI CStates.\r | |
| 1603 | \r | |
| 1604 | @param ECX MSR_GOLDMONT_PKGC_IRTL2 (0x0000060C)\r | |
| 1605 | @param EAX Lower 32-bits of MSR value.\r | |
| 1606 | Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.\r | |
| 1607 | @param EDX Upper 32-bits of MSR value.\r | |
| 1608 | Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.\r | |
| 1609 | \r | |
| 1610 | <b>Example usage</b>\r | |
| 1611 | @code\r | |
| 1612 | MSR_GOLDMONT_PKGC_IRTL2_REGISTER Msr;\r | |
| 1613 | \r | |
| 1614 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL2);\r | |
| 1615 | AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL2, Msr.Uint64);\r | |
| 1616 | @endcode\r | |
| 1617 | @note MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.\r | |
| 1618 | **/\r | |
| 1619 | #define MSR_GOLDMONT_PKGC_IRTL2 0x0000060C\r | |
| 1620 | \r | |
| 1621 | /**\r | |
| 1622 | MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2\r | |
| 1623 | **/\r | |
| 1624 | typedef union {\r | |
| 1625 | ///\r | |
| 1626 | /// Individual bit fields\r | |
| 1627 | ///\r | |
| 1628 | struct {\r | |
| 1629 | ///\r | |
| 1630 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r | |
| 1631 | /// that should be used to decide if the package should be put into a\r | |
| 1632 | /// package C7 state.\r | |
| 1633 | ///\r | |
| 1634 | UINT32 InterruptResponseTimeLimit:10;\r | |
| 1635 | ///\r | |
| ba1a2d11 ED |
1636 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r |
| 1637 | /// of the interrupt response time limit. See Table 2-19 for supported\r | |
| 1638 | /// time unit encodings.\r | |
| 35fd9411 HW |
1639 | ///\r |
| 1640 | UINT32 TimeUnit:3;\r | |
| 1641 | UINT32 Reserved1:2;\r | |
| 1642 | ///\r | |
| 1643 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r | |
| 1644 | /// valid and can be used by the processor for package C-sate management.\r | |
| 1645 | ///\r | |
| 1646 | UINT32 Valid:1;\r | |
| 1647 | UINT32 Reserved2:16;\r | |
| 1648 | UINT32 Reserved3:32;\r | |
| 1649 | } Bits;\r | |
| 1650 | ///\r | |
| 1651 | /// All bit fields as a 32-bit value\r | |
| 1652 | ///\r | |
| 1653 | UINT32 Uint32;\r | |
| 1654 | ///\r | |
| 1655 | /// All bit fields as a 64-bit value\r | |
| 1656 | ///\r | |
| 1657 | UINT64 Uint64;\r | |
| 1658 | } MSR_GOLDMONT_PKGC_IRTL2_REGISTER;\r | |
| 1659 | \r | |
| 1660 | \r | |
| 1661 | /**\r | |
| 1662 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 1663 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2\r | |
| 1664 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
| 1665 | processor-specific C2 states. Count at the same frequency as the TSC.\r | |
| 1666 | \r | |
| 1667 | @param ECX MSR_GOLDMONT_PKG_C2_RESIDENCY (0x0000060D)\r | |
| 1668 | @param EAX Lower 32-bits of MSR value.\r | |
| 1669 | @param EDX Upper 32-bits of MSR value.\r | |
| 1670 | \r | |
| 1671 | <b>Example usage</b>\r | |
| 1672 | @code\r | |
| 1673 | UINT64 Msr;\r | |
| 1674 | \r | |
| 1675 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY);\r | |
| 1676 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY, Msr);\r | |
| 1677 | @endcode\r | |
| 1678 | @note MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r | |
| 1679 | **/\r | |
| 1680 | #define MSR_GOLDMONT_PKG_C2_RESIDENCY 0x0000060D\r | |
| 1681 | \r | |
| 1682 | \r | |
| 1683 | /**\r | |
| 1684 | Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r | |
| 1685 | RAPL Domain.".\r | |
| 1686 | \r | |
| 1687 | @param ECX MSR_GOLDMONT_PKG_POWER_LIMIT (0x00000610)\r | |
| 1688 | @param EAX Lower 32-bits of MSR value.\r | |
| 1689 | @param EDX Upper 32-bits of MSR value.\r | |
| 1690 | \r | |
| 1691 | <b>Example usage</b>\r | |
| 1692 | @code\r | |
| 1693 | UINT64 Msr;\r | |
| 1694 | \r | |
| 1695 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT);\r | |
| 1696 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT, Msr);\r | |
| 1697 | @endcode\r | |
| 1698 | @note MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r | |
| 1699 | **/\r | |
| 1700 | #define MSR_GOLDMONT_PKG_POWER_LIMIT 0x00000610\r | |
| 1701 | \r | |
| 1702 | \r | |
| 1703 | /**\r | |
| 1704 | Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r | |
| 1705 | \r | |
| 1706 | @param ECX MSR_GOLDMONT_PKG_ENERGY_STATUS (0x00000611)\r | |
| 1707 | @param EAX Lower 32-bits of MSR value.\r | |
| 1708 | @param EDX Upper 32-bits of MSR value.\r | |
| 1709 | \r | |
| 1710 | <b>Example usage</b>\r | |
| 1711 | @code\r | |
| 1712 | UINT64 Msr;\r | |
| 1713 | \r | |
| 1714 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_ENERGY_STATUS);\r | |
| 1715 | @endcode\r | |
| 1716 | @note MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r | |
| 1717 | **/\r | |
| 1718 | #define MSR_GOLDMONT_PKG_ENERGY_STATUS 0x00000611\r | |
| 1719 | \r | |
| 1720 | \r | |
| 1721 | /**\r | |
| 1722 | Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r | |
| 1723 | \r | |
| 1724 | @param ECX MSR_GOLDMONT_PKG_PERF_STATUS (0x00000613)\r | |
| 1725 | @param EAX Lower 32-bits of MSR value.\r | |
| 1726 | @param EDX Upper 32-bits of MSR value.\r | |
| 1727 | \r | |
| 1728 | <b>Example usage</b>\r | |
| 1729 | @code\r | |
| 1730 | UINT64 Msr;\r | |
| 1731 | \r | |
| 1732 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_PERF_STATUS);\r | |
| 1733 | @endcode\r | |
| 1734 | @note MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r | |
| 1735 | **/\r | |
| 1736 | #define MSR_GOLDMONT_PKG_PERF_STATUS 0x00000613\r | |
| 1737 | \r | |
| 1738 | \r | |
| 1739 | /**\r | |
| 1740 | Package. PKG RAPL Parameters (R/W).\r | |
| 1741 | \r | |
| 1742 | @param ECX MSR_GOLDMONT_PKG_POWER_INFO (0x00000614)\r | |
| 1743 | @param EAX Lower 32-bits of MSR value.\r | |
| 1744 | Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.\r | |
| 1745 | @param EDX Upper 32-bits of MSR value.\r | |
| 1746 | Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.\r | |
| 1747 | \r | |
| 1748 | <b>Example usage</b>\r | |
| 1749 | @code\r | |
| 1750 | MSR_GOLDMONT_PKG_POWER_INFO_REGISTER Msr;\r | |
| 1751 | \r | |
| 1752 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_INFO);\r | |
| 1753 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_INFO, Msr.Uint64);\r | |
| 1754 | @endcode\r | |
| 1755 | @note MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r | |
| 1756 | **/\r | |
| 1757 | #define MSR_GOLDMONT_PKG_POWER_INFO 0x00000614\r | |
| 1758 | \r | |
| 1759 | /**\r | |
| 1760 | MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO\r | |
| 1761 | **/\r | |
| 1762 | typedef union {\r | |
| 1763 | ///\r | |
| 1764 | /// Individual bit fields\r | |
| 1765 | ///\r | |
| 1766 | struct {\r | |
| 1767 | ///\r | |
| 1768 | /// [Bits 14:0] Thermal Spec Power (R/W) See Section 14.9.3, "Package\r | |
| 1769 | /// RAPL Domain.".\r | |
| 1770 | ///\r | |
| 1771 | UINT32 ThermalSpecPower:15;\r | |
| 1772 | UINT32 Reserved1:1;\r | |
| 1773 | ///\r | |
| 1774 | /// [Bits 30:16] Minimum Power (R/W) See Section 14.9.3, "Package RAPL\r | |
| 1775 | /// Domain.".\r | |
| 1776 | ///\r | |
| 1777 | UINT32 MinimumPower:15;\r | |
| 1778 | UINT32 Reserved2:1;\r | |
| 1779 | ///\r | |
| 1780 | /// [Bits 46:32] Maximum Power (R/W) See Section 14.9.3, "Package RAPL\r | |
| 1781 | /// Domain.".\r | |
| 1782 | ///\r | |
| 1783 | UINT32 MaximumPower:15;\r | |
| 1784 | UINT32 Reserved3:1;\r | |
| 1785 | ///\r | |
| 1786 | /// [Bits 54:48] Maximum Time Window (R/W) Specified by 2^Y * (1.0 +\r | |
| 1787 | /// Z/4.0) * Time_Unit, where "Y" is the unsigned integer value\r | |
| 1788 | /// represented. by bits 52:48, "Z" is an unsigned integer represented by\r | |
| 1789 | /// bits 54:53. "Time_Unit" is specified by the "Time Units" field of\r | |
| 1790 | /// MSR_RAPL_POWER_UNIT.\r | |
| 1791 | ///\r | |
| 1792 | UINT32 MaximumTimeWindow:7;\r | |
| 1793 | UINT32 Reserved4:9;\r | |
| 1794 | } Bits;\r | |
| 1795 | ///\r | |
| 1796 | /// All bit fields as a 64-bit value\r | |
| 1797 | ///\r | |
| 1798 | UINT64 Uint64;\r | |
| 1799 | } MSR_GOLDMONT_PKG_POWER_INFO_REGISTER;\r | |
| 1800 | \r | |
| 1801 | \r | |
| 1802 | /**\r | |
| 1803 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r | |
| 1804 | Domain.".\r | |
| 1805 | \r | |
| 1806 | @param ECX MSR_GOLDMONT_DRAM_POWER_LIMIT (0x00000618)\r | |
| 1807 | @param EAX Lower 32-bits of MSR value.\r | |
| 1808 | @param EDX Upper 32-bits of MSR value.\r | |
| 1809 | \r | |
| 1810 | <b>Example usage</b>\r | |
| 1811 | @code\r | |
| 1812 | UINT64 Msr;\r | |
| 1813 | \r | |
| 1814 | Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT);\r | |
| 1815 | AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT, Msr);\r | |
| 1816 | @endcode\r | |
| 1817 | @note MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r | |
| 1818 | **/\r | |
| 1819 | #define MSR_GOLDMONT_DRAM_POWER_LIMIT 0x00000618\r | |
| 1820 | \r | |
| 1821 | \r | |
| 1822 | /**\r | |
| 1823 | Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
| 1824 | \r | |
| 1825 | @param ECX MSR_GOLDMONT_DRAM_ENERGY_STATUS (0x00000619)\r | |
| 1826 | @param EAX Lower 32-bits of MSR value.\r | |
| 1827 | @param EDX Upper 32-bits of MSR value.\r | |
| 1828 | \r | |
| 1829 | <b>Example usage</b>\r | |
| 1830 | @code\r | |
| 1831 | UINT64 Msr;\r | |
| 1832 | \r | |
| 1833 | Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_ENERGY_STATUS);\r | |
| 1834 | @endcode\r | |
| 1835 | @note MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r | |
| 1836 | **/\r | |
| 1837 | #define MSR_GOLDMONT_DRAM_ENERGY_STATUS 0x00000619\r | |
| 1838 | \r | |
| 1839 | \r | |
| 1840 | /**\r | |
| 1841 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r | |
| 1842 | RAPL Domain.".\r | |
| 1843 | \r | |
| 1844 | @param ECX MSR_GOLDMONT_DRAM_PERF_STATUS (0x0000061B)\r | |
| 1845 | @param EAX Lower 32-bits of MSR value.\r | |
| 1846 | @param EDX Upper 32-bits of MSR value.\r | |
| 1847 | \r | |
| 1848 | <b>Example usage</b>\r | |
| 1849 | @code\r | |
| 1850 | UINT64 Msr;\r | |
| 1851 | \r | |
| 1852 | Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_PERF_STATUS);\r | |
| 1853 | @endcode\r | |
| 1854 | @note MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r | |
| 1855 | **/\r | |
| 1856 | #define MSR_GOLDMONT_DRAM_PERF_STATUS 0x0000061B\r | |
| 1857 | \r | |
| 1858 | \r | |
| 1859 | /**\r | |
| 1860 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
| 1861 | \r | |
| 1862 | @param ECX MSR_GOLDMONT_DRAM_POWER_INFO (0x0000061C)\r | |
| 1863 | @param EAX Lower 32-bits of MSR value.\r | |
| 1864 | @param EDX Upper 32-bits of MSR value.\r | |
| 1865 | \r | |
| 1866 | <b>Example usage</b>\r | |
| 1867 | @code\r | |
| 1868 | UINT64 Msr;\r | |
| 1869 | \r | |
| 1870 | Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO);\r | |
| 1871 | AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO, Msr);\r | |
| 1872 | @endcode\r | |
| 1873 | @note MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r | |
| 1874 | **/\r | |
| 1875 | #define MSR_GOLDMONT_DRAM_POWER_INFO 0x0000061C\r | |
| 1876 | \r | |
| 1877 | \r | |
| 1878 | /**\r | |
| 1879 | Package. Note: C-state values are processor specific C-state code names,.\r | |
| 1880 | Package C10 Residency Counter. (R/O) Value since last reset that the entire\r | |
| 1881 | SOC is in an S0i3 state. Count at the same frequency as the TSC.\r | |
| 1882 | \r | |
| 1883 | @param ECX MSR_GOLDMONT_PKG_C10_RESIDENCY (0x00000632)\r | |
| 1884 | @param EAX Lower 32-bits of MSR value.\r | |
| 1885 | @param EDX Upper 32-bits of MSR value.\r | |
| 1886 | \r | |
| 1887 | <b>Example usage</b>\r | |
| 1888 | @code\r | |
| 1889 | UINT64 Msr;\r | |
| 1890 | \r | |
| 1891 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY);\r | |
| 1892 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY, Msr);\r | |
| 1893 | @endcode\r | |
| 1894 | @note MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r | |
| 1895 | **/\r | |
| 1896 | #define MSR_GOLDMONT_PKG_C10_RESIDENCY 0x00000632\r | |
| 1897 | \r | |
| 1898 | \r | |
| 1899 | /**\r | |
| 1900 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
| 1901 | Domains.".\r | |
| 1902 | \r | |
| 1903 | @param ECX MSR_GOLDMONT_PP0_ENERGY_STATUS (0x00000639)\r | |
| 1904 | @param EAX Lower 32-bits of MSR value.\r | |
| 1905 | @param EDX Upper 32-bits of MSR value.\r | |
| 1906 | \r | |
| 1907 | <b>Example usage</b>\r | |
| 1908 | @code\r | |
| 1909 | UINT64 Msr;\r | |
| 1910 | \r | |
| 1911 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PP0_ENERGY_STATUS);\r | |
| 1912 | @endcode\r | |
| 1913 | @note MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r | |
| 1914 | **/\r | |
| 1915 | #define MSR_GOLDMONT_PP0_ENERGY_STATUS 0x00000639\r | |
| 1916 | \r | |
| 1917 | \r | |
| 1918 | /**\r | |
| 1919 | Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
| 1920 | Domains.".\r | |
| 1921 | \r | |
| 1922 | @param ECX MSR_GOLDMONT_PP1_ENERGY_STATUS (0x00000641)\r | |
| 1923 | @param EAX Lower 32-bits of MSR value.\r | |
| 1924 | @param EDX Upper 32-bits of MSR value.\r | |
| 1925 | \r | |
| 1926 | <b>Example usage</b>\r | |
| 1927 | @code\r | |
| 1928 | UINT64 Msr;\r | |
| 1929 | \r | |
| 1930 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PP1_ENERGY_STATUS);\r | |
| 1931 | @endcode\r | |
| 1932 | @note MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r | |
| 1933 | **/\r | |
| 1934 | #define MSR_GOLDMONT_PP1_ENERGY_STATUS 0x00000641\r | |
| 1935 | \r | |
| 1936 | \r | |
| 1937 | /**\r | |
| 1938 | Package. ConfigTDP Control (R/W).\r | |
| 1939 | \r | |
| 1940 | @param ECX MSR_GOLDMONT_TURBO_ACTIVATION_RATIO (0x0000064C)\r | |
| 1941 | @param EAX Lower 32-bits of MSR value.\r | |
| 1942 | Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.\r | |
| 1943 | @param EDX Upper 32-bits of MSR value.\r | |
| 1944 | Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.\r | |
| 1945 | \r | |
| 1946 | <b>Example usage</b>\r | |
| 1947 | @code\r | |
| 1948 | MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r | |
| 1949 | \r | |
| 1950 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO);\r | |
| 1951 | AsmWriteMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r | |
| 1952 | @endcode\r | |
| 1953 | @note MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r | |
| 1954 | **/\r | |
| 1955 | #define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 0x0000064C\r | |
| 1956 | \r | |
| 1957 | /**\r | |
| 1958 | MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO\r | |
| 1959 | **/\r | |
| 1960 | typedef union {\r | |
| 1961 | ///\r | |
| 1962 | /// Individual bit fields\r | |
| 1963 | ///\r | |
| 1964 | struct {\r | |
| 1965 | ///\r | |
| 1966 | /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r | |
| 1967 | /// field.\r | |
| 1968 | ///\r | |
| 1969 | UINT32 MAX_NON_TURBO_RATIO:8;\r | |
| 1970 | UINT32 Reserved1:23;\r | |
| 1971 | ///\r | |
| 1972 | /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r | |
| 1973 | /// content of this register is locked until a reset.\r | |
| 1974 | ///\r | |
| 1975 | UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r | |
| 1976 | UINT32 Reserved2:32;\r | |
| 1977 | } Bits;\r | |
| 1978 | ///\r | |
| 1979 | /// All bit fields as a 32-bit value\r | |
| 1980 | ///\r | |
| 1981 | UINT32 Uint32;\r | |
| 1982 | ///\r | |
| 1983 | /// All bit fields as a 64-bit value\r | |
| 1984 | ///\r | |
| 1985 | UINT64 Uint64;\r | |
| 1986 | } MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER;\r | |
| 1987 | \r | |
| 1988 | \r | |
| 1989 | /**\r | |
| 1990 | Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r | |
| 1991 | refers to processor core frequency).\r | |
| 1992 | \r | |
| 1993 | @param ECX MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS (0x0000064F)\r | |
| 1994 | @param EAX Lower 32-bits of MSR value.\r | |
| 1995 | Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1996 | @param EDX Upper 32-bits of MSR value.\r | |
| 1997 | Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1998 | \r | |
| 1999 | <b>Example usage</b>\r | |
| 2000 | @code\r | |
| 2001 | MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
| 2002 | \r | |
| 2003 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS);\r | |
| 2004 | AsmWriteMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
| 2005 | @endcode\r | |
| 2006 | @note MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r | |
| 2007 | **/\r | |
| 2008 | #define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 0x0000064F\r | |
| 2009 | \r | |
| 2010 | /**\r | |
| 2011 | MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS\r | |
| 2012 | **/\r | |
| 2013 | typedef union {\r | |
| 2014 | ///\r | |
| 2015 | /// Individual bit fields\r | |
| 2016 | ///\r | |
| 2017 | struct {\r | |
| 2018 | ///\r | |
| 2019 | /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r | |
| 2020 | /// reduced below the operating system request due to assertion of\r | |
| 2021 | /// external PROCHOT.\r | |
| 2022 | ///\r | |
| 2023 | UINT32 PROCHOTStatus:1;\r | |
| 2024 | ///\r | |
| 2025 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r | |
| 2026 | /// operating system request due to a thermal event.\r | |
| 2027 | ///\r | |
| 2028 | UINT32 ThermalStatus:1;\r | |
| 2029 | ///\r | |
| 2030 | /// [Bit 2] Package-Level Power Limiting PL1 Status (R0) When set,\r | |
| 2031 | /// frequency is reduced below the operating system request due to\r | |
| 2032 | /// package-level power limiting PL1.\r | |
| 2033 | ///\r | |
| 2034 | UINT32 PL1Status:1;\r | |
| 2035 | ///\r | |
| 2036 | /// [Bit 3] Package-Level PL2 Power Limiting Status (R0) When set,\r | |
| 2037 | /// frequency is reduced below the operating system request due to\r | |
| 2038 | /// package-level power limiting PL2.\r | |
| 2039 | ///\r | |
| 2040 | UINT32 PL2Status:1;\r | |
| 2041 | UINT32 Reserved1:5;\r | |
| 2042 | ///\r | |
| 2043 | /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced\r | |
| 2044 | /// below the operating system request due to domain-level power limiting.\r | |
| 2045 | ///\r | |
| 2046 | UINT32 PowerLimitingStatus:1;\r | |
| 2047 | ///\r | |
| 2048 | /// [Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced\r | |
| 2049 | /// below the operating system request due to a thermal alert from the\r | |
| 2050 | /// Voltage Regulator.\r | |
| 2051 | ///\r | |
| 2052 | UINT32 VRThermAlertStatus:1;\r | |
| 2053 | ///\r | |
| 2054 | /// [Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced\r | |
| 2055 | /// below the operating system request due to multi-core turbo limits.\r | |
| 2056 | ///\r | |
| 2057 | UINT32 MaxTurboLimitStatus:1;\r | |
| 2058 | ///\r | |
| 2059 | /// [Bit 12] Electrical Design Point Status (R0) When set, frequency is\r | |
| 2060 | /// reduced below the operating system request due to electrical design\r | |
| 2061 | /// point constraints (e.g. maximum electrical current consumption).\r | |
| 2062 | ///\r | |
| 2063 | UINT32 ElectricalDesignPointStatus:1;\r | |
| 2064 | ///\r | |
| 2065 | /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r | |
| 2066 | /// is reduced below the operating system request due to Turbo transition\r | |
| 2067 | /// attenuation. This prevents performance degradation due to frequent\r | |
| 2068 | /// operating ratio changes.\r | |
| 2069 | ///\r | |
| 2070 | UINT32 TurboTransitionAttenuationStatus:1;\r | |
| 2071 | ///\r | |
| 2072 | /// [Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency\r | |
| 2073 | /// is reduced below the maximum efficiency frequency.\r | |
| 2074 | ///\r | |
| 2075 | UINT32 MaximumEfficiencyFrequencyStatus:1;\r | |
| 2076 | UINT32 Reserved2:1;\r | |
| 2077 | ///\r | |
| 2078 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r | |
| 2079 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 2080 | /// remain set until cleared by software writing 0.\r | |
| 2081 | ///\r | |
| 2082 | UINT32 PROCHOT:1;\r | |
| 2083 | ///\r | |
| 2084 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r | |
| 2085 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 2086 | /// remain set until cleared by software writing 0.\r | |
| 2087 | ///\r | |
| 2088 | UINT32 ThermalLog:1;\r | |
| 2089 | ///\r | |
| 2090 | /// [Bit 18] Package-Level PL1 Power Limiting Log When set, indicates\r | |
| 2091 | /// that the Package Level PL1 Power Limiting Status bit has asserted\r | |
| 2092 | /// since the log bit was last cleared. This log bit will remain set until\r | |
| 2093 | /// cleared by software writing 0.\r | |
| 2094 | ///\r | |
| 2095 | UINT32 PL1Log:1;\r | |
| 2096 | ///\r | |
| 2097 | /// [Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that\r | |
| 2098 | /// the Package Level PL2 Power Limiting Status bit has asserted since the\r | |
| 2099 | /// log bit was last cleared. This log bit will remain set until cleared\r | |
| 2100 | /// by software writing 0.\r | |
| 2101 | ///\r | |
| 2102 | UINT32 PL2Log:1;\r | |
| 2103 | UINT32 Reserved3:5;\r | |
| 2104 | ///\r | |
| 2105 | /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r | |
| 2106 | /// Power Limiting Status bit has asserted since the log bit was last\r | |
| 2107 | /// cleared. This log bit will remain set until cleared by software\r | |
| 2108 | /// writing 0.\r | |
| 2109 | ///\r | |
| 2110 | UINT32 CorePowerLimitingLog:1;\r | |
| 2111 | ///\r | |
| 2112 | /// [Bit 26] VR Therm Alert Log When set, indicates that the VR Therm\r | |
| 2113 | /// Alert Status bit has asserted since the log bit was last cleared. This\r | |
| 2114 | /// log bit will remain set until cleared by software writing 0.\r | |
| 2115 | ///\r | |
| 2116 | UINT32 VRThermAlertLog:1;\r | |
| 2117 | ///\r | |
| 2118 | /// [Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo\r | |
| 2119 | /// Limit Status bit has asserted since the log bit was last cleared. This\r | |
| 2120 | /// log bit will remain set until cleared by software writing 0.\r | |
| 2121 | ///\r | |
| 2122 | UINT32 MaxTurboLimitLog:1;\r | |
| 2123 | ///\r | |
| 2124 | /// [Bit 28] Electrical Design Point Log When set, indicates that the EDP\r | |
| 2125 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 2126 | /// bit will remain set until cleared by software writing 0.\r | |
| 2127 | ///\r | |
| 2128 | UINT32 ElectricalDesignPointLog:1;\r | |
| 2129 | ///\r | |
| 2130 | /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r | |
| 2131 | /// Turbo Transition Attenuation Status bit has asserted since the log bit\r | |
| 2132 | /// was last cleared. This log bit will remain set until cleared by\r | |
| 2133 | /// software writing 0.\r | |
| 2134 | ///\r | |
| 2135 | UINT32 TurboTransitionAttenuationLog:1;\r | |
| 2136 | ///\r | |
| 2137 | /// [Bit 30] Maximum Efficiency Frequency Log When set, indicates that\r | |
| 2138 | /// the Maximum Efficiency Frequency Status bit has asserted since the log\r | |
| 2139 | /// bit was last cleared. This log bit will remain set until cleared by\r | |
| 2140 | /// software writing 0.\r | |
| 2141 | ///\r | |
| 2142 | UINT32 MaximumEfficiencyFrequencyLog:1;\r | |
| 2143 | UINT32 Reserved4:1;\r | |
| 2144 | UINT32 Reserved5:32;\r | |
| 2145 | } Bits;\r | |
| 2146 | ///\r | |
| 2147 | /// All bit fields as a 32-bit value\r | |
| 2148 | ///\r | |
| 2149 | UINT32 Uint32;\r | |
| 2150 | ///\r | |
| 2151 | /// All bit fields as a 64-bit value\r | |
| 2152 | ///\r | |
| 2153 | UINT64 Uint64;\r | |
| 2154 | } MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER;\r | |
| 2155 | \r | |
| 2156 | \r | |
| 2157 | /**\r | |
| 2158 | Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch\r | |
| 2159 | record registers on the last branch record stack. The From_IP part of the\r | |
| 2160 | stack contains pointers to the source instruction . See also: - Last Branch\r | |
| 2161 | Record Stack TOS at 1C9H - Section 17.6 and record format in Section\r | |
| 2162 | 17.4.8.1.\r | |
| 2163 | \r | |
| 2164 | @param ECX MSR_GOLDMONT_LASTBRANCH_n_FROM_IP\r | |
| 2165 | @param EAX Lower 32-bits of MSR value.\r | |
| 2166 | Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.\r | |
| 2167 | @param EDX Upper 32-bits of MSR value.\r | |
| 2168 | Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.\r | |
| 2169 | \r | |
| 2170 | <b>Example usage</b>\r | |
| 2171 | @code\r | |
| 2172 | MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER Msr;\r | |
| 2173 | \r | |
| 2174 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP);\r | |
| 2175 | AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP, Msr.Uint64);\r | |
| 2176 | @endcode\r | |
| 2177 | @note MSR_GOLDMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r | |
| 2178 | MSR_GOLDMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r | |
| 2179 | MSR_GOLDMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r | |
| 2180 | MSR_GOLDMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r | |
| 2181 | MSR_GOLDMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r | |
| 2182 | MSR_GOLDMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r | |
| 2183 | MSR_GOLDMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r | |
| 2184 | MSR_GOLDMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r | |
| 2185 | MSR_GOLDMONT_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r | |
| 2186 | MSR_GOLDMONT_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r | |
| 2187 | MSR_GOLDMONT_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r | |
| 2188 | MSR_GOLDMONT_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r | |
| 2189 | MSR_GOLDMONT_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r | |
| 2190 | MSR_GOLDMONT_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r | |
| 2191 | MSR_GOLDMONT_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r | |
| 2192 | MSR_GOLDMONT_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r | |
| 2193 | MSR_GOLDMONT_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.\r | |
| 2194 | MSR_GOLDMONT_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.\r | |
| 2195 | MSR_GOLDMONT_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.\r | |
| 2196 | MSR_GOLDMONT_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.\r | |
| 2197 | MSR_GOLDMONT_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.\r | |
| 2198 | MSR_GOLDMONT_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.\r | |
| 2199 | MSR_GOLDMONT_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.\r | |
| 2200 | MSR_GOLDMONT_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.\r | |
| 2201 | MSR_GOLDMONT_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.\r | |
| 2202 | MSR_GOLDMONT_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.\r | |
| 2203 | MSR_GOLDMONT_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.\r | |
| 2204 | MSR_GOLDMONT_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.\r | |
| 2205 | MSR_GOLDMONT_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.\r | |
| 2206 | MSR_GOLDMONT_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.\r | |
| 2207 | MSR_GOLDMONT_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.\r | |
| 2208 | MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r | |
| 2209 | @{\r | |
| 2210 | **/\r | |
| 2211 | #define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 0x00000680\r | |
| 2212 | #define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP 0x00000681\r | |
| 2213 | #define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP 0x00000682\r | |
| 2214 | #define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP 0x00000683\r | |
| 2215 | #define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP 0x00000684\r | |
| 2216 | #define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP 0x00000685\r | |
| 2217 | #define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP 0x00000686\r | |
| 2218 | #define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP 0x00000687\r | |
| 2219 | #define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP 0x00000688\r | |
| 2220 | #define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP 0x00000689\r | |
| 2221 | #define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP 0x0000068A\r | |
| 2222 | #define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP 0x0000068B\r | |
| 2223 | #define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP 0x0000068C\r | |
| 2224 | #define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP 0x0000068D\r | |
| 2225 | #define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP 0x0000068E\r | |
| 2226 | #define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP 0x0000068F\r | |
| 2227 | #define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP 0x00000690\r | |
| 2228 | #define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP 0x00000691\r | |
| 2229 | #define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP 0x00000692\r | |
| 2230 | #define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP 0x00000693\r | |
| 2231 | #define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP 0x00000694\r | |
| 2232 | #define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP 0x00000695\r | |
| 2233 | #define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP 0x00000696\r | |
| 2234 | #define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP 0x00000697\r | |
| 2235 | #define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP 0x00000698\r | |
| 2236 | #define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP 0x00000699\r | |
| 2237 | #define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP 0x0000069A\r | |
| 2238 | #define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP 0x0000069B\r | |
| 2239 | #define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP 0x0000069C\r | |
| 2240 | #define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP 0x0000069D\r | |
| 2241 | #define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP 0x0000069E\r | |
| 2242 | #define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP 0x0000069F\r | |
| 2243 | /// @}\r | |
| 2244 | \r | |
| 2245 | /**\r | |
| 2246 | MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_FROM_IP\r | |
| 2247 | to #MSR_GOLDMONT_LASTBRANCH_31_FROM_IP.\r | |
| 2248 | **/\r | |
| 2249 | typedef union {\r | |
| 2250 | ///\r | |
| 2251 | /// Individual bit fields\r | |
| 2252 | ///\r | |
| 2253 | struct {\r | |
| 2254 | ///\r | |
| 2255 | /// [Bit 31:0] From Linear Address (R/W).\r | |
| 2256 | ///\r | |
| 2257 | UINT32 FromLinearAddress:32;\r | |
| 2258 | ///\r | |
| 2259 | /// [Bit 47:32] From Linear Address (R/W).\r | |
| 2260 | ///\r | |
| 2261 | UINT32 FromLinearAddressHi:16;\r | |
| 2262 | ///\r | |
| 2263 | /// [Bits 62:48] Signed extension of bits 47:0.\r | |
| 2264 | ///\r | |
| 2265 | UINT32 SignedExtension:15;\r | |
| 2266 | ///\r | |
| 2267 | /// [Bit 63] Mispred.\r | |
| 2268 | ///\r | |
| 2269 | UINT32 Mispred:1;\r | |
| 2270 | } Bits;\r | |
| 2271 | ///\r | |
| 2272 | /// All bit fields as a 32-bit value\r | |
| 2273 | ///\r | |
| 2274 | UINT32 Uint32;\r | |
| 2275 | ///\r | |
| 2276 | /// All bit fields as a 64-bit value\r | |
| 2277 | ///\r | |
| 2278 | UINT64 Uint64;\r | |
| 2279 | } MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER;\r | |
| 2280 | \r | |
| 2281 | \r | |
| 2282 | /**\r | |
| 2283 | Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record\r | |
| 2284 | registers on the last branch record stack. The To_IP part of the stack\r | |
| 2285 | contains pointers to the Destination instruction and elapsed cycles from\r | |
| 2286 | last LBR update. See also: - Section 17.6.\r | |
| 2287 | \r | |
| 2288 | @param ECX MSR_GOLDMONT_LASTBRANCH_n_TO_IP\r | |
| 2289 | @param EAX Lower 32-bits of MSR value.\r | |
| 2290 | Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.\r | |
| 2291 | @param EDX Upper 32-bits of MSR value.\r | |
| 2292 | Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.\r | |
| 2293 | \r | |
| 2294 | <b>Example usage</b>\r | |
| 2295 | @code\r | |
| 2296 | MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER Msr;\r | |
| 2297 | \r | |
| 2298 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP);\r | |
| 2299 | AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP, Msr.Uint64);\r | |
| 2300 | @endcode\r | |
| 2301 | @note MSR_GOLDMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r | |
| 2302 | MSR_GOLDMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r | |
| 2303 | MSR_GOLDMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r | |
| 2304 | MSR_GOLDMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r | |
| 2305 | MSR_GOLDMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r | |
| 2306 | MSR_GOLDMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r | |
| 2307 | MSR_GOLDMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r | |
| 2308 | MSR_GOLDMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r | |
| 2309 | MSR_GOLDMONT_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r | |
| 2310 | MSR_GOLDMONT_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r | |
| 2311 | MSR_GOLDMONT_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r | |
| 2312 | MSR_GOLDMONT_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r | |
| 2313 | MSR_GOLDMONT_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r | |
| 2314 | MSR_GOLDMONT_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r | |
| 2315 | MSR_GOLDMONT_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r | |
| 2316 | MSR_GOLDMONT_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r | |
| 2317 | MSR_GOLDMONT_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.\r | |
| 2318 | MSR_GOLDMONT_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.\r | |
| 2319 | MSR_GOLDMONT_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.\r | |
| 2320 | MSR_GOLDMONT_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.\r | |
| 2321 | MSR_GOLDMONT_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.\r | |
| 2322 | MSR_GOLDMONT_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.\r | |
| 2323 | MSR_GOLDMONT_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.\r | |
| 2324 | MSR_GOLDMONT_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.\r | |
| 2325 | MSR_GOLDMONT_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.\r | |
| 2326 | MSR_GOLDMONT_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.\r | |
| 2327 | MSR_GOLDMONT_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.\r | |
| 2328 | MSR_GOLDMONT_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.\r | |
| 2329 | MSR_GOLDMONT_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.\r | |
| 2330 | MSR_GOLDMONT_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.\r | |
| 2331 | MSR_GOLDMONT_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.\r | |
| 2332 | MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r | |
| 2333 | @{\r | |
| 2334 | **/\r | |
| 2335 | #define MSR_GOLDMONT_LASTBRANCH_0_TO_IP 0x000006C0\r | |
| 2336 | #define MSR_GOLDMONT_LASTBRANCH_1_TO_IP 0x000006C1\r | |
| 2337 | #define MSR_GOLDMONT_LASTBRANCH_2_TO_IP 0x000006C2\r | |
| 2338 | #define MSR_GOLDMONT_LASTBRANCH_3_TO_IP 0x000006C3\r | |
| 2339 | #define MSR_GOLDMONT_LASTBRANCH_4_TO_IP 0x000006C4\r | |
| 2340 | #define MSR_GOLDMONT_LASTBRANCH_5_TO_IP 0x000006C5\r | |
| 2341 | #define MSR_GOLDMONT_LASTBRANCH_6_TO_IP 0x000006C6\r | |
| 2342 | #define MSR_GOLDMONT_LASTBRANCH_7_TO_IP 0x000006C7\r | |
| 2343 | #define MSR_GOLDMONT_LASTBRANCH_8_TO_IP 0x000006C8\r | |
| 2344 | #define MSR_GOLDMONT_LASTBRANCH_9_TO_IP 0x000006C9\r | |
| 2345 | #define MSR_GOLDMONT_LASTBRANCH_10_TO_IP 0x000006CA\r | |
| 2346 | #define MSR_GOLDMONT_LASTBRANCH_11_TO_IP 0x000006CB\r | |
| 2347 | #define MSR_GOLDMONT_LASTBRANCH_12_TO_IP 0x000006CC\r | |
| 2348 | #define MSR_GOLDMONT_LASTBRANCH_13_TO_IP 0x000006CD\r | |
| 2349 | #define MSR_GOLDMONT_LASTBRANCH_14_TO_IP 0x000006CE\r | |
| 2350 | #define MSR_GOLDMONT_LASTBRANCH_15_TO_IP 0x000006CF\r | |
| 2351 | #define MSR_GOLDMONT_LASTBRANCH_16_TO_IP 0x000006D0\r | |
| 2352 | #define MSR_GOLDMONT_LASTBRANCH_17_TO_IP 0x000006D1\r | |
| 2353 | #define MSR_GOLDMONT_LASTBRANCH_18_TO_IP 0x000006D2\r | |
| 2354 | #define MSR_GOLDMONT_LASTBRANCH_19_TO_IP 0x000006D3\r | |
| 2355 | #define MSR_GOLDMONT_LASTBRANCH_20_TO_IP 0x000006D4\r | |
| 2356 | #define MSR_GOLDMONT_LASTBRANCH_21_TO_IP 0x000006D5\r | |
| 2357 | #define MSR_GOLDMONT_LASTBRANCH_22_TO_IP 0x000006D6\r | |
| 2358 | #define MSR_GOLDMONT_LASTBRANCH_23_TO_IP 0x000006D7\r | |
| 2359 | #define MSR_GOLDMONT_LASTBRANCH_24_TO_IP 0x000006D8\r | |
| 2360 | #define MSR_GOLDMONT_LASTBRANCH_25_TO_IP 0x000006D9\r | |
| 2361 | #define MSR_GOLDMONT_LASTBRANCH_26_TO_IP 0x000006DA\r | |
| 2362 | #define MSR_GOLDMONT_LASTBRANCH_27_TO_IP 0x000006DB\r | |
| 2363 | #define MSR_GOLDMONT_LASTBRANCH_28_TO_IP 0x000006DC\r | |
| 2364 | #define MSR_GOLDMONT_LASTBRANCH_29_TO_IP 0x000006DD\r | |
| 2365 | #define MSR_GOLDMONT_LASTBRANCH_30_TO_IP 0x000006DE\r | |
| 2366 | #define MSR_GOLDMONT_LASTBRANCH_31_TO_IP 0x000006DF\r | |
| 2367 | /// @}\r | |
| 2368 | \r | |
| 2369 | /**\r | |
| 2370 | MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_TO_IP to\r | |
| 2371 | #MSR_GOLDMONT_LASTBRANCH_31_TO_IP.\r | |
| 2372 | **/\r | |
| 2373 | typedef union {\r | |
| 2374 | ///\r | |
| 2375 | /// Individual bit fields\r | |
| 2376 | ///\r | |
| 2377 | struct {\r | |
| 2378 | ///\r | |
| 2379 | /// [Bit 31:0] Target Linear Address (R/W).\r | |
| 2380 | ///\r | |
| 2381 | UINT32 TargetLinearAddress:32;\r | |
| 2382 | ///\r | |
| 2383 | /// [Bit 47:32] Target Linear Address (R/W).\r | |
| 2384 | ///\r | |
| 2385 | UINT32 TargetLinearAddressHi:16;\r | |
| 2386 | ///\r | |
| 2387 | /// [Bits 63:48] Elapsed cycles from last update to the LBR.\r | |
| 2388 | ///\r | |
| 2389 | UINT32 ElapsedCycles:16;\r | |
| 2390 | } Bits;\r | |
| 2391 | ///\r | |
| 2392 | /// All bit fields as a 32-bit value\r | |
| 2393 | ///\r | |
| 2394 | UINT32 Uint32;\r | |
| 2395 | ///\r | |
| 2396 | /// All bit fields as a 64-bit value\r | |
| 2397 | ///\r | |
| 2398 | UINT64 Uint64;\r | |
| 2399 | } MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER;\r | |
| 2400 | \r | |
| 2401 | \r | |
| 2402 | /**\r | |
| 2403 | Core. Resource Association Register (R/W).\r | |
| 2404 | \r | |
| 2405 | @param ECX MSR_GOLDMONT_IA32_PQR_ASSOC (0x00000C8F)\r | |
| 2406 | @param EAX Lower 32-bits of MSR value.\r | |
| 2407 | Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.\r | |
| 2408 | @param EDX Upper 32-bits of MSR value.\r | |
| 2409 | Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.\r | |
| 2410 | \r | |
| 2411 | <b>Example usage</b>\r | |
| 2412 | @code\r | |
| 2413 | MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER Msr;\r | |
| 2414 | \r | |
| 2415 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC);\r | |
| 2416 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC, Msr.Uint64);\r | |
| 2417 | @endcode\r | |
| 2418 | @note MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r | |
| 2419 | **/\r | |
| 2420 | #define MSR_GOLDMONT_IA32_PQR_ASSOC 0x00000C8F\r | |
| 2421 | \r | |
| 2422 | /**\r | |
| 2423 | MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC\r | |
| 2424 | **/\r | |
| 2425 | typedef union {\r | |
| 2426 | ///\r | |
| 2427 | /// Individual bit fields\r | |
| 2428 | ///\r | |
| 2429 | struct {\r | |
| 2430 | UINT32 Reserved1:32;\r | |
| 2431 | ///\r | |
| 2432 | /// [Bits 33:32] COS (R/W).\r | |
| 2433 | ///\r | |
| 2434 | UINT32 COS:2;\r | |
| 2435 | UINT32 Reserved2:30;\r | |
| 2436 | } Bits;\r | |
| 2437 | ///\r | |
| 2438 | /// All bit fields as a 64-bit value\r | |
| 2439 | ///\r | |
| 2440 | UINT64 Uint64;\r | |
| 2441 | } MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER;\r | |
| 2442 | \r | |
| 2443 | \r | |
| 2444 | /**\r | |
| 2445 | Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r | |
| 2446 | ECX=1):EDX.COS_MAX[15:0] >=n.\r | |
| 2447 | \r | |
| 2448 | @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_n\r | |
| 2449 | @param EAX Lower 32-bits of MSR value.\r | |
| 2450 | Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.\r | |
| 2451 | @param EDX Upper 32-bits of MSR value.\r | |
| 2452 | Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.\r | |
| 2453 | \r | |
| 2454 | <b>Example usage</b>\r | |
| 2455 | @code\r | |
| 2456 | MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER Msr;\r | |
| 2457 | \r | |
| 2458 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n);\r | |
| 2459 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n, Msr.Uint64);\r | |
| 2460 | @endcode\r | |
| 2461 | @note MSR_GOLDMONT_IA32_L2_QOS_MASK_0 is defined as IA32_L2_QOS_MASK_0 in SDM.\r | |
| 2462 | MSR_GOLDMONT_IA32_L2_QOS_MASK_1 is defined as IA32_L2_QOS_MASK_1 in SDM.\r | |
| 2463 | MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM.\r | |
| 2464 | @{\r | |
| 2465 | **/\r | |
| 2466 | #define MSR_GOLDMONT_IA32_L2_QOS_MASK_0 0x00000D10\r | |
| 2467 | #define MSR_GOLDMONT_IA32_L2_QOS_MASK_1 0x00000D11\r | |
| 2468 | #define MSR_GOLDMONT_IA32_L2_QOS_MASK_2 0x00000D12\r | |
| 2469 | /// @}\r | |
| 2470 | \r | |
| 2471 | /**\r | |
| 2472 | MSR information returned for MSR indexes #MSR_GOLDMONT_IA32_L2_QOS_MASK_0 to\r | |
| 2473 | #MSR_GOLDMONT_IA32_L2_QOS_MASK_2.\r | |
| 2474 | **/\r | |
| 2475 | typedef union {\r | |
| 2476 | ///\r | |
| 2477 | /// Individual bit fields\r | |
| 2478 | ///\r | |
| 2479 | struct {\r | |
| 2480 | ///\r | |
| 2481 | /// [Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement\r | |
| 2482 | ///\r | |
| 2483 | UINT32 CBM:8;\r | |
| 2484 | UINT32 Reserved1:24;\r | |
| 2485 | UINT32 Reserved2:32;\r | |
| 2486 | } Bits;\r | |
| 2487 | ///\r | |
| 2488 | /// All bit fields as a 32-bit value\r | |
| 2489 | ///\r | |
| 2490 | UINT32 Uint32;\r | |
| 2491 | ///\r | |
| 2492 | /// All bit fields as a 64-bit value\r | |
| 2493 | ///\r | |
| 2494 | UINT64 Uint64;\r | |
| 2495 | } MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER;\r | |
| 2496 | \r | |
| 2497 | \r | |
| 2498 | /**\r | |
| 2499 | Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H,\r | |
| 2500 | ECX=1):EDX.COS_MAX[15:0] >=3.\r | |
| 2501 | \r | |
| 2502 | @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_3\r | |
| 2503 | @param EAX Lower 32-bits of MSR value.\r | |
| 2504 | Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.\r | |
| 2505 | @param EDX Upper 32-bits of MSR value.\r | |
| 2506 | Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.\r | |
| 2507 | \r | |
| 2508 | <b>Example usage</b>\r | |
| 2509 | @code\r | |
| 2510 | MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER Msr;\r | |
| 2511 | \r | |
| 2512 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3);\r | |
| 2513 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3, Msr.Uint64);\r | |
| 2514 | @endcode\r | |
| 2515 | @note MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM.\r | |
| 2516 | **/\r | |
| 2517 | #define MSR_GOLDMONT_IA32_L2_QOS_MASK_3 0x00000D13\r | |
| 2518 | \r | |
| 2519 | /**\r | |
| 2520 | MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3.\r | |
| 2521 | **/\r | |
| 2522 | typedef union {\r | |
| 2523 | ///\r | |
| 2524 | /// Individual bit fields\r | |
| 2525 | ///\r | |
| 2526 | struct {\r | |
| 2527 | ///\r | |
| 2528 | /// [Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement\r | |
| 2529 | ///\r | |
| 2530 | UINT32 CBM:20;\r | |
| 2531 | UINT32 Reserved1:12;\r | |
| 2532 | UINT32 Reserved2:32;\r | |
| 2533 | } Bits;\r | |
| 2534 | ///\r | |
| 2535 | /// All bit fields as a 32-bit value\r | |
| 2536 | ///\r | |
| 2537 | UINT32 Uint32;\r | |
| 2538 | ///\r | |
| 2539 | /// All bit fields as a 64-bit value\r | |
| 2540 | ///\r | |
| 2541 | UINT64 Uint64;\r | |
| 2542 | } MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER;\r | |
| 2543 | \r | |
| 2544 | \r | |
| 2545 | #endif\r |