projects / mirror_edk2.git / blame
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| bd946618 MK |
1 | /** @file\r |
| 2 | MSR Definitions for Intel processors based on the Nehalem microarchitecture.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| ba1a2d11 | 9 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| 0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| bd946618 MK |
11 | \r |
| 12 | @par Specification Reference:\r | |
| ba1a2d11 ED |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
| bd946618 MK |
15 | \r |
| 16 | **/\r | |
| 17 | \r | |
| 18 | #ifndef __NEHALEM_MSR_H__\r | |
| 19 | #define __NEHALEM_MSR_H__\r | |
| 20 | \r | |
| 21 | #include <Register/ArchitecturalMsr.h>\r | |
| 22 | \r | |
| f4c982bf JF |
23 | /**\r |
| 24 | Is Intel processors based on the Nehalem microarchitecture?\r | |
| 25 | \r | |
| 26 | @param DisplayFamily Display Family ID\r | |
| 27 | @param DisplayModel Display Model ID\r | |
| 28 | \r | |
| 29 | @retval TRUE Yes, it is.\r | |
| 30 | @retval FALSE No, it isn't.\r | |
| 31 | **/\r | |
| 32 | #define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
| 33 | (DisplayFamily == 0x06 && \\r | |
| 34 | ( \\r | |
| 35 | DisplayModel == 0x1A || \\r | |
| 36 | DisplayModel == 0x1E || \\r | |
| 37 | DisplayModel == 0x1F || \\r | |
| 38 | DisplayModel == 0x2E \\r | |
| 39 | ) \\r | |
| 40 | )\r | |
| 41 | \r | |
| bd946618 MK |
42 | /**\r |
| 43 | Package. Model Specific Platform ID (R).\r | |
| 44 | \r | |
| 45 | @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017)\r | |
| 46 | @param EAX Lower 32-bits of MSR value.\r | |
| 47 | Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.\r | |
| 48 | @param EDX Upper 32-bits of MSR value.\r | |
| 49 | Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.\r | |
| 50 | \r | |
| 51 | <b>Example usage</b>\r | |
| 52 | @code\r | |
| 53 | MSR_NEHALEM_PLATFORM_ID_REGISTER Msr;\r | |
| 54 | \r | |
| 55 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);\r | |
| 56 | @endcode\r | |
| c2aa191b | 57 | @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r |
| bd946618 MK |
58 | **/\r |
| 59 | #define MSR_NEHALEM_PLATFORM_ID 0x00000017\r | |
| 60 | \r | |
| 61 | /**\r | |
| 62 | MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID\r | |
| 63 | **/\r | |
| 64 | typedef union {\r | |
| 65 | ///\r | |
| 66 | /// Individual bit fields\r | |
| 67 | ///\r | |
| 68 | struct {\r | |
| 69 | UINT32 Reserved1:32;\r | |
| 70 | UINT32 Reserved2:18;\r | |
| 71 | ///\r | |
| ba1a2d11 | 72 | /// [Bits 52:50] See Table 2-2.\r |
| bd946618 MK |
73 | ///\r |
| 74 | UINT32 PlatformId:3;\r | |
| 75 | UINT32 Reserved3:11;\r | |
| 76 | } Bits;\r | |
| 77 | ///\r | |
| 78 | /// All bit fields as a 64-bit value\r | |
| 79 | ///\r | |
| 80 | UINT64 Uint64;\r | |
| 81 | } MSR_NEHALEM_PLATFORM_ID_REGISTER;\r | |
| 82 | \r | |
| 83 | \r | |
| 84 | /**\r | |
| 85 | Thread. SMI Counter (R/O).\r | |
| 86 | \r | |
| 87 | @param ECX MSR_NEHALEM_SMI_COUNT (0x00000034)\r | |
| 88 | @param EAX Lower 32-bits of MSR value.\r | |
| 89 | Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.\r | |
| 90 | @param EDX Upper 32-bits of MSR value.\r | |
| 91 | Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.\r | |
| 92 | \r | |
| 93 | <b>Example usage</b>\r | |
| 94 | @code\r | |
| 95 | MSR_NEHALEM_SMI_COUNT_REGISTER Msr;\r | |
| 96 | \r | |
| 97 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);\r | |
| 98 | @endcode\r | |
| c2aa191b | 99 | @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r |
| bd946618 MK |
100 | **/\r |
| 101 | #define MSR_NEHALEM_SMI_COUNT 0x00000034\r | |
| 102 | \r | |
| 103 | /**\r | |
| 104 | MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT\r | |
| 105 | **/\r | |
| 106 | typedef union {\r | |
| 107 | ///\r | |
| 108 | /// Individual bit fields\r | |
| 109 | ///\r | |
| 110 | struct {\r | |
| 111 | ///\r | |
| 112 | /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last\r | |
| 113 | /// RESET.\r | |
| 114 | ///\r | |
| 115 | UINT32 SMICount:32;\r | |
| 116 | UINT32 Reserved:32;\r | |
| 117 | } Bits;\r | |
| 118 | ///\r | |
| 119 | /// All bit fields as a 32-bit value\r | |
| 120 | ///\r | |
| 121 | UINT32 Uint32;\r | |
| 122 | ///\r | |
| 123 | /// All bit fields as a 64-bit value\r | |
| 124 | ///\r | |
| 125 | UINT64 Uint64;\r | |
| 126 | } MSR_NEHALEM_SMI_COUNT_REGISTER;\r | |
| 127 | \r | |
| 128 | \r | |
| 129 | /**\r | |
| 130 | Package. see http://biosbits.org.\r | |
| 131 | \r | |
| 132 | @param ECX MSR_NEHALEM_PLATFORM_INFO (0x000000CE)\r | |
| 133 | @param EAX Lower 32-bits of MSR value.\r | |
| 134 | Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.\r | |
| 135 | @param EDX Upper 32-bits of MSR value.\r | |
| 136 | Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.\r | |
| 137 | \r | |
| 138 | <b>Example usage</b>\r | |
| 139 | @code\r | |
| 140 | MSR_NEHALEM_PLATFORM_INFO_REGISTER Msr;\r | |
| 141 | \r | |
| 142 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);\r | |
| 143 | AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);\r | |
| 144 | @endcode\r | |
| c2aa191b | 145 | @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r |
| bd946618 MK |
146 | **/\r |
| 147 | #define MSR_NEHALEM_PLATFORM_INFO 0x000000CE\r | |
| 148 | \r | |
| 149 | /**\r | |
| 150 | MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO\r | |
| 151 | **/\r | |
| 152 | typedef union {\r | |
| 153 | ///\r | |
| 154 | /// Individual bit fields\r | |
| 155 | ///\r | |
| 156 | struct {\r | |
| 157 | UINT32 Reserved1:8;\r | |
| 158 | ///\r | |
| 159 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r | |
| 160 | /// of the frequency that invariant TSC runs at. The invariant TSC\r | |
| 161 | /// frequency can be computed by multiplying this ratio by 133.33 MHz.\r | |
| 162 | ///\r | |
| 163 | UINT32 MaximumNonTurboRatio:8;\r | |
| 164 | UINT32 Reserved2:12;\r | |
| 165 | ///\r | |
| 166 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r | |
| 167 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r | |
| 168 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r | |
| 169 | /// Turbo mode is disabled.\r | |
| 170 | ///\r | |
| 171 | UINT32 RatioLimit:1;\r | |
| 172 | ///\r | |
| 173 | /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)\r | |
| 174 | /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are\r | |
| 175 | /// programmable, and when set to 0, indicates TDC and TDP Limits for\r | |
| 176 | /// Turbo mode are not programmable.\r | |
| 177 | ///\r | |
| 178 | UINT32 TDC_TDPLimit:1;\r | |
| 179 | UINT32 Reserved3:2;\r | |
| 180 | UINT32 Reserved4:8;\r | |
| 181 | ///\r | |
| 182 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r | |
| 183 | /// minimum ratio (maximum efficiency) that the processor can operates, in\r | |
| 184 | /// units of 133.33MHz.\r | |
| 185 | ///\r | |
| 186 | UINT32 MaximumEfficiencyRatio:8;\r | |
| 187 | UINT32 Reserved5:16;\r | |
| 188 | } Bits;\r | |
| 189 | ///\r | |
| 190 | /// All bit fields as a 64-bit value\r | |
| 191 | ///\r | |
| 192 | UINT64 Uint64;\r | |
| 193 | } MSR_NEHALEM_PLATFORM_INFO_REGISTER;\r | |
| 194 | \r | |
| 195 | \r | |
| 196 | /**\r | |
| 197 | Core. C-State Configuration Control (R/W) Note: C-state values are\r | |
| 198 | processor specific C-state code names, unrelated to MWAIT extension C-state\r | |
| 199 | parameters or ACPI CStates. See http://biosbits.org.\r | |
| 200 | \r | |
| 201 | @param ECX MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
| 202 | @param EAX Lower 32-bits of MSR value.\r | |
| 203 | Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 204 | @param EDX Upper 32-bits of MSR value.\r | |
| 205 | Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 206 | \r | |
| 207 | <b>Example usage</b>\r | |
| 208 | @code\r | |
| 209 | MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
| 210 | \r | |
| 211 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);\r | |
| 212 | AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
| 213 | @endcode\r | |
| c2aa191b | 214 | @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r |
| bd946618 MK |
215 | **/\r |
| 216 | #define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
| 217 | \r | |
| 218 | /**\r | |
| 219 | MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL\r | |
| 220 | **/\r | |
| 221 | typedef union {\r | |
| 222 | ///\r | |
| 223 | /// Individual bit fields\r | |
| 224 | ///\r | |
| 225 | struct {\r | |
| 226 | ///\r | |
| 227 | /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r | |
| 228 | /// processor-specific C-state code name (consuming the least power). for\r | |
| 229 | /// the package. The default is set as factory-configured package C-state\r | |
| 230 | /// limit. The following C-state code name encodings are supported: 000b:\r | |
| 231 | /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)\r | |
| 232 | /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package\r | |
| 233 | /// C-state limit. Note: This field cannot be used to limit package\r | |
| 234 | /// C-state to C3.\r | |
| 235 | ///\r | |
| 236 | UINT32 Limit:3;\r | |
| 237 | UINT32 Reserved1:7;\r | |
| 238 | ///\r | |
| 239 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r | |
| 240 | /// IO_read instructions sent to IO register specified by\r | |
| 241 | /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r | |
| 242 | ///\r | |
| 243 | UINT32 IO_MWAIT:1;\r | |
| 244 | UINT32 Reserved2:4;\r | |
| 245 | ///\r | |
| 246 | /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r | |
| 247 | /// until next reset.\r | |
| 248 | ///\r | |
| 249 | UINT32 CFGLock:1;\r | |
| 250 | UINT32 Reserved3:8;\r | |
| 251 | ///\r | |
| 252 | /// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores\r | |
| 253 | /// in a deep C-State will wake only when the event message is destined\r | |
| 254 | /// for that core. When 0, all processor cores in a deep C-State will wake\r | |
| 255 | /// for an event message.\r | |
| 256 | ///\r | |
| 257 | UINT32 InterruptFiltering:1;\r | |
| 258 | ///\r | |
| 259 | /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r | |
| 260 | /// will conditionally demote C6/C7 requests to C3 based on uncore\r | |
| 261 | /// auto-demote information.\r | |
| 262 | ///\r | |
| 263 | UINT32 C3AutoDemotion:1;\r | |
| 264 | ///\r | |
| 265 | /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r | |
| 266 | /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r | |
| 267 | /// auto-demote information.\r | |
| 268 | ///\r | |
| 269 | UINT32 C1AutoDemotion:1;\r | |
| 0f16be6d HW |
270 | ///\r |
| 271 | /// [Bit 27] Enable C3 Undemotion (R/W).\r | |
| 272 | ///\r | |
| 273 | UINT32 C3Undemotion:1;\r | |
| 274 | ///\r | |
| 275 | /// [Bit 28] Enable C1 Undemotion (R/W).\r | |
| 276 | ///\r | |
| 277 | UINT32 C1Undemotion:1;\r | |
| 278 | ///\r | |
| 279 | /// [Bit 29] Package C State Demotion Enable (R/W).\r | |
| 280 | ///\r | |
| 281 | UINT32 CStateDemotion:1;\r | |
| 282 | ///\r | |
| 283 | /// [Bit 30] Package C State UnDemotion Enable (R/W).\r | |
| 284 | ///\r | |
| 285 | UINT32 CStateUndemotion:1;\r | |
| 286 | UINT32 Reserved4:1;\r | |
| bd946618 MK |
287 | UINT32 Reserved5:32;\r |
| 288 | } Bits;\r | |
| 289 | ///\r | |
| 290 | /// All bit fields as a 32-bit value\r | |
| 291 | ///\r | |
| 292 | UINT32 Uint32;\r | |
| 293 | ///\r | |
| 294 | /// All bit fields as a 64-bit value\r | |
| 295 | ///\r | |
| 296 | UINT64 Uint64;\r | |
| 297 | } MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
| 298 | \r | |
| 299 | \r | |
| 300 | /**\r | |
| 301 | Core. Power Management IO Redirection in C-state (R/W) See\r | |
| 302 | http://biosbits.org.\r | |
| 303 | \r | |
| 304 | @param ECX MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)\r | |
| 305 | @param EAX Lower 32-bits of MSR value.\r | |
| 306 | Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
| 307 | @param EDX Upper 32-bits of MSR value.\r | |
| 308 | Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
| 309 | \r | |
| 310 | <b>Example usage</b>\r | |
| 311 | @code\r | |
| 312 | MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r | |
| 313 | \r | |
| 314 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);\r | |
| 315 | AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r | |
| 316 | @endcode\r | |
| c2aa191b | 317 | @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r |
| bd946618 MK |
318 | **/\r |
| 319 | #define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4\r | |
| 320 | \r | |
| 321 | /**\r | |
| 322 | MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE\r | |
| 323 | **/\r | |
| 324 | typedef union {\r | |
| 325 | ///\r | |
| 326 | /// Individual bit fields\r | |
| 327 | ///\r | |
| 328 | struct {\r | |
| 329 | ///\r | |
| 330 | /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r | |
| 331 | /// visible to software for IO redirection. If IO MWAIT Redirection is\r | |
| 332 | /// enabled, reads to this address will be consumed by the power\r | |
| 333 | /// management logic and decoded to MWAIT instructions. When IO port\r | |
| 334 | /// address redirection is enabled, this is the IO port address reported\r | |
| 335 | /// to the OS/software.\r | |
| 336 | ///\r | |
| 337 | UINT32 Lvl2Base:16;\r | |
| 338 | ///\r | |
| 339 | /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r | |
| 340 | /// maximum C-State code name to be included when IO read to MWAIT\r | |
| 341 | /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3\r | |
| 342 | /// is the max C-State to include 001b - C6 is the max C-State to include\r | |
| 343 | /// 010b - C7 is the max C-State to include.\r | |
| 344 | ///\r | |
| 345 | UINT32 CStateRange:3;\r | |
| 346 | UINT32 Reserved1:13;\r | |
| 347 | UINT32 Reserved2:32;\r | |
| 348 | } Bits;\r | |
| 349 | ///\r | |
| 350 | /// All bit fields as a 32-bit value\r | |
| 351 | ///\r | |
| 352 | UINT32 Uint32;\r | |
| 353 | ///\r | |
| 354 | /// All bit fields as a 64-bit value\r | |
| 355 | ///\r | |
| 356 | UINT64 Uint64;\r | |
| 357 | } MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER;\r | |
| 358 | \r | |
| 359 | \r | |
| 360 | /**\r | |
| 361 | Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
| 362 | functions to be enabled and disabled.\r | |
| 363 | \r | |
| 364 | @param ECX MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)\r | |
| 365 | @param EAX Lower 32-bits of MSR value.\r | |
| 366 | Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.\r | |
| 367 | @param EDX Upper 32-bits of MSR value.\r | |
| 368 | Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.\r | |
| 369 | \r | |
| 370 | <b>Example usage</b>\r | |
| 371 | @code\r | |
| 372 | MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Msr;\r | |
| 373 | \r | |
| 374 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);\r | |
| 375 | AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);\r | |
| 376 | @endcode\r | |
| c2aa191b | 377 | @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
| bd946618 MK |
378 | **/\r |
| 379 | #define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0\r | |
| 380 | \r | |
| 381 | /**\r | |
| 382 | MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE\r | |
| 383 | **/\r | |
| 384 | typedef union {\r | |
| 385 | ///\r | |
| 386 | /// Individual bit fields\r | |
| 387 | ///\r | |
| 388 | struct {\r | |
| 389 | ///\r | |
| ba1a2d11 | 390 | /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.\r |
| bd946618 MK |
391 | ///\r |
| 392 | UINT32 FastStrings:1;\r | |
| 393 | UINT32 Reserved1:2;\r | |
| 394 | ///\r | |
| 395 | /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See\r | |
| ba1a2d11 | 396 | /// Table 2-2. Default value is 1.\r |
| bd946618 MK |
397 | ///\r |
| 398 | UINT32 AutomaticThermalControlCircuit:1;\r | |
| 399 | UINT32 Reserved2:3;\r | |
| 400 | ///\r | |
| ba1a2d11 | 401 | /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.\r |
| bd946618 MK |
402 | ///\r |
| 403 | UINT32 PerformanceMonitoring:1;\r | |
| 404 | UINT32 Reserved3:3;\r | |
| 405 | ///\r | |
| ba1a2d11 | 406 | /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.\r |
| bd946618 MK |
407 | ///\r |
| 408 | UINT32 BTS:1;\r | |
| 409 | ///\r | |
| 0f16be6d | 410 | /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r |
| ba1a2d11 | 411 | /// Table 2-2.\r |
| bd946618 MK |
412 | ///\r |
| 413 | UINT32 PEBS:1;\r | |
| 414 | UINT32 Reserved4:3;\r | |
| 415 | ///\r | |
| 416 | /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r | |
| ba1a2d11 | 417 | /// Table 2-2.\r |
| bd946618 MK |
418 | ///\r |
| 419 | UINT32 EIST:1;\r | |
| 420 | UINT32 Reserved5:1;\r | |
| 421 | ///\r | |
| ba1a2d11 | 422 | /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2.\r |
| bd946618 MK |
423 | ///\r |
| 424 | UINT32 MONITOR:1;\r | |
| 425 | UINT32 Reserved6:3;\r | |
| 426 | ///\r | |
| ba1a2d11 | 427 | /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.\r |
| bd946618 MK |
428 | ///\r |
| 429 | UINT32 LimitCpuidMaxval:1;\r | |
| 430 | ///\r | |
| ba1a2d11 | 431 | /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.\r |
| bd946618 MK |
432 | ///\r |
| 433 | UINT32 xTPR_Message_Disable:1;\r | |
| 434 | UINT32 Reserved7:8;\r | |
| 435 | UINT32 Reserved8:2;\r | |
| 436 | ///\r | |
| ba1a2d11 | 437 | /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.\r |
| bd946618 MK |
438 | ///\r |
| 439 | UINT32 XD:1;\r | |
| 440 | UINT32 Reserved9:3;\r | |
| 441 | ///\r | |
| 442 | /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r | |
| 443 | /// that support Intel Turbo Boost Technology, the turbo mode feature is\r | |
| 444 | /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r | |
| 445 | /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r | |
| 446 | /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r | |
| 447 | /// the power-on default value is used by BIOS to detect hardware support\r | |
| 448 | /// of turbo mode. If power-on default value is 1, turbo mode is available\r | |
| 449 | /// in the processor. If power-on default value is 0, turbo mode is not\r | |
| 450 | /// available.\r | |
| 451 | ///\r | |
| 452 | UINT32 TurboModeDisable:1;\r | |
| 453 | UINT32 Reserved10:25;\r | |
| 454 | } Bits;\r | |
| 455 | ///\r | |
| 456 | /// All bit fields as a 64-bit value\r | |
| 457 | ///\r | |
| 458 | UINT64 Uint64;\r | |
| 459 | } MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER;\r | |
| 460 | \r | |
| 461 | \r | |
| 462 | /**\r | |
| 463 | Thread.\r | |
| 464 | \r | |
| 465 | @param ECX MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)\r | |
| 466 | @param EAX Lower 32-bits of MSR value.\r | |
| 467 | Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.\r | |
| 468 | @param EDX Upper 32-bits of MSR value.\r | |
| 469 | Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.\r | |
| 470 | \r | |
| 471 | <b>Example usage</b>\r | |
| 472 | @code\r | |
| 473 | MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Msr;\r | |
| 474 | \r | |
| 475 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);\r | |
| 476 | AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);\r | |
| 477 | @endcode\r | |
| c2aa191b | 478 | @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r |
| bd946618 MK |
479 | **/\r |
| 480 | #define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2\r | |
| 481 | \r | |
| 482 | /**\r | |
| 483 | MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET\r | |
| 484 | **/\r | |
| 485 | typedef union {\r | |
| 486 | ///\r | |
| 487 | /// Individual bit fields\r | |
| 488 | ///\r | |
| 489 | struct {\r | |
| 490 | UINT32 Reserved1:16;\r | |
| 491 | ///\r | |
| 492 | /// [Bits 23:16] Temperature Target (R) The minimum temperature at which\r | |
| 493 | /// PROCHOT# will be asserted. The value is degree C.\r | |
| 494 | ///\r | |
| 495 | UINT32 TemperatureTarget:8;\r | |
| 496 | UINT32 Reserved2:8;\r | |
| 497 | UINT32 Reserved3:32;\r | |
| 498 | } Bits;\r | |
| 499 | ///\r | |
| 500 | /// All bit fields as a 32-bit value\r | |
| 501 | ///\r | |
| 502 | UINT32 Uint32;\r | |
| 503 | ///\r | |
| 504 | /// All bit fields as a 64-bit value\r | |
| 505 | ///\r | |
| 506 | UINT64 Uint64;\r | |
| 507 | } MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER;\r | |
| 508 | \r | |
| 509 | \r | |
| 510 | /**\r | |
| 511 | Miscellaneous Feature Control (R/W).\r | |
| 512 | \r | |
| 513 | @param ECX MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)\r | |
| 514 | @param EAX Lower 32-bits of MSR value.\r | |
| 515 | Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.\r | |
| 516 | @param EDX Upper 32-bits of MSR value.\r | |
| 517 | Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.\r | |
| 518 | \r | |
| 519 | <b>Example usage</b>\r | |
| 520 | @code\r | |
| 521 | MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Msr;\r | |
| 522 | \r | |
| 523 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);\r | |
| 524 | AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);\r | |
| 525 | @endcode\r | |
| c2aa191b | 526 | @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r |
| bd946618 MK |
527 | **/\r |
| 528 | #define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4\r | |
| 529 | \r | |
| 530 | /**\r | |
| 531 | MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL\r | |
| 532 | **/\r | |
| 533 | typedef union {\r | |
| 534 | ///\r | |
| 535 | /// Individual bit fields\r | |
| 536 | ///\r | |
| 537 | struct {\r | |
| 538 | ///\r | |
| 539 | /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r | |
| 540 | /// L2 hardware prefetcher, which fetches additional lines of code or data\r | |
| 541 | /// into the L2 cache.\r | |
| 542 | ///\r | |
| 543 | UINT32 L2HardwarePrefetcherDisable:1;\r | |
| 544 | ///\r | |
| 545 | /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,\r | |
| 546 | /// disables the adjacent cache line prefetcher, which fetches the cache\r | |
| 547 | /// line that comprises a cache line pair (128 bytes).\r | |
| 548 | ///\r | |
| 549 | UINT32 L2AdjacentCacheLinePrefetcherDisable:1;\r | |
| 550 | ///\r | |
| 551 | /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r | |
| 552 | /// the L1 data cache prefetcher, which fetches the next cache line into\r | |
| 553 | /// L1 data cache.\r | |
| 554 | ///\r | |
| 555 | UINT32 DCUHardwarePrefetcherDisable:1;\r | |
| 556 | ///\r | |
| 557 | /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1\r | |
| 558 | /// data cache IP prefetcher, which uses sequential load history (based on\r | |
| 559 | /// instruction Pointer of previous loads) to determine whether to\r | |
| 560 | /// prefetch additional lines.\r | |
| 561 | ///\r | |
| 562 | UINT32 DCUIPPrefetcherDisable:1;\r | |
| 563 | UINT32 Reserved1:28;\r | |
| 564 | UINT32 Reserved2:32;\r | |
| 565 | } Bits;\r | |
| 566 | ///\r | |
| 567 | /// All bit fields as a 32-bit value\r | |
| 568 | ///\r | |
| 569 | UINT32 Uint32;\r | |
| 570 | ///\r | |
| 571 | /// All bit fields as a 64-bit value\r | |
| 572 | ///\r | |
| 573 | UINT64 Uint64;\r | |
| 574 | } MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER;\r | |
| 575 | \r | |
| 576 | \r | |
| 577 | /**\r | |
| 578 | Thread. Offcore Response Event Select Register (R/W).\r | |
| 579 | \r | |
| 580 | @param ECX MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)\r | |
| 581 | @param EAX Lower 32-bits of MSR value.\r | |
| 582 | @param EDX Upper 32-bits of MSR value.\r | |
| 583 | \r | |
| 584 | <b>Example usage</b>\r | |
| 585 | @code\r | |
| 586 | UINT64 Msr;\r | |
| 587 | \r | |
| 588 | Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);\r | |
| 589 | AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);\r | |
| 590 | @endcode\r | |
| c2aa191b | 591 | @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r |
| bd946618 MK |
592 | **/\r |
| 593 | #define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6\r | |
| 594 | \r | |
| 595 | \r | |
| 596 | /**\r | |
| 597 | See http://biosbits.org.\r | |
| 598 | \r | |
| 599 | @param ECX MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)\r | |
| 600 | @param EAX Lower 32-bits of MSR value.\r | |
| 601 | Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.\r | |
| 602 | @param EDX Upper 32-bits of MSR value.\r | |
| 603 | Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.\r | |
| 604 | \r | |
| 605 | <b>Example usage</b>\r | |
| 606 | @code\r | |
| 607 | MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Msr;\r | |
| 608 | \r | |
| 609 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);\r | |
| 610 | AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);\r | |
| 611 | @endcode\r | |
| c2aa191b | 612 | @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r |
| bd946618 MK |
613 | **/\r |
| 614 | #define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA\r | |
| 615 | \r | |
| 616 | /**\r | |
| 617 | MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT\r | |
| 618 | **/\r | |
| 619 | typedef union {\r | |
| 620 | ///\r | |
| 621 | /// Individual bit fields\r | |
| 622 | ///\r | |
| 623 | struct {\r | |
| 624 | ///\r | |
| 625 | /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,\r | |
| 626 | /// enables hardware coordination of Enhanced Intel Speedstep Technology\r | |
| 627 | /// request from processor cores; When 1, disables hardware coordination\r | |
| 628 | /// of Enhanced Intel Speedstep Technology requests.\r | |
| 629 | ///\r | |
| 630 | UINT32 EISTHardwareCoordinationDisable:1;\r | |
| 631 | ///\r | |
| 632 | /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes\r | |
| 633 | /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with\r | |
| 634 | /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by\r | |
| 635 | /// CPUID.(EAX=06h):ECX[3].\r | |
| 636 | ///\r | |
| 637 | UINT32 EnergyPerformanceBiasEnable:1;\r | |
| 638 | UINT32 Reserved1:30;\r | |
| 639 | UINT32 Reserved2:32;\r | |
| 640 | } Bits;\r | |
| 641 | ///\r | |
| 642 | /// All bit fields as a 32-bit value\r | |
| 643 | ///\r | |
| 644 | UINT32 Uint32;\r | |
| 645 | ///\r | |
| 646 | /// All bit fields as a 64-bit value\r | |
| 647 | ///\r | |
| 648 | UINT64 Uint64;\r | |
| 649 | } MSR_NEHALEM_MISC_PWR_MGMT_REGISTER;\r | |
| 650 | \r | |
| 651 | \r | |
| 652 | /**\r | |
| 653 | See http://biosbits.org.\r | |
| 654 | \r | |
| 655 | @param ECX MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)\r | |
| 656 | @param EAX Lower 32-bits of MSR value.\r | |
| 657 | Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.\r | |
| 658 | @param EDX Upper 32-bits of MSR value.\r | |
| 659 | Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.\r | |
| 660 | \r | |
| 661 | <b>Example usage</b>\r | |
| 662 | @code\r | |
| 663 | MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Msr;\r | |
| 664 | \r | |
| 665 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);\r | |
| 666 | AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);\r | |
| 667 | @endcode\r | |
| c2aa191b | 668 | @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.\r |
| bd946618 MK |
669 | **/\r |
| 670 | #define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC\r | |
| 671 | \r | |
| 672 | /**\r | |
| 673 | MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT\r | |
| 674 | **/\r | |
| 675 | typedef union {\r | |
| 676 | ///\r | |
| 677 | /// Individual bit fields\r | |
| 678 | ///\r | |
| 679 | struct {\r | |
| 680 | ///\r | |
| 681 | /// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt\r | |
| 682 | /// granularity.\r | |
| 683 | ///\r | |
| 684 | UINT32 TDPLimit:15;\r | |
| 685 | ///\r | |
| 686 | /// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0\r | |
| 687 | /// indicates override is not active, and a value = 1 indicates active.\r | |
| 688 | ///\r | |
| 689 | UINT32 TDPLimitOverrideEnable:1;\r | |
| 690 | ///\r | |
| 691 | /// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp\r | |
| 692 | /// granularity.\r | |
| 693 | ///\r | |
| 694 | UINT32 TDCLimit:15;\r | |
| 695 | ///\r | |
| 696 | /// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0\r | |
| 697 | /// indicates override is not active, and a value = 1 indicates active.\r | |
| 698 | ///\r | |
| 699 | UINT32 TDCLimitOverrideEnable:1;\r | |
| 700 | UINT32 Reserved:32;\r | |
| 701 | } Bits;\r | |
| 702 | ///\r | |
| 703 | /// All bit fields as a 32-bit value\r | |
| 704 | ///\r | |
| 705 | UINT32 Uint32;\r | |
| 706 | ///\r | |
| 707 | /// All bit fields as a 64-bit value\r | |
| 708 | ///\r | |
| 709 | UINT64 Uint64;\r | |
| 710 | } MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER;\r | |
| 711 | \r | |
| 712 | \r | |
| 713 | /**\r | |
| 714 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
| 715 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
| 716 | \r | |
| 717 | @param ECX MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)\r | |
| 718 | @param EAX Lower 32-bits of MSR value.\r | |
| 719 | Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 720 | @param EDX Upper 32-bits of MSR value.\r | |
| 721 | Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 722 | \r | |
| 723 | <b>Example usage</b>\r | |
| 724 | @code\r | |
| 725 | MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
| 726 | \r | |
| 727 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);\r | |
| 728 | @endcode\r | |
| c2aa191b | 729 | @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r |
| bd946618 MK |
730 | **/\r |
| 731 | #define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD\r | |
| 732 | \r | |
| 733 | /**\r | |
| 734 | MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT\r | |
| 735 | **/\r | |
| 736 | typedef union {\r | |
| 737 | ///\r | |
| 738 | /// Individual bit fields\r | |
| 739 | ///\r | |
| 740 | struct {\r | |
| 741 | ///\r | |
| 742 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r | |
| 743 | /// limit of 1 core active.\r | |
| 744 | ///\r | |
| 745 | UINT32 Maximum1C:8;\r | |
| 746 | ///\r | |
| 747 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r | |
| 748 | /// limit of 2 core active.\r | |
| 749 | ///\r | |
| 750 | UINT32 Maximum2C:8;\r | |
| 751 | ///\r | |
| 752 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r | |
| 753 | /// limit of 3 core active.\r | |
| 754 | ///\r | |
| 755 | UINT32 Maximum3C:8;\r | |
| 756 | ///\r | |
| 757 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r | |
| 758 | /// limit of 4 core active.\r | |
| 759 | ///\r | |
| 760 | UINT32 Maximum4C:8;\r | |
| 761 | UINT32 Reserved:32;\r | |
| 762 | } Bits;\r | |
| 763 | ///\r | |
| 764 | /// All bit fields as a 32-bit value\r | |
| 765 | ///\r | |
| 766 | UINT32 Uint32;\r | |
| 767 | ///\r | |
| 768 | /// All bit fields as a 64-bit value\r | |
| 769 | ///\r | |
| 770 | UINT64 Uint64;\r | |
| 771 | } MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER;\r | |
| 772 | \r | |
| 773 | \r | |
| 774 | /**\r | |
| ba1a2d11 ED |
775 | Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r |
| 776 | "Filtering of Last Branch Records.".\r | |
| bd946618 MK |
777 | \r |
| 778 | @param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)\r | |
| 779 | @param EAX Lower 32-bits of MSR value.\r | |
| 780 | Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.\r | |
| 781 | @param EDX Upper 32-bits of MSR value.\r | |
| 782 | Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.\r | |
| 783 | \r | |
| 784 | <b>Example usage</b>\r | |
| 785 | @code\r | |
| 786 | MSR_NEHALEM_LBR_SELECT_REGISTER Msr;\r | |
| 787 | \r | |
| 788 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);\r | |
| 789 | AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);\r | |
| 790 | @endcode\r | |
| c2aa191b | 791 | @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r |
| bd946618 MK |
792 | **/\r |
| 793 | #define MSR_NEHALEM_LBR_SELECT 0x000001C8\r | |
| 794 | \r | |
| 795 | /**\r | |
| 796 | MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT\r | |
| 797 | **/\r | |
| 798 | typedef union {\r | |
| 799 | ///\r | |
| 800 | /// Individual bit fields\r | |
| 801 | ///\r | |
| 802 | struct {\r | |
| 803 | ///\r | |
| 804 | /// [Bit 0] CPL_EQ_0.\r | |
| 805 | ///\r | |
| 806 | UINT32 CPL_EQ_0:1;\r | |
| 807 | ///\r | |
| 808 | /// [Bit 1] CPL_NEQ_0.\r | |
| 809 | ///\r | |
| 810 | UINT32 CPL_NEQ_0:1;\r | |
| 811 | ///\r | |
| 812 | /// [Bit 2] JCC.\r | |
| 813 | ///\r | |
| 814 | UINT32 JCC:1;\r | |
| 815 | ///\r | |
| 816 | /// [Bit 3] NEAR_REL_CALL.\r | |
| 817 | ///\r | |
| 818 | UINT32 NEAR_REL_CALL:1;\r | |
| 819 | ///\r | |
| 820 | /// [Bit 4] NEAR_IND_CALL.\r | |
| 821 | ///\r | |
| 822 | UINT32 NEAR_IND_CALL:1;\r | |
| 823 | ///\r | |
| 824 | /// [Bit 5] NEAR_RET.\r | |
| 825 | ///\r | |
| 826 | UINT32 NEAR_RET:1;\r | |
| 827 | ///\r | |
| 828 | /// [Bit 6] NEAR_IND_JMP.\r | |
| 829 | ///\r | |
| 830 | UINT32 NEAR_IND_JMP:1;\r | |
| 831 | ///\r | |
| 832 | /// [Bit 7] NEAR_REL_JMP.\r | |
| 833 | ///\r | |
| 834 | UINT32 NEAR_REL_JMP:1;\r | |
| 835 | ///\r | |
| 836 | /// [Bit 8] FAR_BRANCH.\r | |
| 837 | ///\r | |
| 838 | UINT32 FAR_BRANCH:1;\r | |
| 839 | UINT32 Reserved1:23;\r | |
| 840 | UINT32 Reserved2:32;\r | |
| 841 | } Bits;\r | |
| 842 | ///\r | |
| 843 | /// All bit fields as a 32-bit value\r | |
| 844 | ///\r | |
| 845 | UINT32 Uint32;\r | |
| 846 | ///\r | |
| 847 | /// All bit fields as a 64-bit value\r | |
| 848 | ///\r | |
| 849 | UINT64 Uint64;\r | |
| 850 | } MSR_NEHALEM_LBR_SELECT_REGISTER;\r | |
| 851 | \r | |
| 852 | \r | |
| 853 | /**\r | |
| 854 | Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r | |
| 855 | that points to the MSR containing the most recent branch record. See\r | |
| 856 | MSR_LASTBRANCH_0_FROM_IP (at 680H).\r | |
| 857 | \r | |
| 858 | @param ECX MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)\r | |
| 859 | @param EAX Lower 32-bits of MSR value.\r | |
| 860 | @param EDX Upper 32-bits of MSR value.\r | |
| 861 | \r | |
| 862 | <b>Example usage</b>\r | |
| 863 | @code\r | |
| 864 | UINT64 Msr;\r | |
| 865 | \r | |
| 866 | Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);\r | |
| 867 | AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);\r | |
| 868 | @endcode\r | |
| c2aa191b | 869 | @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r |
| bd946618 MK |
870 | **/\r |
| 871 | #define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9\r | |
| 872 | \r | |
| 873 | \r | |
| 874 | /**\r | |
| 875 | Thread. Last Exception Record From Linear IP (R) Contains a pointer to the\r | |
| 876 | last branch instruction that the processor executed prior to the last\r | |
| 877 | exception that was generated or the last interrupt that was handled.\r | |
| 878 | \r | |
| 879 | @param ECX MSR_NEHALEM_LER_FROM_LIP (0x000001DD)\r | |
| 880 | @param EAX Lower 32-bits of MSR value.\r | |
| 881 | @param EDX Upper 32-bits of MSR value.\r | |
| 882 | \r | |
| 883 | <b>Example usage</b>\r | |
| 884 | @code\r | |
| 885 | UINT64 Msr;\r | |
| 886 | \r | |
| 887 | Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);\r | |
| 888 | @endcode\r | |
| c2aa191b | 889 | @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r |
| bd946618 MK |
890 | **/\r |
| 891 | #define MSR_NEHALEM_LER_FROM_LIP 0x000001DD\r | |
| 892 | \r | |
| 893 | \r | |
| 894 | /**\r | |
| 895 | Thread. Last Exception Record To Linear IP (R) This area contains a pointer\r | |
| 896 | to the target of the last branch instruction that the processor executed\r | |
| 897 | prior to the last exception that was generated or the last interrupt that\r | |
| 898 | was handled.\r | |
| 899 | \r | |
| 900 | @param ECX MSR_NEHALEM_LER_TO_LIP (0x000001DE)\r | |
| 901 | @param EAX Lower 32-bits of MSR value.\r | |
| 902 | @param EDX Upper 32-bits of MSR value.\r | |
| 903 | \r | |
| 904 | <b>Example usage</b>\r | |
| 905 | @code\r | |
| 906 | UINT64 Msr;\r | |
| 907 | \r | |
| 908 | Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);\r | |
| 909 | @endcode\r | |
| c2aa191b | 910 | @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r |
| bd946618 MK |
911 | **/\r |
| 912 | #define MSR_NEHALEM_LER_TO_LIP 0x000001DE\r | |
| 913 | \r | |
| 914 | \r | |
| 915 | /**\r | |
| 916 | Core. Power Control Register. See http://biosbits.org.\r | |
| 917 | \r | |
| 918 | @param ECX MSR_NEHALEM_POWER_CTL (0x000001FC)\r | |
| 919 | @param EAX Lower 32-bits of MSR value.\r | |
| 920 | Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.\r | |
| 921 | @param EDX Upper 32-bits of MSR value.\r | |
| 922 | Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.\r | |
| 923 | \r | |
| 924 | <b>Example usage</b>\r | |
| 925 | @code\r | |
| 926 | MSR_NEHALEM_POWER_CTL_REGISTER Msr;\r | |
| 927 | \r | |
| 928 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);\r | |
| 929 | AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);\r | |
| 930 | @endcode\r | |
| c2aa191b | 931 | @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r |
| bd946618 MK |
932 | **/\r |
| 933 | #define MSR_NEHALEM_POWER_CTL 0x000001FC\r | |
| 934 | \r | |
| 935 | /**\r | |
| 936 | MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL\r | |
| 937 | **/\r | |
| 938 | typedef union {\r | |
| 939 | ///\r | |
| 940 | /// Individual bit fields\r | |
| 941 | ///\r | |
| 942 | struct {\r | |
| 943 | UINT32 Reserved1:1;\r | |
| 944 | ///\r | |
| 945 | /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the\r | |
| 946 | /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology\r | |
| 947 | /// operating point when all execution cores enter MWAIT (C1).\r | |
| 948 | ///\r | |
| 949 | UINT32 C1EEnable:1;\r | |
| 950 | UINT32 Reserved2:30;\r | |
| 951 | UINT32 Reserved3:32;\r | |
| 952 | } Bits;\r | |
| 953 | ///\r | |
| 954 | /// All bit fields as a 32-bit value\r | |
| 955 | ///\r | |
| 956 | UINT32 Uint32;\r | |
| 957 | ///\r | |
| 958 | /// All bit fields as a 64-bit value\r | |
| 959 | ///\r | |
| 960 | UINT64 Uint64;\r | |
| 961 | } MSR_NEHALEM_POWER_CTL_REGISTER;\r | |
| 962 | \r | |
| 963 | \r | |
| bd946618 MK |
964 | /**\r |
| 965 | Thread. (RO).\r | |
| 966 | \r | |
| 0f16be6d | 967 | @param ECX MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)\r |
| bd946618 | 968 | @param EAX Lower 32-bits of MSR value.\r |
| 0f16be6d | 969 | Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r |
| bd946618 | 970 | @param EDX Upper 32-bits of MSR value.\r |
| 0f16be6d | 971 | Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r |
| bd946618 MK |
972 | \r |
| 973 | <b>Example usage</b>\r | |
| 974 | @code\r | |
| 0f16be6d | 975 | MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Msr;\r |
| bd946618 | 976 | \r |
| 0f16be6d | 977 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);\r |
| bd946618 | 978 | @endcode\r |
| 0f16be6d | 979 | @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r |
| bd946618 | 980 | **/\r |
| 0f16be6d | 981 | #define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E\r |
| bd946618 MK |
982 | \r |
| 983 | /**\r | |
| 0f16be6d | 984 | MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS\r |
| bd946618 MK |
985 | **/\r |
| 986 | typedef union {\r | |
| 987 | ///\r | |
| 988 | /// Individual bit fields\r | |
| 989 | ///\r | |
| 990 | struct {\r | |
| 991 | UINT32 Reserved1:32;\r | |
| 992 | UINT32 Reserved2:29;\r | |
| 993 | ///\r | |
| 994 | /// [Bit 61] UNC_Ovf Uncore overflowed if 1.\r | |
| 995 | ///\r | |
| 996 | UINT32 Ovf_Uncore:1;\r | |
| 997 | UINT32 Reserved3:2;\r | |
| 998 | } Bits;\r | |
| 999 | ///\r | |
| 1000 | /// All bit fields as a 64-bit value\r | |
| 1001 | ///\r | |
| 1002 | UINT64 Uint64;\r | |
| 0f16be6d | 1003 | } MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER;\r |
| bd946618 MK |
1004 | \r |
| 1005 | \r | |
| 1006 | /**\r | |
| 1007 | Thread. (R/W).\r | |
| 1008 | \r | |
| 1009 | @param ECX MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)\r | |
| 1010 | @param EAX Lower 32-bits of MSR value.\r | |
| 1011 | Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
| 1012 | @param EDX Upper 32-bits of MSR value.\r | |
| 1013 | Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
| 1014 | \r | |
| 1015 | <b>Example usage</b>\r | |
| 1016 | @code\r | |
| 1017 | MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r | |
| 1018 | \r | |
| 1019 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);\r | |
| 1020 | AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r | |
| 1021 | @endcode\r | |
| c2aa191b | 1022 | @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.\r |
| bd946618 MK |
1023 | **/\r |
| 1024 | #define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390\r | |
| 1025 | \r | |
| 1026 | /**\r | |
| 1027 | MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL\r | |
| 1028 | **/\r | |
| 1029 | typedef union {\r | |
| 1030 | ///\r | |
| 1031 | /// Individual bit fields\r | |
| 1032 | ///\r | |
| 1033 | struct {\r | |
| 1034 | UINT32 Reserved1:32;\r | |
| 1035 | UINT32 Reserved2:29;\r | |
| 1036 | ///\r | |
| 1037 | /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.\r | |
| 1038 | ///\r | |
| 1039 | UINT32 Ovf_Uncore:1;\r | |
| 1040 | UINT32 Reserved3:2;\r | |
| 1041 | } Bits;\r | |
| 1042 | ///\r | |
| 1043 | /// All bit fields as a 64-bit value\r | |
| 1044 | ///\r | |
| 1045 | UINT64 Uint64;\r | |
| 1046 | } MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER;\r | |
| 1047 | \r | |
| 1048 | \r | |
| 1049 | /**\r | |
| ba1a2d11 | 1050 | Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r |
| bd946618 MK |
1051 | \r |
| 1052 | @param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)\r | |
| 1053 | @param EAX Lower 32-bits of MSR value.\r | |
| 1054 | Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.\r | |
| 1055 | @param EDX Upper 32-bits of MSR value.\r | |
| 1056 | Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.\r | |
| 1057 | \r | |
| 1058 | <b>Example usage</b>\r | |
| 1059 | @code\r | |
| 1060 | MSR_NEHALEM_PEBS_ENABLE_REGISTER Msr;\r | |
| 1061 | \r | |
| 1062 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);\r | |
| 1063 | AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);\r | |
| 1064 | @endcode\r | |
| c2aa191b | 1065 | @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r |
| bd946618 MK |
1066 | **/\r |
| 1067 | #define MSR_NEHALEM_PEBS_ENABLE 0x000003F1\r | |
| 1068 | \r | |
| 1069 | /**\r | |
| 1070 | MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE\r | |
| 1071 | **/\r | |
| 1072 | typedef union {\r | |
| 1073 | ///\r | |
| 1074 | /// Individual bit fields\r | |
| 1075 | ///\r | |
| 1076 | struct {\r | |
| 1077 | ///\r | |
| 1078 | /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r | |
| 1079 | ///\r | |
| 1080 | UINT32 PEBS_EN_PMC0:1;\r | |
| 1081 | ///\r | |
| 1082 | /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r | |
| 1083 | ///\r | |
| 1084 | UINT32 PEBS_EN_PMC1:1;\r | |
| 1085 | ///\r | |
| 1086 | /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r | |
| 1087 | ///\r | |
| 1088 | UINT32 PEBS_EN_PMC2:1;\r | |
| 1089 | ///\r | |
| 1090 | /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r | |
| 1091 | ///\r | |
| 1092 | UINT32 PEBS_EN_PMC3:1;\r | |
| 1093 | UINT32 Reserved1:28;\r | |
| 1094 | ///\r | |
| 1095 | /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r | |
| 1096 | ///\r | |
| 1097 | UINT32 LL_EN_PMC0:1;\r | |
| 1098 | ///\r | |
| 1099 | /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r | |
| 1100 | ///\r | |
| 1101 | UINT32 LL_EN_PMC1:1;\r | |
| 1102 | ///\r | |
| 1103 | /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r | |
| 1104 | ///\r | |
| 1105 | UINT32 LL_EN_PMC2:1;\r | |
| 1106 | ///\r | |
| 1107 | /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r | |
| 1108 | ///\r | |
| 1109 | UINT32 LL_EN_PMC3:1;\r | |
| 1110 | UINT32 Reserved2:28;\r | |
| 1111 | } Bits;\r | |
| 1112 | ///\r | |
| 1113 | /// All bit fields as a 64-bit value\r | |
| 1114 | ///\r | |
| 1115 | UINT64 Uint64;\r | |
| 1116 | } MSR_NEHALEM_PEBS_ENABLE_REGISTER;\r | |
| 1117 | \r | |
| 1118 | \r | |
| 1119 | /**\r | |
| ba1a2d11 | 1120 | Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring\r |
| bd946618 MK |
1121 | Facility.".\r |
| 1122 | \r | |
| 1123 | @param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)\r | |
| 1124 | @param EAX Lower 32-bits of MSR value.\r | |
| 1125 | Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.\r | |
| 1126 | @param EDX Upper 32-bits of MSR value.\r | |
| 1127 | Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.\r | |
| 1128 | \r | |
| 1129 | <b>Example usage</b>\r | |
| 1130 | @code\r | |
| 1131 | MSR_NEHALEM_PEBS_LD_LAT_REGISTER Msr;\r | |
| 1132 | \r | |
| 1133 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);\r | |
| 1134 | AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);\r | |
| 1135 | @endcode\r | |
| c2aa191b | 1136 | @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.\r |
| bd946618 MK |
1137 | **/\r |
| 1138 | #define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6\r | |
| 1139 | \r | |
| 1140 | /**\r | |
| 1141 | MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT\r | |
| 1142 | **/\r | |
| 1143 | typedef union {\r | |
| 1144 | ///\r | |
| 1145 | /// Individual bit fields\r | |
| 1146 | ///\r | |
| 1147 | struct {\r | |
| 1148 | ///\r | |
| 1149 | /// [Bits 15:0] Minimum threshold latency value of tagged load operation\r | |
| 1150 | /// that will be counted. (R/W).\r | |
| 1151 | ///\r | |
| 1152 | UINT32 MinimumThreshold:16;\r | |
| 1153 | UINT32 Reserved1:16;\r | |
| 1154 | UINT32 Reserved2:32;\r | |
| 1155 | } Bits;\r | |
| 1156 | ///\r | |
| 1157 | /// All bit fields as a 32-bit value\r | |
| 1158 | ///\r | |
| 1159 | UINT32 Uint32;\r | |
| 1160 | ///\r | |
| 1161 | /// All bit fields as a 64-bit value\r | |
| 1162 | ///\r | |
| 1163 | UINT64 Uint64;\r | |
| 1164 | } MSR_NEHALEM_PEBS_LD_LAT_REGISTER;\r | |
| 1165 | \r | |
| 1166 | \r | |
| 1167 | /**\r | |
| 1168 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 1169 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r | |
| 1170 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
| 1171 | processor-specific C3 states. Count at the same frequency as the TSC.\r | |
| 1172 | \r | |
| 1173 | @param ECX MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)\r | |
| 1174 | @param EAX Lower 32-bits of MSR value.\r | |
| 1175 | @param EDX Upper 32-bits of MSR value.\r | |
| 1176 | \r | |
| 1177 | <b>Example usage</b>\r | |
| 1178 | @code\r | |
| 1179 | UINT64 Msr;\r | |
| 1180 | \r | |
| 1181 | Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);\r | |
| 1182 | AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);\r | |
| 1183 | @endcode\r | |
| c2aa191b | 1184 | @note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r |
| bd946618 MK |
1185 | **/\r |
| 1186 | #define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8\r | |
| 1187 | \r | |
| 1188 | \r | |
| 1189 | /**\r | |
| 1190 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 1191 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r | |
| 1192 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
| 1193 | processor-specific C6 states. Count at the same frequency as the TSC.\r | |
| 1194 | \r | |
| 1195 | @param ECX MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)\r | |
| 1196 | @param EAX Lower 32-bits of MSR value.\r | |
| 1197 | @param EDX Upper 32-bits of MSR value.\r | |
| 1198 | \r | |
| 1199 | <b>Example usage</b>\r | |
| 1200 | @code\r | |
| 1201 | UINT64 Msr;\r | |
| 1202 | \r | |
| 1203 | Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);\r | |
| 1204 | AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);\r | |
| 1205 | @endcode\r | |
| c2aa191b | 1206 | @note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r |
| bd946618 MK |
1207 | **/\r |
| 1208 | #define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9\r | |
| 1209 | \r | |
| 1210 | \r | |
| 1211 | /**\r | |
| 1212 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 1213 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7\r | |
| 1214 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
| 1215 | processor-specific C7 states. Count at the same frequency as the TSC.\r | |
| 1216 | \r | |
| 1217 | @param ECX MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)\r | |
| 1218 | @param EAX Lower 32-bits of MSR value.\r | |
| 1219 | @param EDX Upper 32-bits of MSR value.\r | |
| 1220 | \r | |
| 1221 | <b>Example usage</b>\r | |
| 1222 | @code\r | |
| 1223 | UINT64 Msr;\r | |
| 1224 | \r | |
| 1225 | Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);\r | |
| 1226 | AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);\r | |
| 1227 | @endcode\r | |
| c2aa191b | 1228 | @note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r |
| bd946618 MK |
1229 | **/\r |
| 1230 | #define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA\r | |
| 1231 | \r | |
| 1232 | \r | |
| 1233 | /**\r | |
| 1234 | Core. Note: C-state values are processor specific C-state code names,\r | |
| 1235 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r | |
| 1236 | Residency Counter. (R/O) Value since last reset that this core is in\r | |
| 1237 | processor-specific C3 states. Count at the same frequency as the TSC.\r | |
| 1238 | \r | |
| 1239 | @param ECX MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)\r | |
| 1240 | @param EAX Lower 32-bits of MSR value.\r | |
| 1241 | @param EDX Upper 32-bits of MSR value.\r | |
| 1242 | \r | |
| 1243 | <b>Example usage</b>\r | |
| 1244 | @code\r | |
| 1245 | UINT64 Msr;\r | |
| 1246 | \r | |
| 1247 | Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);\r | |
| 1248 | AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);\r | |
| 1249 | @endcode\r | |
| c2aa191b | 1250 | @note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r |
| bd946618 MK |
1251 | **/\r |
| 1252 | #define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC\r | |
| 1253 | \r | |
| 1254 | \r | |
| 1255 | /**\r | |
| 1256 | Core. Note: C-state values are processor specific C-state code names,\r | |
| 1257 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r | |
| 1258 | Residency Counter. (R/O) Value since last reset that this core is in\r | |
| 1259 | processor-specific C6 states. Count at the same frequency as the TSC.\r | |
| 1260 | \r | |
| 1261 | @param ECX MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)\r | |
| 1262 | @param EAX Lower 32-bits of MSR value.\r | |
| 1263 | @param EDX Upper 32-bits of MSR value.\r | |
| 1264 | \r | |
| 1265 | <b>Example usage</b>\r | |
| 1266 | @code\r | |
| 1267 | UINT64 Msr;\r | |
| 1268 | \r | |
| 1269 | Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);\r | |
| 1270 | AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);\r | |
| 1271 | @endcode\r | |
| c2aa191b | 1272 | @note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r |
| bd946618 MK |
1273 | **/\r |
| 1274 | #define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD\r | |
| 1275 | \r | |
| 1276 | \r | |
| bd946618 MK |
1277 | /**\r |
| 1278 | Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r | |
| 0f16be6d HW |
1279 | branch record registers on the last branch record stack. The From_IP part of\r |
| 1280 | the stack contains pointers to the source instruction. See also: - Last\r | |
| 1281 | Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in\r | |
| 1282 | Section 17.4.8.1.\r | |
| bd946618 MK |
1283 | \r |
| 1284 | @param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP\r | |
| 1285 | @param EAX Lower 32-bits of MSR value.\r | |
| 1286 | @param EDX Upper 32-bits of MSR value.\r | |
| 1287 | \r | |
| 1288 | <b>Example usage</b>\r | |
| 1289 | @code\r | |
| 1290 | UINT64 Msr;\r | |
| 1291 | \r | |
| 1292 | Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);\r | |
| 1293 | AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);\r | |
| 1294 | @endcode\r | |
| c2aa191b JF |
1295 | @note MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r |
| 1296 | MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r | |
| 1297 | MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r | |
| 1298 | MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r | |
| 1299 | MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r | |
| 1300 | MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r | |
| 1301 | MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r | |
| 1302 | MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r | |
| 1303 | MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r | |
| 1304 | MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r | |
| 1305 | MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r | |
| 1306 | MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r | |
| 1307 | MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r | |
| 1308 | MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r | |
| 1309 | MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r | |
| 1310 | MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r | |
| bd946618 MK |
1311 | @{\r |
| 1312 | **/\r | |
| 1313 | #define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680\r | |
| 1314 | #define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681\r | |
| 1315 | #define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682\r | |
| 1316 | #define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683\r | |
| 1317 | #define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684\r | |
| 1318 | #define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685\r | |
| 1319 | #define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686\r | |
| 1320 | #define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687\r | |
| 1321 | #define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688\r | |
| 1322 | #define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689\r | |
| 1323 | #define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A\r | |
| 1324 | #define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B\r | |
| 1325 | #define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C\r | |
| 1326 | #define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D\r | |
| 1327 | #define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E\r | |
| 1328 | #define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F\r | |
| 1329 | /// @}\r | |
| 1330 | \r | |
| 1331 | \r | |
| 1332 | /**\r | |
| 1333 | Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r | |
| 1334 | record registers on the last branch record stack. This part of the stack\r | |
| 0f16be6d | 1335 | contains pointers to the destination instruction.\r |
| bd946618 MK |
1336 | \r |
| 1337 | @param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP\r | |
| 1338 | @param EAX Lower 32-bits of MSR value.\r | |
| 1339 | @param EDX Upper 32-bits of MSR value.\r | |
| 1340 | \r | |
| 1341 | <b>Example usage</b>\r | |
| 1342 | @code\r | |
| 1343 | UINT64 Msr;\r | |
| 1344 | \r | |
| 1345 | Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);\r | |
| 1346 | AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);\r | |
| 1347 | @endcode\r | |
| c2aa191b JF |
1348 | @note MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r |
| 1349 | MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r | |
| 1350 | MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r | |
| 1351 | MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r | |
| 1352 | MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r | |
| 1353 | MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r | |
| 1354 | MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r | |
| 1355 | MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r | |
| 1356 | MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r | |
| 1357 | MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r | |
| 1358 | MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r | |
| 1359 | MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r | |
| 1360 | MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r | |
| 1361 | MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r | |
| 1362 | MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r | |
| 1363 | MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r | |
| bd946618 MK |
1364 | @{\r |
| 1365 | **/\r | |
| 1366 | #define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0\r | |
| 1367 | #define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1\r | |
| 1368 | #define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2\r | |
| 1369 | #define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3\r | |
| 1370 | #define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4\r | |
| 1371 | #define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5\r | |
| 1372 | #define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6\r | |
| 1373 | #define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7\r | |
| 1374 | #define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8\r | |
| 1375 | #define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9\r | |
| 1376 | #define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA\r | |
| 1377 | #define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB\r | |
| 1378 | #define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC\r | |
| 1379 | #define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD\r | |
| 1380 | #define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE\r | |
| 1381 | #define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF\r | |
| 1382 | /// @}\r | |
| 1383 | \r | |
| 1384 | \r | |
| 1385 | /**\r | |
| 1386 | Package.\r | |
| 1387 | \r | |
| 1388 | @param ECX MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)\r | |
| 1389 | @param EAX Lower 32-bits of MSR value.\r | |
| 1390 | Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.\r | |
| 1391 | @param EDX Upper 32-bits of MSR value.\r | |
| 1392 | Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.\r | |
| 1393 | \r | |
| 1394 | <b>Example usage</b>\r | |
| 1395 | @code\r | |
| 1396 | MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Msr;\r | |
| 1397 | \r | |
| 1398 | Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);\r | |
| 1399 | AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);\r | |
| 1400 | @endcode\r | |
| c2aa191b | 1401 | @note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM.\r |
| bd946618 MK |
1402 | **/\r |
| 1403 | #define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301\r | |
| 1404 | \r | |
| 1405 | /**\r | |
| 1406 | MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF\r | |
| 1407 | **/\r | |
| 1408 | typedef union {\r | |
| 1409 | ///\r | |
| 1410 | /// Individual bit fields\r | |
| 1411 | ///\r | |
| 1412 | struct {\r | |
| 1413 | ///\r | |
| 1414 | /// [Bit 0] From M to S (R/W).\r | |
| 1415 | ///\r | |
| 1416 | UINT32 FromMtoS:1;\r | |
| 1417 | ///\r | |
| 1418 | /// [Bit 1] From E to S (R/W).\r | |
| 1419 | ///\r | |
| 1420 | UINT32 FromEtoS:1;\r | |
| 1421 | ///\r | |
| 1422 | /// [Bit 2] From S to S (R/W).\r | |
| 1423 | ///\r | |
| 1424 | UINT32 FromStoS:1;\r | |
| 1425 | ///\r | |
| 1426 | /// [Bit 3] From F to S (R/W).\r | |
| 1427 | ///\r | |
| 1428 | UINT32 FromFtoS:1;\r | |
| 1429 | ///\r | |
| 1430 | /// [Bit 4] From M to I (R/W).\r | |
| 1431 | ///\r | |
| 1432 | UINT32 FromMtoI:1;\r | |
| 1433 | ///\r | |
| 1434 | /// [Bit 5] From E to I (R/W).\r | |
| 1435 | ///\r | |
| 1436 | UINT32 FromEtoI:1;\r | |
| 1437 | ///\r | |
| 1438 | /// [Bit 6] From S to I (R/W).\r | |
| 1439 | ///\r | |
| 1440 | UINT32 FromStoI:1;\r | |
| 1441 | ///\r | |
| 1442 | /// [Bit 7] From F to I (R/W).\r | |
| 1443 | ///\r | |
| 1444 | UINT32 FromFtoI:1;\r | |
| 1445 | UINT32 Reserved1:24;\r | |
| 1446 | UINT32 Reserved2:32;\r | |
| 1447 | } Bits;\r | |
| 1448 | ///\r | |
| 1449 | /// All bit fields as a 32-bit value\r | |
| 1450 | ///\r | |
| 1451 | UINT32 Uint32;\r | |
| 1452 | ///\r | |
| 1453 | /// All bit fields as a 64-bit value\r | |
| 1454 | ///\r | |
| 1455 | UINT64 Uint64;\r | |
| 1456 | } MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER;\r | |
| 1457 | \r | |
| 1458 | \r | |
| 1459 | /**\r | |
| ba1a2d11 | 1460 | Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r |
| bd946618 MK |
1461 | Facility.".\r |
| 1462 | \r | |
| 1463 | @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)\r | |
| 1464 | @param EAX Lower 32-bits of MSR value.\r | |
| 1465 | @param EDX Upper 32-bits of MSR value.\r | |
| 1466 | \r | |
| 1467 | <b>Example usage</b>\r | |
| 1468 | @code\r | |
| 1469 | UINT64 Msr;\r | |
| 1470 | \r | |
| 1471 | Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);\r | |
| 1472 | AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);\r | |
| 1473 | @endcode\r | |
| c2aa191b | 1474 | @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM.\r |
| bd946618 MK |
1475 | **/\r |
| 1476 | #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391\r | |
| 1477 | \r | |
| 1478 | \r | |
| 1479 | /**\r | |
| ba1a2d11 | 1480 | Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r |
| bd946618 MK |
1481 | Facility.".\r |
| 1482 | \r | |
| 1483 | @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)\r | |
| 1484 | @param EAX Lower 32-bits of MSR value.\r | |
| 1485 | @param EDX Upper 32-bits of MSR value.\r | |
| 1486 | \r | |
| 1487 | <b>Example usage</b>\r | |
| 1488 | @code\r | |
| 1489 | UINT64 Msr;\r | |
| 1490 | \r | |
| 1491 | Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);\r | |
| 1492 | AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);\r | |
| 1493 | @endcode\r | |
| c2aa191b | 1494 | @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM.\r |
| bd946618 MK |
1495 | **/\r |
| 1496 | #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392\r | |
| 1497 | \r | |
| 1498 | \r | |
| 1499 | /**\r | |
| ba1a2d11 | 1500 | Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r |
| bd946618 MK |
1501 | Facility.".\r |
| 1502 | \r | |
| 1503 | @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)\r | |
| 1504 | @param EAX Lower 32-bits of MSR value.\r | |
| 1505 | @param EDX Upper 32-bits of MSR value.\r | |
| 1506 | \r | |
| 1507 | <b>Example usage</b>\r | |
| 1508 | @code\r | |
| 1509 | UINT64 Msr;\r | |
| 1510 | \r | |
| 1511 | Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);\r | |
| 1512 | AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);\r | |
| 1513 | @endcode\r | |
| c2aa191b | 1514 | @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM.\r |
| bd946618 MK |
1515 | **/\r |
| 1516 | #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393\r | |
| 1517 | \r | |
| 1518 | \r | |
| 1519 | /**\r | |
| ba1a2d11 | 1520 | Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r |
| bd946618 MK |
1521 | Facility.".\r |
| 1522 | \r | |
| 1523 | @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)\r | |
| 1524 | @param EAX Lower 32-bits of MSR value.\r | |
| 1525 | @param EDX Upper 32-bits of MSR value.\r | |
| 1526 | \r | |
| 1527 | <b>Example usage</b>\r | |
| 1528 | @code\r | |
| 1529 | UINT64 Msr;\r | |
| 1530 | \r | |
| 1531 | Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);\r | |
| 1532 | AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);\r | |
| 1533 | @endcode\r | |
| c2aa191b | 1534 | @note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM.\r |
| bd946618 MK |
1535 | **/\r |
| 1536 | #define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394\r | |
| 1537 | \r | |
| 1538 | \r | |
| 1539 | /**\r | |
| ba1a2d11 | 1540 | Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r |
| bd946618 MK |
1541 | Facility.".\r |
| 1542 | \r | |
| 1543 | @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)\r | |
| 1544 | @param EAX Lower 32-bits of MSR value.\r | |
| 1545 | @param EDX Upper 32-bits of MSR value.\r | |
| 1546 | \r | |
| 1547 | <b>Example usage</b>\r | |
| 1548 | @code\r | |
| 1549 | UINT64 Msr;\r | |
| 1550 | \r | |
| 1551 | Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);\r | |
| 1552 | AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);\r | |
| 1553 | @endcode\r | |
| c2aa191b | 1554 | @note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM.\r |
| bd946618 MK |
1555 | **/\r |
| 1556 | #define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395\r | |
| 1557 | \r | |
| 1558 | \r | |
| 1559 | /**\r | |
| ba1a2d11 | 1560 | Package. See Section 18.3.1.2.3, "Uncore Address/Opcode Match MSR.".\r |
| bd946618 MK |
1561 | \r |
| 1562 | @param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)\r | |
| 1563 | @param EAX Lower 32-bits of MSR value.\r | |
| 1564 | @param EDX Upper 32-bits of MSR value.\r | |
| 1565 | \r | |
| 1566 | <b>Example usage</b>\r | |
| 1567 | @code\r | |
| 1568 | UINT64 Msr;\r | |
| 1569 | \r | |
| 1570 | Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);\r | |
| 1571 | AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);\r | |
| 1572 | @endcode\r | |
| c2aa191b | 1573 | @note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM.\r |
| bd946618 MK |
1574 | **/\r |
| 1575 | #define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396\r | |
| 1576 | \r | |
| 1577 | \r | |
| 1578 | /**\r | |
| ba1a2d11 | 1579 | Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration\r |
| bd946618 MK |
1580 | Facility.".\r |
| 1581 | \r | |
| 1582 | @param ECX MSR_NEHALEM_UNCORE_PMCi\r | |
| 1583 | @param EAX Lower 32-bits of MSR value.\r | |
| 1584 | @param EDX Upper 32-bits of MSR value.\r | |
| 1585 | \r | |
| 1586 | <b>Example usage</b>\r | |
| 1587 | @code\r | |
| 1588 | UINT64 Msr;\r | |
| 1589 | \r | |
| 1590 | Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);\r | |
| 1591 | AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);\r | |
| 1592 | @endcode\r | |
| c2aa191b JF |
1593 | @note MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM.\r |
| 1594 | MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM.\r | |
| 1595 | MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM.\r | |
| 1596 | MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM.\r | |
| 1597 | MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM.\r | |
| 1598 | MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM.\r | |
| 1599 | MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM.\r | |
| 1600 | MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.\r | |
| bd946618 MK |
1601 | @{\r |
| 1602 | **/\r | |
| 1603 | #define MSR_NEHALEM_UNCORE_PMC0 0x000003B0\r | |
| 1604 | #define MSR_NEHALEM_UNCORE_PMC1 0x000003B1\r | |
| 1605 | #define MSR_NEHALEM_UNCORE_PMC2 0x000003B2\r | |
| 1606 | #define MSR_NEHALEM_UNCORE_PMC3 0x000003B3\r | |
| 1607 | #define MSR_NEHALEM_UNCORE_PMC4 0x000003B4\r | |
| 1608 | #define MSR_NEHALEM_UNCORE_PMC5 0x000003B5\r | |
| 1609 | #define MSR_NEHALEM_UNCORE_PMC6 0x000003B6\r | |
| 1610 | #define MSR_NEHALEM_UNCORE_PMC7 0x000003B7\r | |
| 1611 | /// @}\r | |
| 1612 | \r | |
| 1613 | /**\r | |
| ba1a2d11 | 1614 | Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration\r |
| bd946618 MK |
1615 | Facility.".\r |
| 1616 | \r | |
| 1617 | @param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi\r | |
| 1618 | @param EAX Lower 32-bits of MSR value.\r | |
| 1619 | @param EDX Upper 32-bits of MSR value.\r | |
| 1620 | \r | |
| 1621 | <b>Example usage</b>\r | |
| 1622 | @code\r | |
| 1623 | UINT64 Msr;\r | |
| 1624 | \r | |
| 1625 | Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);\r | |
| 1626 | AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);\r | |
| 1627 | @endcode\r | |
| c2aa191b JF |
1628 | @note MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM.\r |
| 1629 | MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM.\r | |
| 1630 | MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM.\r | |
| 1631 | MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM.\r | |
| 1632 | MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM.\r | |
| 1633 | MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM.\r | |
| 1634 | MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM.\r | |
| 1635 | MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.\r | |
| bd946618 MK |
1636 | @{\r |
| 1637 | **/\r | |
| 1638 | #define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0\r | |
| 1639 | #define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1\r | |
| 1640 | #define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2\r | |
| 1641 | #define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3\r | |
| 1642 | #define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4\r | |
| 1643 | #define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5\r | |
| 1644 | #define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6\r | |
| 1645 | #define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7\r | |
| 1646 | /// @}\r | |
| 1647 | \r | |
| 1648 | \r | |
| 1649 | /**\r | |
| 1650 | Package. Uncore W-box perfmon fixed counter.\r | |
| 1651 | \r | |
| 1652 | @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)\r | |
| 1653 | @param EAX Lower 32-bits of MSR value.\r | |
| 1654 | @param EDX Upper 32-bits of MSR value.\r | |
| 1655 | \r | |
| 1656 | <b>Example usage</b>\r | |
| 1657 | @code\r | |
| 1658 | UINT64 Msr;\r | |
| 1659 | \r | |
| 1660 | Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);\r | |
| 1661 | AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);\r | |
| 1662 | @endcode\r | |
| c2aa191b | 1663 | @note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM.\r |
| bd946618 MK |
1664 | **/\r |
| 1665 | #define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394\r | |
| 1666 | \r | |
| 1667 | \r | |
| 1668 | /**\r | |
| 1669 | Package. Uncore U-box perfmon fixed counter control MSR.\r | |
| 1670 | \r | |
| 1671 | @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)\r | |
| 1672 | @param EAX Lower 32-bits of MSR value.\r | |
| 1673 | @param EDX Upper 32-bits of MSR value.\r | |
| 1674 | \r | |
| 1675 | <b>Example usage</b>\r | |
| 1676 | @code\r | |
| 1677 | UINT64 Msr;\r | |
| 1678 | \r | |
| 1679 | Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);\r | |
| 1680 | AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);\r | |
| 1681 | @endcode\r | |
| c2aa191b | 1682 | @note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM.\r |
| bd946618 MK |
1683 | **/\r |
| 1684 | #define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395\r | |
| 1685 | \r | |
| 1686 | \r | |
| 1687 | /**\r | |
| 1688 | Package. Uncore U-box perfmon global control MSR.\r | |
| 1689 | \r | |
| 1690 | @param ECX MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)\r | |
| 1691 | @param EAX Lower 32-bits of MSR value.\r | |
| 1692 | @param EDX Upper 32-bits of MSR value.\r | |
| 1693 | \r | |
| 1694 | <b>Example usage</b>\r | |
| 1695 | @code\r | |
| 1696 | UINT64 Msr;\r | |
| 1697 | \r | |
| 1698 | Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);\r | |
| 1699 | AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);\r | |
| 1700 | @endcode\r | |
| c2aa191b | 1701 | @note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM.\r |
| bd946618 MK |
1702 | **/\r |
| 1703 | #define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00\r | |
| 1704 | \r | |
| 1705 | \r | |
| 1706 | /**\r | |
| 1707 | Package. Uncore U-box perfmon global status MSR.\r | |
| 1708 | \r | |
| 1709 | @param ECX MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)\r | |
| 1710 | @param EAX Lower 32-bits of MSR value.\r | |
| 1711 | @param EDX Upper 32-bits of MSR value.\r | |
| 1712 | \r | |
| 1713 | <b>Example usage</b>\r | |
| 1714 | @code\r | |
| 1715 | UINT64 Msr;\r | |
| 1716 | \r | |
| 1717 | Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);\r | |
| 1718 | AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);\r | |
| 1719 | @endcode\r | |
| c2aa191b | 1720 | @note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM.\r |
| bd946618 MK |
1721 | **/\r |
| 1722 | #define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01\r | |
| 1723 | \r | |
| 1724 | \r | |
| 1725 | /**\r | |
| 1726 | Package. Uncore U-box perfmon global overflow control MSR.\r | |
| 1727 | \r | |
| 1728 | @param ECX MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)\r | |
| 1729 | @param EAX Lower 32-bits of MSR value.\r | |
| 1730 | @param EDX Upper 32-bits of MSR value.\r | |
| 1731 | \r | |
| 1732 | <b>Example usage</b>\r | |
| 1733 | @code\r | |
| 1734 | UINT64 Msr;\r | |
| 1735 | \r | |
| 1736 | Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);\r | |
| 1737 | AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);\r | |
| 1738 | @endcode\r | |
| c2aa191b | 1739 | @note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM.\r |
| bd946618 MK |
1740 | **/\r |
| 1741 | #define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02\r | |
| 1742 | \r | |
| 1743 | \r | |
| 1744 | /**\r | |
| 1745 | Package. Uncore U-box perfmon event select MSR.\r | |
| 1746 | \r | |
| 1747 | @param ECX MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)\r | |
| 1748 | @param EAX Lower 32-bits of MSR value.\r | |
| 1749 | @param EDX Upper 32-bits of MSR value.\r | |
| 1750 | \r | |
| 1751 | <b>Example usage</b>\r | |
| 1752 | @code\r | |
| 1753 | UINT64 Msr;\r | |
| 1754 | \r | |
| 1755 | Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);\r | |
| 1756 | AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);\r | |
| 1757 | @endcode\r | |
| c2aa191b | 1758 | @note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM.\r |
| bd946618 MK |
1759 | **/\r |
| 1760 | #define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10\r | |
| 1761 | \r | |
| 1762 | \r | |
| 1763 | /**\r | |
| 1764 | Package. Uncore U-box perfmon counter MSR.\r | |
| 1765 | \r | |
| 1766 | @param ECX MSR_NEHALEM_U_PMON_CTR (0x00000C11)\r | |
| 1767 | @param EAX Lower 32-bits of MSR value.\r | |
| 1768 | @param EDX Upper 32-bits of MSR value.\r | |
| 1769 | \r | |
| 1770 | <b>Example usage</b>\r | |
| 1771 | @code\r | |
| 1772 | UINT64 Msr;\r | |
| 1773 | \r | |
| 1774 | Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);\r | |
| 1775 | AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);\r | |
| 1776 | @endcode\r | |
| c2aa191b | 1777 | @note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM.\r |
| bd946618 MK |
1778 | **/\r |
| 1779 | #define MSR_NEHALEM_U_PMON_CTR 0x00000C11\r | |
| 1780 | \r | |
| 1781 | \r | |
| 1782 | /**\r | |
| 1783 | Package. Uncore B-box 0 perfmon local box control MSR.\r | |
| 1784 | \r | |
| 1785 | @param ECX MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)\r | |
| 1786 | @param EAX Lower 32-bits of MSR value.\r | |
| 1787 | @param EDX Upper 32-bits of MSR value.\r | |
| 1788 | \r | |
| 1789 | <b>Example usage</b>\r | |
| 1790 | @code\r | |
| 1791 | UINT64 Msr;\r | |
| 1792 | \r | |
| 1793 | Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);\r | |
| 1794 | AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);\r | |
| 1795 | @endcode\r | |
| c2aa191b | 1796 | @note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
1797 | **/\r |
| 1798 | #define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20\r | |
| 1799 | \r | |
| 1800 | \r | |
| 1801 | /**\r | |
| 1802 | Package. Uncore B-box 0 perfmon local box status MSR.\r | |
| 1803 | \r | |
| 1804 | @param ECX MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)\r | |
| 1805 | @param EAX Lower 32-bits of MSR value.\r | |
| 1806 | @param EDX Upper 32-bits of MSR value.\r | |
| 1807 | \r | |
| 1808 | <b>Example usage</b>\r | |
| 1809 | @code\r | |
| 1810 | UINT64 Msr;\r | |
| 1811 | \r | |
| 1812 | Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);\r | |
| 1813 | AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);\r | |
| 1814 | @endcode\r | |
| c2aa191b | 1815 | @note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
1816 | **/\r |
| 1817 | #define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21\r | |
| 1818 | \r | |
| 1819 | \r | |
| 1820 | /**\r | |
| 1821 | Package. Uncore B-box 0 perfmon local box overflow control MSR.\r | |
| 1822 | \r | |
| 1823 | @param ECX MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)\r | |
| 1824 | @param EAX Lower 32-bits of MSR value.\r | |
| 1825 | @param EDX Upper 32-bits of MSR value.\r | |
| 1826 | \r | |
| 1827 | <b>Example usage</b>\r | |
| 1828 | @code\r | |
| 1829 | UINT64 Msr;\r | |
| 1830 | \r | |
| 1831 | Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);\r | |
| 1832 | AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);\r | |
| 1833 | @endcode\r | |
| c2aa191b | 1834 | @note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
1835 | **/\r |
| 1836 | #define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22\r | |
| 1837 | \r | |
| 1838 | \r | |
| 1839 | /**\r | |
| 1840 | Package. Uncore B-box 0 perfmon event select MSR.\r | |
| 1841 | \r | |
| 1842 | @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)\r | |
| 1843 | @param EAX Lower 32-bits of MSR value.\r | |
| 1844 | @param EDX Upper 32-bits of MSR value.\r | |
| 1845 | \r | |
| 1846 | <b>Example usage</b>\r | |
| 1847 | @code\r | |
| 1848 | UINT64 Msr;\r | |
| 1849 | \r | |
| 1850 | Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);\r | |
| 1851 | AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);\r | |
| 1852 | @endcode\r | |
| c2aa191b | 1853 | @note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
1854 | **/\r |
| 1855 | #define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30\r | |
| 1856 | \r | |
| 1857 | \r | |
| 1858 | /**\r | |
| 1859 | Package. Uncore B-box 0 perfmon counter MSR.\r | |
| 1860 | \r | |
| 1861 | @param ECX MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)\r | |
| 1862 | @param EAX Lower 32-bits of MSR value.\r | |
| 1863 | @param EDX Upper 32-bits of MSR value.\r | |
| 1864 | \r | |
| 1865 | <b>Example usage</b>\r | |
| 1866 | @code\r | |
| 1867 | UINT64 Msr;\r | |
| 1868 | \r | |
| 1869 | Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);\r | |
| 1870 | AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);\r | |
| 1871 | @endcode\r | |
| c2aa191b | 1872 | @note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM.\r |
| bd946618 MK |
1873 | **/\r |
| 1874 | #define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31\r | |
| 1875 | \r | |
| 1876 | \r | |
| 1877 | /**\r | |
| 1878 | Package. Uncore B-box 0 perfmon event select MSR.\r | |
| 1879 | \r | |
| 1880 | @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)\r | |
| 1881 | @param EAX Lower 32-bits of MSR value.\r | |
| 1882 | @param EDX Upper 32-bits of MSR value.\r | |
| 1883 | \r | |
| 1884 | <b>Example usage</b>\r | |
| 1885 | @code\r | |
| 1886 | UINT64 Msr;\r | |
| 1887 | \r | |
| 1888 | Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);\r | |
| 1889 | AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);\r | |
| 1890 | @endcode\r | |
| c2aa191b | 1891 | @note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
1892 | **/\r |
| 1893 | #define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32\r | |
| 1894 | \r | |
| 1895 | \r | |
| 1896 | /**\r | |
| 1897 | Package. Uncore B-box 0 perfmon counter MSR.\r | |
| 1898 | \r | |
| 1899 | @param ECX MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)\r | |
| 1900 | @param EAX Lower 32-bits of MSR value.\r | |
| 1901 | @param EDX Upper 32-bits of MSR value.\r | |
| 1902 | \r | |
| 1903 | <b>Example usage</b>\r | |
| 1904 | @code\r | |
| 1905 | UINT64 Msr;\r | |
| 1906 | \r | |
| 1907 | Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);\r | |
| 1908 | AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);\r | |
| 1909 | @endcode\r | |
| c2aa191b | 1910 | @note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM.\r |
| bd946618 MK |
1911 | **/\r |
| 1912 | #define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33\r | |
| 1913 | \r | |
| 1914 | \r | |
| 1915 | /**\r | |
| 1916 | Package. Uncore B-box 0 perfmon event select MSR.\r | |
| 1917 | \r | |
| 1918 | @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)\r | |
| 1919 | @param EAX Lower 32-bits of MSR value.\r | |
| 1920 | @param EDX Upper 32-bits of MSR value.\r | |
| 1921 | \r | |
| 1922 | <b>Example usage</b>\r | |
| 1923 | @code\r | |
| 1924 | UINT64 Msr;\r | |
| 1925 | \r | |
| 1926 | Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);\r | |
| 1927 | AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);\r | |
| 1928 | @endcode\r | |
| c2aa191b | 1929 | @note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
1930 | **/\r |
| 1931 | #define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34\r | |
| 1932 | \r | |
| 1933 | \r | |
| 1934 | /**\r | |
| 1935 | Package. Uncore B-box 0 perfmon counter MSR.\r | |
| 1936 | \r | |
| 1937 | @param ECX MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)\r | |
| 1938 | @param EAX Lower 32-bits of MSR value.\r | |
| 1939 | @param EDX Upper 32-bits of MSR value.\r | |
| 1940 | \r | |
| 1941 | <b>Example usage</b>\r | |
| 1942 | @code\r | |
| 1943 | UINT64 Msr;\r | |
| 1944 | \r | |
| 1945 | Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);\r | |
| 1946 | AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);\r | |
| 1947 | @endcode\r | |
| c2aa191b | 1948 | @note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM.\r |
| bd946618 MK |
1949 | **/\r |
| 1950 | #define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35\r | |
| 1951 | \r | |
| 1952 | \r | |
| 1953 | /**\r | |
| 1954 | Package. Uncore B-box 0 perfmon event select MSR.\r | |
| 1955 | \r | |
| 1956 | @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)\r | |
| 1957 | @param EAX Lower 32-bits of MSR value.\r | |
| 1958 | @param EDX Upper 32-bits of MSR value.\r | |
| 1959 | \r | |
| 1960 | <b>Example usage</b>\r | |
| 1961 | @code\r | |
| 1962 | UINT64 Msr;\r | |
| 1963 | \r | |
| 1964 | Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);\r | |
| 1965 | AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);\r | |
| 1966 | @endcode\r | |
| c2aa191b | 1967 | @note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
1968 | **/\r |
| 1969 | #define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36\r | |
| 1970 | \r | |
| 1971 | \r | |
| 1972 | /**\r | |
| 1973 | Package. Uncore B-box 0 perfmon counter MSR.\r | |
| 1974 | \r | |
| 1975 | @param ECX MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)\r | |
| 1976 | @param EAX Lower 32-bits of MSR value.\r | |
| 1977 | @param EDX Upper 32-bits of MSR value.\r | |
| 1978 | \r | |
| 1979 | <b>Example usage</b>\r | |
| 1980 | @code\r | |
| 1981 | UINT64 Msr;\r | |
| 1982 | \r | |
| 1983 | Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);\r | |
| 1984 | AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);\r | |
| 1985 | @endcode\r | |
| c2aa191b | 1986 | @note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM.\r |
| bd946618 MK |
1987 | **/\r |
| 1988 | #define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37\r | |
| 1989 | \r | |
| 1990 | \r | |
| 1991 | /**\r | |
| 1992 | Package. Uncore S-box 0 perfmon local box control MSR.\r | |
| 1993 | \r | |
| 1994 | @param ECX MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)\r | |
| 1995 | @param EAX Lower 32-bits of MSR value.\r | |
| 1996 | @param EDX Upper 32-bits of MSR value.\r | |
| 1997 | \r | |
| 1998 | <b>Example usage</b>\r | |
| 1999 | @code\r | |
| 2000 | UINT64 Msr;\r | |
| 2001 | \r | |
| 2002 | Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);\r | |
| 2003 | AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);\r | |
| 2004 | @endcode\r | |
| c2aa191b | 2005 | @note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
2006 | **/\r |
| 2007 | #define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40\r | |
| 2008 | \r | |
| 2009 | \r | |
| 2010 | /**\r | |
| 2011 | Package. Uncore S-box 0 perfmon local box status MSR.\r | |
| 2012 | \r | |
| 2013 | @param ECX MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)\r | |
| 2014 | @param EAX Lower 32-bits of MSR value.\r | |
| 2015 | @param EDX Upper 32-bits of MSR value.\r | |
| 2016 | \r | |
| 2017 | <b>Example usage</b>\r | |
| 2018 | @code\r | |
| 2019 | UINT64 Msr;\r | |
| 2020 | \r | |
| 2021 | Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);\r | |
| 2022 | AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);\r | |
| 2023 | @endcode\r | |
| c2aa191b | 2024 | @note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
2025 | **/\r |
| 2026 | #define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41\r | |
| 2027 | \r | |
| 2028 | \r | |
| 2029 | /**\r | |
| 2030 | Package. Uncore S-box 0 perfmon local box overflow control MSR.\r | |
| 2031 | \r | |
| 2032 | @param ECX MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)\r | |
| 2033 | @param EAX Lower 32-bits of MSR value.\r | |
| 2034 | @param EDX Upper 32-bits of MSR value.\r | |
| 2035 | \r | |
| 2036 | <b>Example usage</b>\r | |
| 2037 | @code\r | |
| 2038 | UINT64 Msr;\r | |
| 2039 | \r | |
| 2040 | Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);\r | |
| 2041 | AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);\r | |
| 2042 | @endcode\r | |
| c2aa191b | 2043 | @note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
2044 | **/\r |
| 2045 | #define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42\r | |
| 2046 | \r | |
| 2047 | \r | |
| 2048 | /**\r | |
| 2049 | Package. Uncore S-box 0 perfmon event select MSR.\r | |
| 2050 | \r | |
| 2051 | @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)\r | |
| 2052 | @param EAX Lower 32-bits of MSR value.\r | |
| 2053 | @param EDX Upper 32-bits of MSR value.\r | |
| 2054 | \r | |
| 2055 | <b>Example usage</b>\r | |
| 2056 | @code\r | |
| 2057 | UINT64 Msr;\r | |
| 2058 | \r | |
| 2059 | Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);\r | |
| 2060 | AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);\r | |
| 2061 | @endcode\r | |
| c2aa191b | 2062 | @note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
2063 | **/\r |
| 2064 | #define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50\r | |
| 2065 | \r | |
| 2066 | \r | |
| 2067 | /**\r | |
| 2068 | Package. Uncore S-box 0 perfmon counter MSR.\r | |
| 2069 | \r | |
| 2070 | @param ECX MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)\r | |
| 2071 | @param EAX Lower 32-bits of MSR value.\r | |
| 2072 | @param EDX Upper 32-bits of MSR value.\r | |
| 2073 | \r | |
| 2074 | <b>Example usage</b>\r | |
| 2075 | @code\r | |
| 2076 | UINT64 Msr;\r | |
| 2077 | \r | |
| 2078 | Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);\r | |
| 2079 | AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);\r | |
| 2080 | @endcode\r | |
| c2aa191b | 2081 | @note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r |
| bd946618 MK |
2082 | **/\r |
| 2083 | #define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51\r | |
| 2084 | \r | |
| 2085 | \r | |
| 2086 | /**\r | |
| 2087 | Package. Uncore S-box 0 perfmon event select MSR.\r | |
| 2088 | \r | |
| 2089 | @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)\r | |
| 2090 | @param EAX Lower 32-bits of MSR value.\r | |
| 2091 | @param EDX Upper 32-bits of MSR value.\r | |
| 2092 | \r | |
| 2093 | <b>Example usage</b>\r | |
| 2094 | @code\r | |
| 2095 | UINT64 Msr;\r | |
| 2096 | \r | |
| 2097 | Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);\r | |
| 2098 | AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);\r | |
| 2099 | @endcode\r | |
| c2aa191b | 2100 | @note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
2101 | **/\r |
| 2102 | #define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52\r | |
| 2103 | \r | |
| 2104 | \r | |
| 2105 | /**\r | |
| 2106 | Package. Uncore S-box 0 perfmon counter MSR.\r | |
| 2107 | \r | |
| 2108 | @param ECX MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)\r | |
| 2109 | @param EAX Lower 32-bits of MSR value.\r | |
| 2110 | @param EDX Upper 32-bits of MSR value.\r | |
| 2111 | \r | |
| 2112 | <b>Example usage</b>\r | |
| 2113 | @code\r | |
| 2114 | UINT64 Msr;\r | |
| 2115 | \r | |
| 2116 | Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);\r | |
| 2117 | AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);\r | |
| 2118 | @endcode\r | |
| c2aa191b | 2119 | @note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r |
| bd946618 MK |
2120 | **/\r |
| 2121 | #define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53\r | |
| 2122 | \r | |
| 2123 | \r | |
| 2124 | /**\r | |
| 2125 | Package. Uncore S-box 0 perfmon event select MSR.\r | |
| 2126 | \r | |
| 2127 | @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)\r | |
| 2128 | @param EAX Lower 32-bits of MSR value.\r | |
| 2129 | @param EDX Upper 32-bits of MSR value.\r | |
| 2130 | \r | |
| 2131 | <b>Example usage</b>\r | |
| 2132 | @code\r | |
| 2133 | UINT64 Msr;\r | |
| 2134 | \r | |
| 2135 | Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);\r | |
| 2136 | AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);\r | |
| 2137 | @endcode\r | |
| c2aa191b | 2138 | @note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
2139 | **/\r |
| 2140 | #define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54\r | |
| 2141 | \r | |
| 2142 | \r | |
| 2143 | /**\r | |
| 2144 | Package. Uncore S-box 0 perfmon counter MSR.\r | |
| 2145 | \r | |
| 2146 | @param ECX MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)\r | |
| 2147 | @param EAX Lower 32-bits of MSR value.\r | |
| 2148 | @param EDX Upper 32-bits of MSR value.\r | |
| 2149 | \r | |
| 2150 | <b>Example usage</b>\r | |
| 2151 | @code\r | |
| 2152 | UINT64 Msr;\r | |
| 2153 | \r | |
| 2154 | Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);\r | |
| 2155 | AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);\r | |
| 2156 | @endcode\r | |
| c2aa191b | 2157 | @note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r |
| bd946618 MK |
2158 | **/\r |
| 2159 | #define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55\r | |
| 2160 | \r | |
| 2161 | \r | |
| 2162 | /**\r | |
| 2163 | Package. Uncore S-box 0 perfmon event select MSR.\r | |
| 2164 | \r | |
| 2165 | @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)\r | |
| 2166 | @param EAX Lower 32-bits of MSR value.\r | |
| 2167 | @param EDX Upper 32-bits of MSR value.\r | |
| 2168 | \r | |
| 2169 | <b>Example usage</b>\r | |
| 2170 | @code\r | |
| 2171 | UINT64 Msr;\r | |
| 2172 | \r | |
| 2173 | Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);\r | |
| 2174 | AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);\r | |
| 2175 | @endcode\r | |
| c2aa191b | 2176 | @note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
2177 | **/\r |
| 2178 | #define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56\r | |
| 2179 | \r | |
| 2180 | \r | |
| 2181 | /**\r | |
| 2182 | Package. Uncore S-box 0 perfmon counter MSR.\r | |
| 2183 | \r | |
| 2184 | @param ECX MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)\r | |
| 2185 | @param EAX Lower 32-bits of MSR value.\r | |
| 2186 | @param EDX Upper 32-bits of MSR value.\r | |
| 2187 | \r | |
| 2188 | <b>Example usage</b>\r | |
| 2189 | @code\r | |
| 2190 | UINT64 Msr;\r | |
| 2191 | \r | |
| 2192 | Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);\r | |
| 2193 | AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);\r | |
| 2194 | @endcode\r | |
| c2aa191b | 2195 | @note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r |
| bd946618 MK |
2196 | **/\r |
| 2197 | #define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57\r | |
| 2198 | \r | |
| 2199 | \r | |
| 2200 | /**\r | |
| 2201 | Package. Uncore B-box 1 perfmon local box control MSR.\r | |
| 2202 | \r | |
| 2203 | @param ECX MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)\r | |
| 2204 | @param EAX Lower 32-bits of MSR value.\r | |
| 2205 | @param EDX Upper 32-bits of MSR value.\r | |
| 2206 | \r | |
| 2207 | <b>Example usage</b>\r | |
| 2208 | @code\r | |
| 2209 | UINT64 Msr;\r | |
| 2210 | \r | |
| 2211 | Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);\r | |
| 2212 | AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);\r | |
| 2213 | @endcode\r | |
| c2aa191b | 2214 | @note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
2215 | **/\r |
| 2216 | #define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60\r | |
| 2217 | \r | |
| 2218 | \r | |
| 2219 | /**\r | |
| 2220 | Package. Uncore B-box 1 perfmon local box status MSR.\r | |
| 2221 | \r | |
| 2222 | @param ECX MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)\r | |
| 2223 | @param EAX Lower 32-bits of MSR value.\r | |
| 2224 | @param EDX Upper 32-bits of MSR value.\r | |
| 2225 | \r | |
| 2226 | <b>Example usage</b>\r | |
| 2227 | @code\r | |
| 2228 | UINT64 Msr;\r | |
| 2229 | \r | |
| 2230 | Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);\r | |
| 2231 | AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);\r | |
| 2232 | @endcode\r | |
| c2aa191b | 2233 | @note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
2234 | **/\r |
| 2235 | #define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61\r | |
| 2236 | \r | |
| 2237 | \r | |
| 2238 | /**\r | |
| 2239 | Package. Uncore B-box 1 perfmon local box overflow control MSR.\r | |
| 2240 | \r | |
| 2241 | @param ECX MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)\r | |
| 2242 | @param EAX Lower 32-bits of MSR value.\r | |
| 2243 | @param EDX Upper 32-bits of MSR value.\r | |
| 2244 | \r | |
| 2245 | <b>Example usage</b>\r | |
| 2246 | @code\r | |
| 2247 | UINT64 Msr;\r | |
| 2248 | \r | |
| 2249 | Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);\r | |
| 2250 | AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);\r | |
| 2251 | @endcode\r | |
| c2aa191b | 2252 | @note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
2253 | **/\r |
| 2254 | #define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62\r | |
| 2255 | \r | |
| 2256 | \r | |
| 2257 | /**\r | |
| 2258 | Package. Uncore B-box 1 perfmon event select MSR.\r | |
| 2259 | \r | |
| 2260 | @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)\r | |
| 2261 | @param EAX Lower 32-bits of MSR value.\r | |
| 2262 | @param EDX Upper 32-bits of MSR value.\r | |
| 2263 | \r | |
| 2264 | <b>Example usage</b>\r | |
| 2265 | @code\r | |
| 2266 | UINT64 Msr;\r | |
| 2267 | \r | |
| 2268 | Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);\r | |
| 2269 | AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);\r | |
| 2270 | @endcode\r | |
| c2aa191b | 2271 | @note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
2272 | **/\r |
| 2273 | #define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70\r | |
| 2274 | \r | |
| 2275 | \r | |
| 2276 | /**\r | |
| 2277 | Package. Uncore B-box 1 perfmon counter MSR.\r | |
| 2278 | \r | |
| 2279 | @param ECX MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)\r | |
| 2280 | @param EAX Lower 32-bits of MSR value.\r | |
| 2281 | @param EDX Upper 32-bits of MSR value.\r | |
| 2282 | \r | |
| 2283 | <b>Example usage</b>\r | |
| 2284 | @code\r | |
| 2285 | UINT64 Msr;\r | |
| 2286 | \r | |
| 2287 | Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);\r | |
| 2288 | AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);\r | |
| 2289 | @endcode\r | |
| c2aa191b | 2290 | @note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM.\r |
| bd946618 MK |
2291 | **/\r |
| 2292 | #define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71\r | |
| 2293 | \r | |
| 2294 | \r | |
| 2295 | /**\r | |
| 2296 | Package. Uncore B-box 1 perfmon event select MSR.\r | |
| 2297 | \r | |
| 2298 | @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)\r | |
| 2299 | @param EAX Lower 32-bits of MSR value.\r | |
| 2300 | @param EDX Upper 32-bits of MSR value.\r | |
| 2301 | \r | |
| 2302 | <b>Example usage</b>\r | |
| 2303 | @code\r | |
| 2304 | UINT64 Msr;\r | |
| 2305 | \r | |
| 2306 | Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);\r | |
| 2307 | AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);\r | |
| 2308 | @endcode\r | |
| c2aa191b | 2309 | @note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
2310 | **/\r |
| 2311 | #define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72\r | |
| 2312 | \r | |
| 2313 | \r | |
| 2314 | /**\r | |
| 2315 | Package. Uncore B-box 1 perfmon counter MSR.\r | |
| 2316 | \r | |
| 2317 | @param ECX MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)\r | |
| 2318 | @param EAX Lower 32-bits of MSR value.\r | |
| 2319 | @param EDX Upper 32-bits of MSR value.\r | |
| 2320 | \r | |
| 2321 | <b>Example usage</b>\r | |
| 2322 | @code\r | |
| 2323 | UINT64 Msr;\r | |
| 2324 | \r | |
| 2325 | Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);\r | |
| 2326 | AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);\r | |
| 2327 | @endcode\r | |
| c2aa191b | 2328 | @note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM.\r |
| bd946618 MK |
2329 | **/\r |
| 2330 | #define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73\r | |
| 2331 | \r | |
| 2332 | \r | |
| 2333 | /**\r | |
| 2334 | Package. Uncore B-box 1 perfmon event select MSR.\r | |
| 2335 | \r | |
| 2336 | @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)\r | |
| 2337 | @param EAX Lower 32-bits of MSR value.\r | |
| 2338 | @param EDX Upper 32-bits of MSR value.\r | |
| 2339 | \r | |
| 2340 | <b>Example usage</b>\r | |
| 2341 | @code\r | |
| 2342 | UINT64 Msr;\r | |
| 2343 | \r | |
| 2344 | Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);\r | |
| 2345 | AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);\r | |
| 2346 | @endcode\r | |
| c2aa191b | 2347 | @note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
2348 | **/\r |
| 2349 | #define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74\r | |
| 2350 | \r | |
| 2351 | \r | |
| 2352 | /**\r | |
| 2353 | Package. Uncore B-box 1 perfmon counter MSR.\r | |
| 2354 | \r | |
| 2355 | @param ECX MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)\r | |
| 2356 | @param EAX Lower 32-bits of MSR value.\r | |
| 2357 | @param EDX Upper 32-bits of MSR value.\r | |
| 2358 | \r | |
| 2359 | <b>Example usage</b>\r | |
| 2360 | @code\r | |
| 2361 | UINT64 Msr;\r | |
| 2362 | \r | |
| 2363 | Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);\r | |
| 2364 | AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);\r | |
| 2365 | @endcode\r | |
| c2aa191b | 2366 | @note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM.\r |
| bd946618 MK |
2367 | **/\r |
| 2368 | #define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75\r | |
| 2369 | \r | |
| 2370 | \r | |
| 2371 | /**\r | |
| 2372 | Package. Uncore B-box 1vperfmon event select MSR.\r | |
| 2373 | \r | |
| 2374 | @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)\r | |
| 2375 | @param EAX Lower 32-bits of MSR value.\r | |
| 2376 | @param EDX Upper 32-bits of MSR value.\r | |
| 2377 | \r | |
| 2378 | <b>Example usage</b>\r | |
| 2379 | @code\r | |
| 2380 | UINT64 Msr;\r | |
| 2381 | \r | |
| 2382 | Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);\r | |
| 2383 | AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);\r | |
| 2384 | @endcode\r | |
| c2aa191b | 2385 | @note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
2386 | **/\r |
| 2387 | #define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76\r | |
| 2388 | \r | |
| 2389 | \r | |
| 2390 | /**\r | |
| 2391 | Package. Uncore B-box 1 perfmon counter MSR.\r | |
| 2392 | \r | |
| 2393 | @param ECX MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)\r | |
| 2394 | @param EAX Lower 32-bits of MSR value.\r | |
| 2395 | @param EDX Upper 32-bits of MSR value.\r | |
| 2396 | \r | |
| 2397 | <b>Example usage</b>\r | |
| 2398 | @code\r | |
| 2399 | UINT64 Msr;\r | |
| 2400 | \r | |
| 2401 | Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);\r | |
| 2402 | AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);\r | |
| 2403 | @endcode\r | |
| c2aa191b | 2404 | @note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM.\r |
| bd946618 MK |
2405 | **/\r |
| 2406 | #define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77\r | |
| 2407 | \r | |
| 2408 | \r | |
| 2409 | /**\r | |
| 2410 | Package. Uncore W-box perfmon local box control MSR.\r | |
| 2411 | \r | |
| 2412 | @param ECX MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)\r | |
| 2413 | @param EAX Lower 32-bits of MSR value.\r | |
| 2414 | @param EDX Upper 32-bits of MSR value.\r | |
| 2415 | \r | |
| 2416 | <b>Example usage</b>\r | |
| 2417 | @code\r | |
| 2418 | UINT64 Msr;\r | |
| 2419 | \r | |
| 2420 | Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);\r | |
| 2421 | AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);\r | |
| 2422 | @endcode\r | |
| c2aa191b | 2423 | @note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
2424 | **/\r |
| 2425 | #define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80\r | |
| 2426 | \r | |
| 2427 | \r | |
| 2428 | /**\r | |
| 2429 | Package. Uncore W-box perfmon local box status MSR.\r | |
| 2430 | \r | |
| 2431 | @param ECX MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)\r | |
| 2432 | @param EAX Lower 32-bits of MSR value.\r | |
| 2433 | @param EDX Upper 32-bits of MSR value.\r | |
| 2434 | \r | |
| 2435 | <b>Example usage</b>\r | |
| 2436 | @code\r | |
| 2437 | UINT64 Msr;\r | |
| 2438 | \r | |
| 2439 | Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);\r | |
| 2440 | AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);\r | |
| 2441 | @endcode\r | |
| c2aa191b | 2442 | @note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
2443 | **/\r |
| 2444 | #define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81\r | |
| 2445 | \r | |
| 2446 | \r | |
| 2447 | /**\r | |
| 2448 | Package. Uncore W-box perfmon local box overflow control MSR.\r | |
| 2449 | \r | |
| 2450 | @param ECX MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)\r | |
| 2451 | @param EAX Lower 32-bits of MSR value.\r | |
| 2452 | @param EDX Upper 32-bits of MSR value.\r | |
| 2453 | \r | |
| 2454 | <b>Example usage</b>\r | |
| 2455 | @code\r | |
| 2456 | UINT64 Msr;\r | |
| 2457 | \r | |
| 2458 | Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);\r | |
| 2459 | AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);\r | |
| 2460 | @endcode\r | |
| c2aa191b | 2461 | @note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
2462 | **/\r |
| 2463 | #define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82\r | |
| 2464 | \r | |
| 2465 | \r | |
| 2466 | /**\r | |
| 2467 | Package. Uncore W-box perfmon event select MSR.\r | |
| 2468 | \r | |
| 2469 | @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)\r | |
| 2470 | @param EAX Lower 32-bits of MSR value.\r | |
| 2471 | @param EDX Upper 32-bits of MSR value.\r | |
| 2472 | \r | |
| 2473 | <b>Example usage</b>\r | |
| 2474 | @code\r | |
| 2475 | UINT64 Msr;\r | |
| 2476 | \r | |
| 2477 | Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);\r | |
| 2478 | AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);\r | |
| 2479 | @endcode\r | |
| c2aa191b | 2480 | @note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
2481 | **/\r |
| 2482 | #define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90\r | |
| 2483 | \r | |
| 2484 | \r | |
| 2485 | /**\r | |
| 2486 | Package. Uncore W-box perfmon counter MSR.\r | |
| 2487 | \r | |
| 2488 | @param ECX MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)\r | |
| 2489 | @param EAX Lower 32-bits of MSR value.\r | |
| 2490 | @param EDX Upper 32-bits of MSR value.\r | |
| 2491 | \r | |
| 2492 | <b>Example usage</b>\r | |
| 2493 | @code\r | |
| 2494 | UINT64 Msr;\r | |
| 2495 | \r | |
| 2496 | Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);\r | |
| 2497 | AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);\r | |
| 2498 | @endcode\r | |
| c2aa191b | 2499 | @note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM.\r |
| bd946618 MK |
2500 | **/\r |
| 2501 | #define MSR_NEHALEM_W_PMON_CTR0 0x00000C91\r | |
| 2502 | \r | |
| 2503 | \r | |
| 2504 | /**\r | |
| 2505 | Package. Uncore W-box perfmon event select MSR.\r | |
| 2506 | \r | |
| 2507 | @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)\r | |
| 2508 | @param EAX Lower 32-bits of MSR value.\r | |
| 2509 | @param EDX Upper 32-bits of MSR value.\r | |
| 2510 | \r | |
| 2511 | <b>Example usage</b>\r | |
| 2512 | @code\r | |
| 2513 | UINT64 Msr;\r | |
| 2514 | \r | |
| 2515 | Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);\r | |
| 2516 | AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);\r | |
| 2517 | @endcode\r | |
| c2aa191b | 2518 | @note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
2519 | **/\r |
| 2520 | #define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92\r | |
| 2521 | \r | |
| 2522 | \r | |
| 2523 | /**\r | |
| 2524 | Package. Uncore W-box perfmon counter MSR.\r | |
| 2525 | \r | |
| 2526 | @param ECX MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)\r | |
| 2527 | @param EAX Lower 32-bits of MSR value.\r | |
| 2528 | @param EDX Upper 32-bits of MSR value.\r | |
| 2529 | \r | |
| 2530 | <b>Example usage</b>\r | |
| 2531 | @code\r | |
| 2532 | UINT64 Msr;\r | |
| 2533 | \r | |
| 2534 | Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);\r | |
| 2535 | AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);\r | |
| 2536 | @endcode\r | |
| c2aa191b | 2537 | @note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM.\r |
| bd946618 MK |
2538 | **/\r |
| 2539 | #define MSR_NEHALEM_W_PMON_CTR1 0x00000C93\r | |
| 2540 | \r | |
| 2541 | \r | |
| 2542 | /**\r | |
| 2543 | Package. Uncore W-box perfmon event select MSR.\r | |
| 2544 | \r | |
| 2545 | @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)\r | |
| 2546 | @param EAX Lower 32-bits of MSR value.\r | |
| 2547 | @param EDX Upper 32-bits of MSR value.\r | |
| 2548 | \r | |
| 2549 | <b>Example usage</b>\r | |
| 2550 | @code\r | |
| 2551 | UINT64 Msr;\r | |
| 2552 | \r | |
| 2553 | Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);\r | |
| 2554 | AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);\r | |
| 2555 | @endcode\r | |
| c2aa191b | 2556 | @note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
2557 | **/\r |
| 2558 | #define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94\r | |
| 2559 | \r | |
| 2560 | \r | |
| 2561 | /**\r | |
| 2562 | Package. Uncore W-box perfmon counter MSR.\r | |
| 2563 | \r | |
| 2564 | @param ECX MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)\r | |
| 2565 | @param EAX Lower 32-bits of MSR value.\r | |
| 2566 | @param EDX Upper 32-bits of MSR value.\r | |
| 2567 | \r | |
| 2568 | <b>Example usage</b>\r | |
| 2569 | @code\r | |
| 2570 | UINT64 Msr;\r | |
| 2571 | \r | |
| 2572 | Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);\r | |
| 2573 | AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);\r | |
| 2574 | @endcode\r | |
| c2aa191b | 2575 | @note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM.\r |
| bd946618 MK |
2576 | **/\r |
| 2577 | #define MSR_NEHALEM_W_PMON_CTR2 0x00000C95\r | |
| 2578 | \r | |
| 2579 | \r | |
| 2580 | /**\r | |
| 2581 | Package. Uncore W-box perfmon event select MSR.\r | |
| 2582 | \r | |
| 2583 | @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)\r | |
| 2584 | @param EAX Lower 32-bits of MSR value.\r | |
| 2585 | @param EDX Upper 32-bits of MSR value.\r | |
| 2586 | \r | |
| 2587 | <b>Example usage</b>\r | |
| 2588 | @code\r | |
| 2589 | UINT64 Msr;\r | |
| 2590 | \r | |
| 2591 | Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);\r | |
| 2592 | AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);\r | |
| 2593 | @endcode\r | |
| c2aa191b | 2594 | @note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
2595 | **/\r |
| 2596 | #define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96\r | |
| 2597 | \r | |
| 2598 | \r | |
| 2599 | /**\r | |
| 2600 | Package. Uncore W-box perfmon counter MSR.\r | |
| 2601 | \r | |
| 2602 | @param ECX MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)\r | |
| 2603 | @param EAX Lower 32-bits of MSR value.\r | |
| 2604 | @param EDX Upper 32-bits of MSR value.\r | |
| 2605 | \r | |
| 2606 | <b>Example usage</b>\r | |
| 2607 | @code\r | |
| 2608 | UINT64 Msr;\r | |
| 2609 | \r | |
| 2610 | Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);\r | |
| 2611 | AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);\r | |
| 2612 | @endcode\r | |
| c2aa191b | 2613 | @note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM.\r |
| bd946618 MK |
2614 | **/\r |
| 2615 | #define MSR_NEHALEM_W_PMON_CTR3 0x00000C97\r | |
| 2616 | \r | |
| 2617 | \r | |
| 2618 | /**\r | |
| 2619 | Package. Uncore M-box 0 perfmon local box control MSR.\r | |
| 2620 | \r | |
| 2621 | @param ECX MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)\r | |
| 2622 | @param EAX Lower 32-bits of MSR value.\r | |
| 2623 | @param EDX Upper 32-bits of MSR value.\r | |
| 2624 | \r | |
| 2625 | <b>Example usage</b>\r | |
| 2626 | @code\r | |
| 2627 | UINT64 Msr;\r | |
| 2628 | \r | |
| 2629 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);\r | |
| 2630 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);\r | |
| 2631 | @endcode\r | |
| c2aa191b | 2632 | @note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
2633 | **/\r |
| 2634 | #define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0\r | |
| 2635 | \r | |
| 2636 | \r | |
| 2637 | /**\r | |
| 2638 | Package. Uncore M-box 0 perfmon local box status MSR.\r | |
| 2639 | \r | |
| 2640 | @param ECX MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)\r | |
| 2641 | @param EAX Lower 32-bits of MSR value.\r | |
| 2642 | @param EDX Upper 32-bits of MSR value.\r | |
| 2643 | \r | |
| 2644 | <b>Example usage</b>\r | |
| 2645 | @code\r | |
| 2646 | UINT64 Msr;\r | |
| 2647 | \r | |
| 2648 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);\r | |
| 2649 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);\r | |
| 2650 | @endcode\r | |
| c2aa191b | 2651 | @note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
2652 | **/\r |
| 2653 | #define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1\r | |
| 2654 | \r | |
| 2655 | \r | |
| 2656 | /**\r | |
| 2657 | Package. Uncore M-box 0 perfmon local box overflow control MSR.\r | |
| 2658 | \r | |
| 2659 | @param ECX MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)\r | |
| 2660 | @param EAX Lower 32-bits of MSR value.\r | |
| 2661 | @param EDX Upper 32-bits of MSR value.\r | |
| 2662 | \r | |
| 2663 | <b>Example usage</b>\r | |
| 2664 | @code\r | |
| 2665 | UINT64 Msr;\r | |
| 2666 | \r | |
| 2667 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);\r | |
| 2668 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);\r | |
| 2669 | @endcode\r | |
| c2aa191b | 2670 | @note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
2671 | **/\r |
| 2672 | #define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2\r | |
| 2673 | \r | |
| 2674 | \r | |
| 2675 | /**\r | |
| 2676 | Package. Uncore M-box 0 perfmon time stamp unit select MSR.\r | |
| 2677 | \r | |
| 2678 | @param ECX MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)\r | |
| 2679 | @param EAX Lower 32-bits of MSR value.\r | |
| 2680 | @param EDX Upper 32-bits of MSR value.\r | |
| 2681 | \r | |
| 2682 | <b>Example usage</b>\r | |
| 2683 | @code\r | |
| 2684 | UINT64 Msr;\r | |
| 2685 | \r | |
| 2686 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);\r | |
| 2687 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);\r | |
| 2688 | @endcode\r | |
| c2aa191b | 2689 | @note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM.\r |
| bd946618 MK |
2690 | **/\r |
| 2691 | #define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4\r | |
| 2692 | \r | |
| 2693 | \r | |
| 2694 | /**\r | |
| 2695 | Package. Uncore M-box 0 perfmon DSP unit select MSR.\r | |
| 2696 | \r | |
| 2697 | @param ECX MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)\r | |
| 2698 | @param EAX Lower 32-bits of MSR value.\r | |
| 2699 | @param EDX Upper 32-bits of MSR value.\r | |
| 2700 | \r | |
| 2701 | <b>Example usage</b>\r | |
| 2702 | @code\r | |
| 2703 | UINT64 Msr;\r | |
| 2704 | \r | |
| 2705 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);\r | |
| 2706 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);\r | |
| 2707 | @endcode\r | |
| c2aa191b | 2708 | @note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM.\r |
| bd946618 MK |
2709 | **/\r |
| 2710 | #define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5\r | |
| 2711 | \r | |
| 2712 | \r | |
| 2713 | /**\r | |
| 2714 | Package. Uncore M-box 0 perfmon ISS unit select MSR.\r | |
| 2715 | \r | |
| 2716 | @param ECX MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)\r | |
| 2717 | @param EAX Lower 32-bits of MSR value.\r | |
| 2718 | @param EDX Upper 32-bits of MSR value.\r | |
| 2719 | \r | |
| 2720 | <b>Example usage</b>\r | |
| 2721 | @code\r | |
| 2722 | UINT64 Msr;\r | |
| 2723 | \r | |
| 2724 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);\r | |
| 2725 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);\r | |
| 2726 | @endcode\r | |
| c2aa191b | 2727 | @note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM.\r |
| bd946618 MK |
2728 | **/\r |
| 2729 | #define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6\r | |
| 2730 | \r | |
| 2731 | \r | |
| 2732 | /**\r | |
| 2733 | Package. Uncore M-box 0 perfmon MAP unit select MSR.\r | |
| 2734 | \r | |
| 2735 | @param ECX MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)\r | |
| 2736 | @param EAX Lower 32-bits of MSR value.\r | |
| 2737 | @param EDX Upper 32-bits of MSR value.\r | |
| 2738 | \r | |
| 2739 | <b>Example usage</b>\r | |
| 2740 | @code\r | |
| 2741 | UINT64 Msr;\r | |
| 2742 | \r | |
| 2743 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);\r | |
| 2744 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);\r | |
| 2745 | @endcode\r | |
| c2aa191b | 2746 | @note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM.\r |
| bd946618 MK |
2747 | **/\r |
| 2748 | #define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7\r | |
| 2749 | \r | |
| 2750 | \r | |
| 2751 | /**\r | |
| 2752 | Package. Uncore M-box 0 perfmon MIC THR select MSR.\r | |
| 2753 | \r | |
| 2754 | @param ECX MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)\r | |
| 2755 | @param EAX Lower 32-bits of MSR value.\r | |
| 2756 | @param EDX Upper 32-bits of MSR value.\r | |
| 2757 | \r | |
| 2758 | <b>Example usage</b>\r | |
| 2759 | @code\r | |
| 2760 | UINT64 Msr;\r | |
| 2761 | \r | |
| 2762 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);\r | |
| 2763 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);\r | |
| 2764 | @endcode\r | |
| c2aa191b | 2765 | @note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM.\r |
| bd946618 MK |
2766 | **/\r |
| 2767 | #define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8\r | |
| 2768 | \r | |
| 2769 | \r | |
| 2770 | /**\r | |
| 2771 | Package. Uncore M-box 0 perfmon PGT unit select MSR.\r | |
| 2772 | \r | |
| 2773 | @param ECX MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)\r | |
| 2774 | @param EAX Lower 32-bits of MSR value.\r | |
| 2775 | @param EDX Upper 32-bits of MSR value.\r | |
| 2776 | \r | |
| 2777 | <b>Example usage</b>\r | |
| 2778 | @code\r | |
| 2779 | UINT64 Msr;\r | |
| 2780 | \r | |
| 2781 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);\r | |
| 2782 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);\r | |
| 2783 | @endcode\r | |
| c2aa191b | 2784 | @note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM.\r |
| bd946618 MK |
2785 | **/\r |
| 2786 | #define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9\r | |
| 2787 | \r | |
| 2788 | \r | |
| 2789 | /**\r | |
| 2790 | Package. Uncore M-box 0 perfmon PLD unit select MSR.\r | |
| 2791 | \r | |
| 2792 | @param ECX MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)\r | |
| 2793 | @param EAX Lower 32-bits of MSR value.\r | |
| 2794 | @param EDX Upper 32-bits of MSR value.\r | |
| 2795 | \r | |
| 2796 | <b>Example usage</b>\r | |
| 2797 | @code\r | |
| 2798 | UINT64 Msr;\r | |
| 2799 | \r | |
| 2800 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);\r | |
| 2801 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);\r | |
| 2802 | @endcode\r | |
| c2aa191b | 2803 | @note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM.\r |
| bd946618 MK |
2804 | **/\r |
| 2805 | #define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA\r | |
| 2806 | \r | |
| 2807 | \r | |
| 2808 | /**\r | |
| 2809 | Package. Uncore M-box 0 perfmon ZDP unit select MSR.\r | |
| 2810 | \r | |
| 2811 | @param ECX MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)\r | |
| 2812 | @param EAX Lower 32-bits of MSR value.\r | |
| 2813 | @param EDX Upper 32-bits of MSR value.\r | |
| 2814 | \r | |
| 2815 | <b>Example usage</b>\r | |
| 2816 | @code\r | |
| 2817 | UINT64 Msr;\r | |
| 2818 | \r | |
| 2819 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);\r | |
| 2820 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);\r | |
| 2821 | @endcode\r | |
| c2aa191b | 2822 | @note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM.\r |
| bd946618 MK |
2823 | **/\r |
| 2824 | #define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB\r | |
| 2825 | \r | |
| 2826 | \r | |
| 2827 | /**\r | |
| 2828 | Package. Uncore M-box 0 perfmon event select MSR.\r | |
| 2829 | \r | |
| 2830 | @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)\r | |
| 2831 | @param EAX Lower 32-bits of MSR value.\r | |
| 2832 | @param EDX Upper 32-bits of MSR value.\r | |
| 2833 | \r | |
| 2834 | <b>Example usage</b>\r | |
| 2835 | @code\r | |
| 2836 | UINT64 Msr;\r | |
| 2837 | \r | |
| 2838 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);\r | |
| 2839 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);\r | |
| 2840 | @endcode\r | |
| c2aa191b | 2841 | @note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
2842 | **/\r |
| 2843 | #define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0\r | |
| 2844 | \r | |
| 2845 | \r | |
| 2846 | /**\r | |
| 2847 | Package. Uncore M-box 0 perfmon counter MSR.\r | |
| 2848 | \r | |
| 2849 | @param ECX MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)\r | |
| 2850 | @param EAX Lower 32-bits of MSR value.\r | |
| 2851 | @param EDX Upper 32-bits of MSR value.\r | |
| 2852 | \r | |
| 2853 | <b>Example usage</b>\r | |
| 2854 | @code\r | |
| 2855 | UINT64 Msr;\r | |
| 2856 | \r | |
| 2857 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);\r | |
| 2858 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);\r | |
| 2859 | @endcode\r | |
| c2aa191b | 2860 | @note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM.\r |
| bd946618 MK |
2861 | **/\r |
| 2862 | #define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1\r | |
| 2863 | \r | |
| 2864 | \r | |
| 2865 | /**\r | |
| 2866 | Package. Uncore M-box 0 perfmon event select MSR.\r | |
| 2867 | \r | |
| 2868 | @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)\r | |
| 2869 | @param EAX Lower 32-bits of MSR value.\r | |
| 2870 | @param EDX Upper 32-bits of MSR value.\r | |
| 2871 | \r | |
| 2872 | <b>Example usage</b>\r | |
| 2873 | @code\r | |
| 2874 | UINT64 Msr;\r | |
| 2875 | \r | |
| 2876 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);\r | |
| 2877 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);\r | |
| 2878 | @endcode\r | |
| c2aa191b | 2879 | @note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
2880 | **/\r |
| 2881 | #define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2\r | |
| 2882 | \r | |
| 2883 | \r | |
| 2884 | /**\r | |
| 2885 | Package. Uncore M-box 0 perfmon counter MSR.\r | |
| 2886 | \r | |
| 2887 | @param ECX MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)\r | |
| 2888 | @param EAX Lower 32-bits of MSR value.\r | |
| 2889 | @param EDX Upper 32-bits of MSR value.\r | |
| 2890 | \r | |
| 2891 | <b>Example usage</b>\r | |
| 2892 | @code\r | |
| 2893 | UINT64 Msr;\r | |
| 2894 | \r | |
| 2895 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);\r | |
| 2896 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);\r | |
| 2897 | @endcode\r | |
| c2aa191b | 2898 | @note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM.\r |
| bd946618 MK |
2899 | **/\r |
| 2900 | #define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3\r | |
| 2901 | \r | |
| 2902 | \r | |
| 2903 | /**\r | |
| 2904 | Package. Uncore M-box 0 perfmon event select MSR.\r | |
| 2905 | \r | |
| 2906 | @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)\r | |
| 2907 | @param EAX Lower 32-bits of MSR value.\r | |
| 2908 | @param EDX Upper 32-bits of MSR value.\r | |
| 2909 | \r | |
| 2910 | <b>Example usage</b>\r | |
| 2911 | @code\r | |
| 2912 | UINT64 Msr;\r | |
| 2913 | \r | |
| 2914 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);\r | |
| 2915 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);\r | |
| 2916 | @endcode\r | |
| c2aa191b | 2917 | @note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
2918 | **/\r |
| 2919 | #define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4\r | |
| 2920 | \r | |
| 2921 | \r | |
| 2922 | /**\r | |
| 2923 | Package. Uncore M-box 0 perfmon counter MSR.\r | |
| 2924 | \r | |
| 2925 | @param ECX MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)\r | |
| 2926 | @param EAX Lower 32-bits of MSR value.\r | |
| 2927 | @param EDX Upper 32-bits of MSR value.\r | |
| 2928 | \r | |
| 2929 | <b>Example usage</b>\r | |
| 2930 | @code\r | |
| 2931 | UINT64 Msr;\r | |
| 2932 | \r | |
| 2933 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);\r | |
| 2934 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);\r | |
| 2935 | @endcode\r | |
| c2aa191b | 2936 | @note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM.\r |
| bd946618 MK |
2937 | **/\r |
| 2938 | #define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5\r | |
| 2939 | \r | |
| 2940 | \r | |
| 2941 | /**\r | |
| 2942 | Package. Uncore M-box 0 perfmon event select MSR.\r | |
| 2943 | \r | |
| 2944 | @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)\r | |
| 2945 | @param EAX Lower 32-bits of MSR value.\r | |
| 2946 | @param EDX Upper 32-bits of MSR value.\r | |
| 2947 | \r | |
| 2948 | <b>Example usage</b>\r | |
| 2949 | @code\r | |
| 2950 | UINT64 Msr;\r | |
| 2951 | \r | |
| 2952 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);\r | |
| 2953 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);\r | |
| 2954 | @endcode\r | |
| c2aa191b | 2955 | @note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
2956 | **/\r |
| 2957 | #define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6\r | |
| 2958 | \r | |
| 2959 | \r | |
| 2960 | /**\r | |
| 2961 | Package. Uncore M-box 0 perfmon counter MSR.\r | |
| 2962 | \r | |
| 2963 | @param ECX MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)\r | |
| 2964 | @param EAX Lower 32-bits of MSR value.\r | |
| 2965 | @param EDX Upper 32-bits of MSR value.\r | |
| 2966 | \r | |
| 2967 | <b>Example usage</b>\r | |
| 2968 | @code\r | |
| 2969 | UINT64 Msr;\r | |
| 2970 | \r | |
| 2971 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);\r | |
| 2972 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);\r | |
| 2973 | @endcode\r | |
| c2aa191b | 2974 | @note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM.\r |
| bd946618 MK |
2975 | **/\r |
| 2976 | #define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7\r | |
| 2977 | \r | |
| 2978 | \r | |
| 2979 | /**\r | |
| 2980 | Package. Uncore M-box 0 perfmon event select MSR.\r | |
| 2981 | \r | |
| 2982 | @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)\r | |
| 2983 | @param EAX Lower 32-bits of MSR value.\r | |
| 2984 | @param EDX Upper 32-bits of MSR value.\r | |
| 2985 | \r | |
| 2986 | <b>Example usage</b>\r | |
| 2987 | @code\r | |
| 2988 | UINT64 Msr;\r | |
| 2989 | \r | |
| 2990 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);\r | |
| 2991 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);\r | |
| 2992 | @endcode\r | |
| c2aa191b | 2993 | @note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM.\r |
| bd946618 MK |
2994 | **/\r |
| 2995 | #define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8\r | |
| 2996 | \r | |
| 2997 | \r | |
| 2998 | /**\r | |
| 2999 | Package. Uncore M-box 0 perfmon counter MSR.\r | |
| 3000 | \r | |
| 3001 | @param ECX MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)\r | |
| 3002 | @param EAX Lower 32-bits of MSR value.\r | |
| 3003 | @param EDX Upper 32-bits of MSR value.\r | |
| 3004 | \r | |
| 3005 | <b>Example usage</b>\r | |
| 3006 | @code\r | |
| 3007 | UINT64 Msr;\r | |
| 3008 | \r | |
| 3009 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);\r | |
| 3010 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);\r | |
| 3011 | @endcode\r | |
| c2aa191b | 3012 | @note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM.\r |
| bd946618 MK |
3013 | **/\r |
| 3014 | #define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9\r | |
| 3015 | \r | |
| 3016 | \r | |
| 3017 | /**\r | |
| 3018 | Package. Uncore M-box 0 perfmon event select MSR.\r | |
| 3019 | \r | |
| 3020 | @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)\r | |
| 3021 | @param EAX Lower 32-bits of MSR value.\r | |
| 3022 | @param EDX Upper 32-bits of MSR value.\r | |
| 3023 | \r | |
| 3024 | <b>Example usage</b>\r | |
| 3025 | @code\r | |
| 3026 | UINT64 Msr;\r | |
| 3027 | \r | |
| 3028 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);\r | |
| 3029 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);\r | |
| 3030 | @endcode\r | |
| c2aa191b | 3031 | @note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM.\r |
| bd946618 MK |
3032 | **/\r |
| 3033 | #define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA\r | |
| 3034 | \r | |
| 3035 | \r | |
| 3036 | /**\r | |
| 3037 | Package. Uncore M-box 0 perfmon counter MSR.\r | |
| 3038 | \r | |
| 3039 | @param ECX MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)\r | |
| 3040 | @param EAX Lower 32-bits of MSR value.\r | |
| 3041 | @param EDX Upper 32-bits of MSR value.\r | |
| 3042 | \r | |
| 3043 | <b>Example usage</b>\r | |
| 3044 | @code\r | |
| 3045 | UINT64 Msr;\r | |
| 3046 | \r | |
| 3047 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);\r | |
| 3048 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);\r | |
| 3049 | @endcode\r | |
| c2aa191b | 3050 | @note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM.\r |
| bd946618 MK |
3051 | **/\r |
| 3052 | #define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB\r | |
| 3053 | \r | |
| 3054 | \r | |
| 3055 | /**\r | |
| 3056 | Package. Uncore S-box 1 perfmon local box control MSR.\r | |
| 3057 | \r | |
| 3058 | @param ECX MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)\r | |
| 3059 | @param EAX Lower 32-bits of MSR value.\r | |
| 3060 | @param EDX Upper 32-bits of MSR value.\r | |
| 3061 | \r | |
| 3062 | <b>Example usage</b>\r | |
| 3063 | @code\r | |
| 3064 | UINT64 Msr;\r | |
| 3065 | \r | |
| 3066 | Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);\r | |
| 3067 | AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);\r | |
| 3068 | @endcode\r | |
| c2aa191b | 3069 | @note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
3070 | **/\r |
| 3071 | #define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0\r | |
| 3072 | \r | |
| 3073 | \r | |
| 3074 | /**\r | |
| 3075 | Package. Uncore S-box 1 perfmon local box status MSR.\r | |
| 3076 | \r | |
| 3077 | @param ECX MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)\r | |
| 3078 | @param EAX Lower 32-bits of MSR value.\r | |
| 3079 | @param EDX Upper 32-bits of MSR value.\r | |
| 3080 | \r | |
| 3081 | <b>Example usage</b>\r | |
| 3082 | @code\r | |
| 3083 | UINT64 Msr;\r | |
| 3084 | \r | |
| 3085 | Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);\r | |
| 3086 | AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);\r | |
| 3087 | @endcode\r | |
| c2aa191b | 3088 | @note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
3089 | **/\r |
| 3090 | #define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1\r | |
| 3091 | \r | |
| 3092 | \r | |
| 3093 | /**\r | |
| 3094 | Package. Uncore S-box 1 perfmon local box overflow control MSR.\r | |
| 3095 | \r | |
| 3096 | @param ECX MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)\r | |
| 3097 | @param EAX Lower 32-bits of MSR value.\r | |
| 3098 | @param EDX Upper 32-bits of MSR value.\r | |
| 3099 | \r | |
| 3100 | <b>Example usage</b>\r | |
| 3101 | @code\r | |
| 3102 | UINT64 Msr;\r | |
| 3103 | \r | |
| 3104 | Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);\r | |
| 3105 | AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);\r | |
| 3106 | @endcode\r | |
| c2aa191b | 3107 | @note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
3108 | **/\r |
| 3109 | #define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2\r | |
| 3110 | \r | |
| 3111 | \r | |
| 3112 | /**\r | |
| 3113 | Package. Uncore S-box 1 perfmon event select MSR.\r | |
| 3114 | \r | |
| 3115 | @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)\r | |
| 3116 | @param EAX Lower 32-bits of MSR value.\r | |
| 3117 | @param EDX Upper 32-bits of MSR value.\r | |
| 3118 | \r | |
| 3119 | <b>Example usage</b>\r | |
| 3120 | @code\r | |
| 3121 | UINT64 Msr;\r | |
| 3122 | \r | |
| 3123 | Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);\r | |
| 3124 | AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);\r | |
| 3125 | @endcode\r | |
| c2aa191b | 3126 | @note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
3127 | **/\r |
| 3128 | #define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0\r | |
| 3129 | \r | |
| 3130 | \r | |
| 3131 | /**\r | |
| 3132 | Package. Uncore S-box 1 perfmon counter MSR.\r | |
| 3133 | \r | |
| 3134 | @param ECX MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)\r | |
| 3135 | @param EAX Lower 32-bits of MSR value.\r | |
| 3136 | @param EDX Upper 32-bits of MSR value.\r | |
| 3137 | \r | |
| 3138 | <b>Example usage</b>\r | |
| 3139 | @code\r | |
| 3140 | UINT64 Msr;\r | |
| 3141 | \r | |
| 3142 | Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);\r | |
| 3143 | AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);\r | |
| 3144 | @endcode\r | |
| c2aa191b | 3145 | @note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r |
| bd946618 MK |
3146 | **/\r |
| 3147 | #define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1\r | |
| 3148 | \r | |
| 3149 | \r | |
| 3150 | /**\r | |
| 3151 | Package. Uncore S-box 1 perfmon event select MSR.\r | |
| 3152 | \r | |
| 3153 | @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)\r | |
| 3154 | @param EAX Lower 32-bits of MSR value.\r | |
| 3155 | @param EDX Upper 32-bits of MSR value.\r | |
| 3156 | \r | |
| 3157 | <b>Example usage</b>\r | |
| 3158 | @code\r | |
| 3159 | UINT64 Msr;\r | |
| 3160 | \r | |
| 3161 | Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);\r | |
| 3162 | AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);\r | |
| 3163 | @endcode\r | |
| c2aa191b | 3164 | @note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
3165 | **/\r |
| 3166 | #define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2\r | |
| 3167 | \r | |
| 3168 | \r | |
| 3169 | /**\r | |
| 3170 | Package. Uncore S-box 1 perfmon counter MSR.\r | |
| 3171 | \r | |
| 3172 | @param ECX MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)\r | |
| 3173 | @param EAX Lower 32-bits of MSR value.\r | |
| 3174 | @param EDX Upper 32-bits of MSR value.\r | |
| 3175 | \r | |
| 3176 | <b>Example usage</b>\r | |
| 3177 | @code\r | |
| 3178 | UINT64 Msr;\r | |
| 3179 | \r | |
| 3180 | Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);\r | |
| 3181 | AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);\r | |
| 3182 | @endcode\r | |
| c2aa191b | 3183 | @note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r |
| bd946618 MK |
3184 | **/\r |
| 3185 | #define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3\r | |
| 3186 | \r | |
| 3187 | \r | |
| 3188 | /**\r | |
| 3189 | Package. Uncore S-box 1 perfmon event select MSR.\r | |
| 3190 | \r | |
| 3191 | @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)\r | |
| 3192 | @param EAX Lower 32-bits of MSR value.\r | |
| 3193 | @param EDX Upper 32-bits of MSR value.\r | |
| 3194 | \r | |
| 3195 | <b>Example usage</b>\r | |
| 3196 | @code\r | |
| 3197 | UINT64 Msr;\r | |
| 3198 | \r | |
| 3199 | Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);\r | |
| 3200 | AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);\r | |
| 3201 | @endcode\r | |
| c2aa191b | 3202 | @note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
3203 | **/\r |
| 3204 | #define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4\r | |
| 3205 | \r | |
| 3206 | \r | |
| 3207 | /**\r | |
| 3208 | Package. Uncore S-box 1 perfmon counter MSR.\r | |
| 3209 | \r | |
| 3210 | @param ECX MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)\r | |
| 3211 | @param EAX Lower 32-bits of MSR value.\r | |
| 3212 | @param EDX Upper 32-bits of MSR value.\r | |
| 3213 | \r | |
| 3214 | <b>Example usage</b>\r | |
| 3215 | @code\r | |
| 3216 | UINT64 Msr;\r | |
| 3217 | \r | |
| 3218 | Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);\r | |
| 3219 | AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);\r | |
| 3220 | @endcode\r | |
| c2aa191b | 3221 | @note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r |
| bd946618 MK |
3222 | **/\r |
| 3223 | #define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5\r | |
| 3224 | \r | |
| 3225 | \r | |
| 3226 | /**\r | |
| 3227 | Package. Uncore S-box 1 perfmon event select MSR.\r | |
| 3228 | \r | |
| 3229 | @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)\r | |
| 3230 | @param EAX Lower 32-bits of MSR value.\r | |
| 3231 | @param EDX Upper 32-bits of MSR value.\r | |
| 3232 | \r | |
| 3233 | <b>Example usage</b>\r | |
| 3234 | @code\r | |
| 3235 | UINT64 Msr;\r | |
| 3236 | \r | |
| 3237 | Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);\r | |
| 3238 | AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);\r | |
| 3239 | @endcode\r | |
| c2aa191b | 3240 | @note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
3241 | **/\r |
| 3242 | #define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6\r | |
| 3243 | \r | |
| 3244 | \r | |
| 3245 | /**\r | |
| 3246 | Package. Uncore S-box 1 perfmon counter MSR.\r | |
| 3247 | \r | |
| 3248 | @param ECX MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)\r | |
| 3249 | @param EAX Lower 32-bits of MSR value.\r | |
| 3250 | @param EDX Upper 32-bits of MSR value.\r | |
| 3251 | \r | |
| 3252 | <b>Example usage</b>\r | |
| 3253 | @code\r | |
| 3254 | UINT64 Msr;\r | |
| 3255 | \r | |
| 3256 | Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);\r | |
| 3257 | AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);\r | |
| 3258 | @endcode\r | |
| c2aa191b | 3259 | @note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r |
| bd946618 MK |
3260 | **/\r |
| 3261 | #define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7\r | |
| 3262 | \r | |
| 3263 | \r | |
| 3264 | /**\r | |
| 3265 | Package. Uncore M-box 1 perfmon local box control MSR.\r | |
| 3266 | \r | |
| 3267 | @param ECX MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)\r | |
| 3268 | @param EAX Lower 32-bits of MSR value.\r | |
| 3269 | @param EDX Upper 32-bits of MSR value.\r | |
| 3270 | \r | |
| 3271 | <b>Example usage</b>\r | |
| 3272 | @code\r | |
| 3273 | UINT64 Msr;\r | |
| 3274 | \r | |
| 3275 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);\r | |
| 3276 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);\r | |
| 3277 | @endcode\r | |
| c2aa191b | 3278 | @note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
3279 | **/\r |
| 3280 | #define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0\r | |
| 3281 | \r | |
| 3282 | \r | |
| 3283 | /**\r | |
| 3284 | Package. Uncore M-box 1 perfmon local box status MSR.\r | |
| 3285 | \r | |
| 3286 | @param ECX MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)\r | |
| 3287 | @param EAX Lower 32-bits of MSR value.\r | |
| 3288 | @param EDX Upper 32-bits of MSR value.\r | |
| 3289 | \r | |
| 3290 | <b>Example usage</b>\r | |
| 3291 | @code\r | |
| 3292 | UINT64 Msr;\r | |
| 3293 | \r | |
| 3294 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);\r | |
| 3295 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);\r | |
| 3296 | @endcode\r | |
| c2aa191b | 3297 | @note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
3298 | **/\r |
| 3299 | #define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1\r | |
| 3300 | \r | |
| 3301 | \r | |
| 3302 | /**\r | |
| 3303 | Package. Uncore M-box 1 perfmon local box overflow control MSR.\r | |
| 3304 | \r | |
| 3305 | @param ECX MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)\r | |
| 3306 | @param EAX Lower 32-bits of MSR value.\r | |
| 3307 | @param EDX Upper 32-bits of MSR value.\r | |
| 3308 | \r | |
| 3309 | <b>Example usage</b>\r | |
| 3310 | @code\r | |
| 3311 | UINT64 Msr;\r | |
| 3312 | \r | |
| 3313 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);\r | |
| 3314 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);\r | |
| 3315 | @endcode\r | |
| c2aa191b | 3316 | @note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
3317 | **/\r |
| 3318 | #define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2\r | |
| 3319 | \r | |
| 3320 | \r | |
| 3321 | /**\r | |
| 3322 | Package. Uncore M-box 1 perfmon time stamp unit select MSR.\r | |
| 3323 | \r | |
| 3324 | @param ECX MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)\r | |
| 3325 | @param EAX Lower 32-bits of MSR value.\r | |
| 3326 | @param EDX Upper 32-bits of MSR value.\r | |
| 3327 | \r | |
| 3328 | <b>Example usage</b>\r | |
| 3329 | @code\r | |
| 3330 | UINT64 Msr;\r | |
| 3331 | \r | |
| 3332 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);\r | |
| 3333 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);\r | |
| 3334 | @endcode\r | |
| c2aa191b | 3335 | @note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM.\r |
| bd946618 MK |
3336 | **/\r |
| 3337 | #define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4\r | |
| 3338 | \r | |
| 3339 | \r | |
| 3340 | /**\r | |
| 3341 | Package. Uncore M-box 1 perfmon DSP unit select MSR.\r | |
| 3342 | \r | |
| 3343 | @param ECX MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)\r | |
| 3344 | @param EAX Lower 32-bits of MSR value.\r | |
| 3345 | @param EDX Upper 32-bits of MSR value.\r | |
| 3346 | \r | |
| 3347 | <b>Example usage</b>\r | |
| 3348 | @code\r | |
| 3349 | UINT64 Msr;\r | |
| 3350 | \r | |
| 3351 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);\r | |
| 3352 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);\r | |
| 3353 | @endcode\r | |
| c2aa191b | 3354 | @note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM.\r |
| bd946618 MK |
3355 | **/\r |
| 3356 | #define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5\r | |
| 3357 | \r | |
| 3358 | \r | |
| 3359 | /**\r | |
| 3360 | Package. Uncore M-box 1 perfmon ISS unit select MSR.\r | |
| 3361 | \r | |
| 3362 | @param ECX MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)\r | |
| 3363 | @param EAX Lower 32-bits of MSR value.\r | |
| 3364 | @param EDX Upper 32-bits of MSR value.\r | |
| 3365 | \r | |
| 3366 | <b>Example usage</b>\r | |
| 3367 | @code\r | |
| 3368 | UINT64 Msr;\r | |
| 3369 | \r | |
| 3370 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);\r | |
| 3371 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);\r | |
| 3372 | @endcode\r | |
| c2aa191b | 3373 | @note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM.\r |
| bd946618 MK |
3374 | **/\r |
| 3375 | #define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6\r | |
| 3376 | \r | |
| 3377 | \r | |
| 3378 | /**\r | |
| 3379 | Package. Uncore M-box 1 perfmon MAP unit select MSR.\r | |
| 3380 | \r | |
| 3381 | @param ECX MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)\r | |
| 3382 | @param EAX Lower 32-bits of MSR value.\r | |
| 3383 | @param EDX Upper 32-bits of MSR value.\r | |
| 3384 | \r | |
| 3385 | <b>Example usage</b>\r | |
| 3386 | @code\r | |
| 3387 | UINT64 Msr;\r | |
| 3388 | \r | |
| 3389 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);\r | |
| 3390 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);\r | |
| 3391 | @endcode\r | |
| c2aa191b | 3392 | @note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM.\r |
| bd946618 MK |
3393 | **/\r |
| 3394 | #define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7\r | |
| 3395 | \r | |
| 3396 | \r | |
| 3397 | /**\r | |
| 3398 | Package. Uncore M-box 1 perfmon MIC THR select MSR.\r | |
| 3399 | \r | |
| 3400 | @param ECX MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)\r | |
| 3401 | @param EAX Lower 32-bits of MSR value.\r | |
| 3402 | @param EDX Upper 32-bits of MSR value.\r | |
| 3403 | \r | |
| 3404 | <b>Example usage</b>\r | |
| 3405 | @code\r | |
| 3406 | UINT64 Msr;\r | |
| 3407 | \r | |
| 3408 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);\r | |
| 3409 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);\r | |
| 3410 | @endcode\r | |
| c2aa191b | 3411 | @note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM.\r |
| bd946618 MK |
3412 | **/\r |
| 3413 | #define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8\r | |
| 3414 | \r | |
| 3415 | \r | |
| 3416 | /**\r | |
| 3417 | Package. Uncore M-box 1 perfmon PGT unit select MSR.\r | |
| 3418 | \r | |
| 3419 | @param ECX MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)\r | |
| 3420 | @param EAX Lower 32-bits of MSR value.\r | |
| 3421 | @param EDX Upper 32-bits of MSR value.\r | |
| 3422 | \r | |
| 3423 | <b>Example usage</b>\r | |
| 3424 | @code\r | |
| 3425 | UINT64 Msr;\r | |
| 3426 | \r | |
| 3427 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);\r | |
| 3428 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);\r | |
| 3429 | @endcode\r | |
| c2aa191b | 3430 | @note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM.\r |
| bd946618 MK |
3431 | **/\r |
| 3432 | #define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9\r | |
| 3433 | \r | |
| 3434 | \r | |
| 3435 | /**\r | |
| 3436 | Package. Uncore M-box 1 perfmon PLD unit select MSR.\r | |
| 3437 | \r | |
| 3438 | @param ECX MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)\r | |
| 3439 | @param EAX Lower 32-bits of MSR value.\r | |
| 3440 | @param EDX Upper 32-bits of MSR value.\r | |
| 3441 | \r | |
| 3442 | <b>Example usage</b>\r | |
| 3443 | @code\r | |
| 3444 | UINT64 Msr;\r | |
| 3445 | \r | |
| 3446 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);\r | |
| 3447 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);\r | |
| 3448 | @endcode\r | |
| c2aa191b | 3449 | @note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM.\r |
| bd946618 MK |
3450 | **/\r |
| 3451 | #define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA\r | |
| 3452 | \r | |
| 3453 | \r | |
| 3454 | /**\r | |
| 3455 | Package. Uncore M-box 1 perfmon ZDP unit select MSR.\r | |
| 3456 | \r | |
| 3457 | @param ECX MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)\r | |
| 3458 | @param EAX Lower 32-bits of MSR value.\r | |
| 3459 | @param EDX Upper 32-bits of MSR value.\r | |
| 3460 | \r | |
| 3461 | <b>Example usage</b>\r | |
| 3462 | @code\r | |
| 3463 | UINT64 Msr;\r | |
| 3464 | \r | |
| 3465 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);\r | |
| 3466 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);\r | |
| 3467 | @endcode\r | |
| c2aa191b | 3468 | @note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM.\r |
| bd946618 MK |
3469 | **/\r |
| 3470 | #define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB\r | |
| 3471 | \r | |
| 3472 | \r | |
| 3473 | /**\r | |
| 3474 | Package. Uncore M-box 1 perfmon event select MSR.\r | |
| 3475 | \r | |
| 3476 | @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)\r | |
| 3477 | @param EAX Lower 32-bits of MSR value.\r | |
| 3478 | @param EDX Upper 32-bits of MSR value.\r | |
| 3479 | \r | |
| 3480 | <b>Example usage</b>\r | |
| 3481 | @code\r | |
| 3482 | UINT64 Msr;\r | |
| 3483 | \r | |
| 3484 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);\r | |
| 3485 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);\r | |
| 3486 | @endcode\r | |
| c2aa191b | 3487 | @note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
3488 | **/\r |
| 3489 | #define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0\r | |
| 3490 | \r | |
| 3491 | \r | |
| 3492 | /**\r | |
| 3493 | Package. Uncore M-box 1 perfmon counter MSR.\r | |
| 3494 | \r | |
| 3495 | @param ECX MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)\r | |
| 3496 | @param EAX Lower 32-bits of MSR value.\r | |
| 3497 | @param EDX Upper 32-bits of MSR value.\r | |
| 3498 | \r | |
| 3499 | <b>Example usage</b>\r | |
| 3500 | @code\r | |
| 3501 | UINT64 Msr;\r | |
| 3502 | \r | |
| 3503 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);\r | |
| 3504 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);\r | |
| 3505 | @endcode\r | |
| c2aa191b | 3506 | @note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM.\r |
| bd946618 MK |
3507 | **/\r |
| 3508 | #define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1\r | |
| 3509 | \r | |
| 3510 | \r | |
| 3511 | /**\r | |
| 3512 | Package. Uncore M-box 1 perfmon event select MSR.\r | |
| 3513 | \r | |
| 3514 | @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)\r | |
| 3515 | @param EAX Lower 32-bits of MSR value.\r | |
| 3516 | @param EDX Upper 32-bits of MSR value.\r | |
| 3517 | \r | |
| 3518 | <b>Example usage</b>\r | |
| 3519 | @code\r | |
| 3520 | UINT64 Msr;\r | |
| 3521 | \r | |
| 3522 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);\r | |
| 3523 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);\r | |
| 3524 | @endcode\r | |
| c2aa191b | 3525 | @note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
3526 | **/\r |
| 3527 | #define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2\r | |
| 3528 | \r | |
| 3529 | \r | |
| 3530 | /**\r | |
| 3531 | Package. Uncore M-box 1 perfmon counter MSR.\r | |
| 3532 | \r | |
| 3533 | @param ECX MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)\r | |
| 3534 | @param EAX Lower 32-bits of MSR value.\r | |
| 3535 | @param EDX Upper 32-bits of MSR value.\r | |
| 3536 | \r | |
| 3537 | <b>Example usage</b>\r | |
| 3538 | @code\r | |
| 3539 | UINT64 Msr;\r | |
| 3540 | \r | |
| 3541 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);\r | |
| 3542 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);\r | |
| 3543 | @endcode\r | |
| c2aa191b | 3544 | @note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM.\r |
| bd946618 MK |
3545 | **/\r |
| 3546 | #define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3\r | |
| 3547 | \r | |
| 3548 | \r | |
| 3549 | /**\r | |
| 3550 | Package. Uncore M-box 1 perfmon event select MSR.\r | |
| 3551 | \r | |
| 3552 | @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)\r | |
| 3553 | @param EAX Lower 32-bits of MSR value.\r | |
| 3554 | @param EDX Upper 32-bits of MSR value.\r | |
| 3555 | \r | |
| 3556 | <b>Example usage</b>\r | |
| 3557 | @code\r | |
| 3558 | UINT64 Msr;\r | |
| 3559 | \r | |
| 3560 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);\r | |
| 3561 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);\r | |
| 3562 | @endcode\r | |
| c2aa191b | 3563 | @note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
3564 | **/\r |
| 3565 | #define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4\r | |
| 3566 | \r | |
| 3567 | \r | |
| 3568 | /**\r | |
| 3569 | Package. Uncore M-box 1 perfmon counter MSR.\r | |
| 3570 | \r | |
| 3571 | @param ECX MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)\r | |
| 3572 | @param EAX Lower 32-bits of MSR value.\r | |
| 3573 | @param EDX Upper 32-bits of MSR value.\r | |
| 3574 | \r | |
| 3575 | <b>Example usage</b>\r | |
| 3576 | @code\r | |
| 3577 | UINT64 Msr;\r | |
| 3578 | \r | |
| 3579 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);\r | |
| 3580 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);\r | |
| 3581 | @endcode\r | |
| c2aa191b | 3582 | @note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM.\r |
| bd946618 MK |
3583 | **/\r |
| 3584 | #define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5\r | |
| 3585 | \r | |
| 3586 | \r | |
| 3587 | /**\r | |
| 3588 | Package. Uncore M-box 1 perfmon event select MSR.\r | |
| 3589 | \r | |
| 3590 | @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)\r | |
| 3591 | @param EAX Lower 32-bits of MSR value.\r | |
| 3592 | @param EDX Upper 32-bits of MSR value.\r | |
| 3593 | \r | |
| 3594 | <b>Example usage</b>\r | |
| 3595 | @code\r | |
| 3596 | UINT64 Msr;\r | |
| 3597 | \r | |
| 3598 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);\r | |
| 3599 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);\r | |
| 3600 | @endcode\r | |
| c2aa191b | 3601 | @note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
3602 | **/\r |
| 3603 | #define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6\r | |
| 3604 | \r | |
| 3605 | \r | |
| 3606 | /**\r | |
| 3607 | Package. Uncore M-box 1 perfmon counter MSR.\r | |
| 3608 | \r | |
| 3609 | @param ECX MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)\r | |
| 3610 | @param EAX Lower 32-bits of MSR value.\r | |
| 3611 | @param EDX Upper 32-bits of MSR value.\r | |
| 3612 | \r | |
| 3613 | <b>Example usage</b>\r | |
| 3614 | @code\r | |
| 3615 | UINT64 Msr;\r | |
| 3616 | \r | |
| 3617 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);\r | |
| 3618 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);\r | |
| 3619 | @endcode\r | |
| c2aa191b | 3620 | @note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM.\r |
| bd946618 MK |
3621 | **/\r |
| 3622 | #define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7\r | |
| 3623 | \r | |
| 3624 | \r | |
| 3625 | /**\r | |
| 3626 | Package. Uncore M-box 1 perfmon event select MSR.\r | |
| 3627 | \r | |
| 3628 | @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)\r | |
| 3629 | @param EAX Lower 32-bits of MSR value.\r | |
| 3630 | @param EDX Upper 32-bits of MSR value.\r | |
| 3631 | \r | |
| 3632 | <b>Example usage</b>\r | |
| 3633 | @code\r | |
| 3634 | UINT64 Msr;\r | |
| 3635 | \r | |
| 3636 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);\r | |
| 3637 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);\r | |
| 3638 | @endcode\r | |
| c2aa191b | 3639 | @note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM.\r |
| bd946618 MK |
3640 | **/\r |
| 3641 | #define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8\r | |
| 3642 | \r | |
| 3643 | \r | |
| 3644 | /**\r | |
| 3645 | Package. Uncore M-box 1 perfmon counter MSR.\r | |
| 3646 | \r | |
| 3647 | @param ECX MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)\r | |
| 3648 | @param EAX Lower 32-bits of MSR value.\r | |
| 3649 | @param EDX Upper 32-bits of MSR value.\r | |
| 3650 | \r | |
| 3651 | <b>Example usage</b>\r | |
| 3652 | @code\r | |
| 3653 | UINT64 Msr;\r | |
| 3654 | \r | |
| 3655 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);\r | |
| 3656 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);\r | |
| 3657 | @endcode\r | |
| c2aa191b | 3658 | @note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM.\r |
| bd946618 MK |
3659 | **/\r |
| 3660 | #define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9\r | |
| 3661 | \r | |
| 3662 | \r | |
| 3663 | /**\r | |
| 3664 | Package. Uncore M-box 1 perfmon event select MSR.\r | |
| 3665 | \r | |
| 3666 | @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)\r | |
| 3667 | @param EAX Lower 32-bits of MSR value.\r | |
| 3668 | @param EDX Upper 32-bits of MSR value.\r | |
| 3669 | \r | |
| 3670 | <b>Example usage</b>\r | |
| 3671 | @code\r | |
| 3672 | UINT64 Msr;\r | |
| 3673 | \r | |
| 3674 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);\r | |
| 3675 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);\r | |
| 3676 | @endcode\r | |
| c2aa191b | 3677 | @note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM.\r |
| bd946618 MK |
3678 | **/\r |
| 3679 | #define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA\r | |
| 3680 | \r | |
| 3681 | \r | |
| 3682 | /**\r | |
| 3683 | Package. Uncore M-box 1 perfmon counter MSR.\r | |
| 3684 | \r | |
| 3685 | @param ECX MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)\r | |
| 3686 | @param EAX Lower 32-bits of MSR value.\r | |
| 3687 | @param EDX Upper 32-bits of MSR value.\r | |
| 3688 | \r | |
| 3689 | <b>Example usage</b>\r | |
| 3690 | @code\r | |
| 3691 | UINT64 Msr;\r | |
| 3692 | \r | |
| 3693 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);\r | |
| 3694 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);\r | |
| 3695 | @endcode\r | |
| c2aa191b | 3696 | @note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM.\r |
| bd946618 MK |
3697 | **/\r |
| 3698 | #define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB\r | |
| 3699 | \r | |
| 3700 | \r | |
| 3701 | /**\r | |
| 3702 | Package. Uncore C-box 0 perfmon local box control MSR.\r | |
| 3703 | \r | |
| 3704 | @param ECX MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)\r | |
| 3705 | @param EAX Lower 32-bits of MSR value.\r | |
| 3706 | @param EDX Upper 32-bits of MSR value.\r | |
| 3707 | \r | |
| 3708 | <b>Example usage</b>\r | |
| 3709 | @code\r | |
| 3710 | UINT64 Msr;\r | |
| 3711 | \r | |
| 3712 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);\r | |
| 3713 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);\r | |
| 3714 | @endcode\r | |
| c2aa191b | 3715 | @note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
3716 | **/\r |
| 3717 | #define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00\r | |
| 3718 | \r | |
| 3719 | \r | |
| 3720 | /**\r | |
| 3721 | Package. Uncore C-box 0 perfmon local box status MSR.\r | |
| 3722 | \r | |
| 3723 | @param ECX MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)\r | |
| 3724 | @param EAX Lower 32-bits of MSR value.\r | |
| 3725 | @param EDX Upper 32-bits of MSR value.\r | |
| 3726 | \r | |
| 3727 | <b>Example usage</b>\r | |
| 3728 | @code\r | |
| 3729 | UINT64 Msr;\r | |
| 3730 | \r | |
| 3731 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);\r | |
| 3732 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);\r | |
| 3733 | @endcode\r | |
| c2aa191b | 3734 | @note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
3735 | **/\r |
| 3736 | #define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01\r | |
| 3737 | \r | |
| 3738 | \r | |
| 3739 | /**\r | |
| 3740 | Package. Uncore C-box 0 perfmon local box overflow control MSR.\r | |
| 3741 | \r | |
| 3742 | @param ECX MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)\r | |
| 3743 | @param EAX Lower 32-bits of MSR value.\r | |
| 3744 | @param EDX Upper 32-bits of MSR value.\r | |
| 3745 | \r | |
| 3746 | <b>Example usage</b>\r | |
| 3747 | @code\r | |
| 3748 | UINT64 Msr;\r | |
| 3749 | \r | |
| 3750 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);\r | |
| 3751 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);\r | |
| 3752 | @endcode\r | |
| c2aa191b | 3753 | @note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
3754 | **/\r |
| 3755 | #define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02\r | |
| 3756 | \r | |
| 3757 | \r | |
| 3758 | /**\r | |
| 3759 | Package. Uncore C-box 0 perfmon event select MSR.\r | |
| 3760 | \r | |
| 3761 | @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)\r | |
| 3762 | @param EAX Lower 32-bits of MSR value.\r | |
| 3763 | @param EDX Upper 32-bits of MSR value.\r | |
| 3764 | \r | |
| 3765 | <b>Example usage</b>\r | |
| 3766 | @code\r | |
| 3767 | UINT64 Msr;\r | |
| 3768 | \r | |
| 3769 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);\r | |
| 3770 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);\r | |
| 3771 | @endcode\r | |
| c2aa191b | 3772 | @note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
3773 | **/\r |
| 3774 | #define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10\r | |
| 3775 | \r | |
| 3776 | \r | |
| 3777 | /**\r | |
| 3778 | Package. Uncore C-box 0 perfmon counter MSR.\r | |
| 3779 | \r | |
| 3780 | @param ECX MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)\r | |
| 3781 | @param EAX Lower 32-bits of MSR value.\r | |
| 3782 | @param EDX Upper 32-bits of MSR value.\r | |
| 3783 | \r | |
| 3784 | <b>Example usage</b>\r | |
| 3785 | @code\r | |
| 3786 | UINT64 Msr;\r | |
| 3787 | \r | |
| 3788 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);\r | |
| 3789 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);\r | |
| 3790 | @endcode\r | |
| c2aa191b | 3791 | @note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r |
| bd946618 MK |
3792 | **/\r |
| 3793 | #define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11\r | |
| 3794 | \r | |
| 3795 | \r | |
| 3796 | /**\r | |
| 3797 | Package. Uncore C-box 0 perfmon event select MSR.\r | |
| 3798 | \r | |
| 3799 | @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)\r | |
| 3800 | @param EAX Lower 32-bits of MSR value.\r | |
| 3801 | @param EDX Upper 32-bits of MSR value.\r | |
| 3802 | \r | |
| 3803 | <b>Example usage</b>\r | |
| 3804 | @code\r | |
| 3805 | UINT64 Msr;\r | |
| 3806 | \r | |
| 3807 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);\r | |
| 3808 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);\r | |
| 3809 | @endcode\r | |
| c2aa191b | 3810 | @note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
3811 | **/\r |
| 3812 | #define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12\r | |
| 3813 | \r | |
| 3814 | \r | |
| 3815 | /**\r | |
| 3816 | Package. Uncore C-box 0 perfmon counter MSR.\r | |
| 3817 | \r | |
| 3818 | @param ECX MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)\r | |
| 3819 | @param EAX Lower 32-bits of MSR value.\r | |
| 3820 | @param EDX Upper 32-bits of MSR value.\r | |
| 3821 | \r | |
| 3822 | <b>Example usage</b>\r | |
| 3823 | @code\r | |
| 3824 | UINT64 Msr;\r | |
| 3825 | \r | |
| 3826 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);\r | |
| 3827 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);\r | |
| 3828 | @endcode\r | |
| c2aa191b | 3829 | @note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r |
| bd946618 MK |
3830 | **/\r |
| 3831 | #define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13\r | |
| 3832 | \r | |
| 3833 | \r | |
| 3834 | /**\r | |
| 3835 | Package. Uncore C-box 0 perfmon event select MSR.\r | |
| 3836 | \r | |
| 3837 | @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)\r | |
| 3838 | @param EAX Lower 32-bits of MSR value.\r | |
| 3839 | @param EDX Upper 32-bits of MSR value.\r | |
| 3840 | \r | |
| 3841 | <b>Example usage</b>\r | |
| 3842 | @code\r | |
| 3843 | UINT64 Msr;\r | |
| 3844 | \r | |
| 3845 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);\r | |
| 3846 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);\r | |
| 3847 | @endcode\r | |
| c2aa191b | 3848 | @note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
3849 | **/\r |
| 3850 | #define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14\r | |
| 3851 | \r | |
| 3852 | \r | |
| 3853 | /**\r | |
| 3854 | Package. Uncore C-box 0 perfmon counter MSR.\r | |
| 3855 | \r | |
| 3856 | @param ECX MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)\r | |
| 3857 | @param EAX Lower 32-bits of MSR value.\r | |
| 3858 | @param EDX Upper 32-bits of MSR value.\r | |
| 3859 | \r | |
| 3860 | <b>Example usage</b>\r | |
| 3861 | @code\r | |
| 3862 | UINT64 Msr;\r | |
| 3863 | \r | |
| 3864 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);\r | |
| 3865 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);\r | |
| 3866 | @endcode\r | |
| c2aa191b | 3867 | @note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r |
| bd946618 MK |
3868 | **/\r |
| 3869 | #define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15\r | |
| 3870 | \r | |
| 3871 | \r | |
| 3872 | /**\r | |
| 3873 | Package. Uncore C-box 0 perfmon event select MSR.\r | |
| 3874 | \r | |
| 3875 | @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)\r | |
| 3876 | @param EAX Lower 32-bits of MSR value.\r | |
| 3877 | @param EDX Upper 32-bits of MSR value.\r | |
| 3878 | \r | |
| 3879 | <b>Example usage</b>\r | |
| 3880 | @code\r | |
| 3881 | UINT64 Msr;\r | |
| 3882 | \r | |
| 3883 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);\r | |
| 3884 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);\r | |
| 3885 | @endcode\r | |
| c2aa191b | 3886 | @note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
3887 | **/\r |
| 3888 | #define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16\r | |
| 3889 | \r | |
| 3890 | \r | |
| 3891 | /**\r | |
| 3892 | Package. Uncore C-box 0 perfmon counter MSR.\r | |
| 3893 | \r | |
| 3894 | @param ECX MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)\r | |
| 3895 | @param EAX Lower 32-bits of MSR value.\r | |
| 3896 | @param EDX Upper 32-bits of MSR value.\r | |
| 3897 | \r | |
| 3898 | <b>Example usage</b>\r | |
| 3899 | @code\r | |
| 3900 | UINT64 Msr;\r | |
| 3901 | \r | |
| 3902 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);\r | |
| 3903 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);\r | |
| 3904 | @endcode\r | |
| c2aa191b | 3905 | @note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r |
| bd946618 MK |
3906 | **/\r |
| 3907 | #define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17\r | |
| 3908 | \r | |
| 3909 | \r | |
| 3910 | /**\r | |
| 3911 | Package. Uncore C-box 0 perfmon event select MSR.\r | |
| 3912 | \r | |
| 3913 | @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)\r | |
| 3914 | @param EAX Lower 32-bits of MSR value.\r | |
| 3915 | @param EDX Upper 32-bits of MSR value.\r | |
| 3916 | \r | |
| 3917 | <b>Example usage</b>\r | |
| 3918 | @code\r | |
| 3919 | UINT64 Msr;\r | |
| 3920 | \r | |
| 3921 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);\r | |
| 3922 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);\r | |
| 3923 | @endcode\r | |
| c2aa191b | 3924 | @note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM.\r |
| bd946618 MK |
3925 | **/\r |
| 3926 | #define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18\r | |
| 3927 | \r | |
| 3928 | \r | |
| 3929 | /**\r | |
| 3930 | Package. Uncore C-box 0 perfmon counter MSR.\r | |
| 3931 | \r | |
| 3932 | @param ECX MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)\r | |
| 3933 | @param EAX Lower 32-bits of MSR value.\r | |
| 3934 | @param EDX Upper 32-bits of MSR value.\r | |
| 3935 | \r | |
| 3936 | <b>Example usage</b>\r | |
| 3937 | @code\r | |
| 3938 | UINT64 Msr;\r | |
| 3939 | \r | |
| 3940 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);\r | |
| 3941 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);\r | |
| 3942 | @endcode\r | |
| c2aa191b | 3943 | @note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM.\r |
| bd946618 MK |
3944 | **/\r |
| 3945 | #define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19\r | |
| 3946 | \r | |
| 3947 | \r | |
| 3948 | /**\r | |
| 3949 | Package. Uncore C-box 0 perfmon event select MSR.\r | |
| 3950 | \r | |
| 3951 | @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)\r | |
| 3952 | @param EAX Lower 32-bits of MSR value.\r | |
| 3953 | @param EDX Upper 32-bits of MSR value.\r | |
| 3954 | \r | |
| 3955 | <b>Example usage</b>\r | |
| 3956 | @code\r | |
| 3957 | UINT64 Msr;\r | |
| 3958 | \r | |
| 3959 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);\r | |
| 3960 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);\r | |
| 3961 | @endcode\r | |
| c2aa191b | 3962 | @note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM.\r |
| bd946618 MK |
3963 | **/\r |
| 3964 | #define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A\r | |
| 3965 | \r | |
| 3966 | \r | |
| 3967 | /**\r | |
| 3968 | Package. Uncore C-box 0 perfmon counter MSR.\r | |
| 3969 | \r | |
| 3970 | @param ECX MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)\r | |
| 3971 | @param EAX Lower 32-bits of MSR value.\r | |
| 3972 | @param EDX Upper 32-bits of MSR value.\r | |
| 3973 | \r | |
| 3974 | <b>Example usage</b>\r | |
| 3975 | @code\r | |
| 3976 | UINT64 Msr;\r | |
| 3977 | \r | |
| 3978 | Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);\r | |
| 3979 | AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);\r | |
| 3980 | @endcode\r | |
| c2aa191b | 3981 | @note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM.\r |
| bd946618 MK |
3982 | **/\r |
| 3983 | #define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B\r | |
| 3984 | \r | |
| 3985 | \r | |
| 3986 | /**\r | |
| 3987 | Package. Uncore C-box 4 perfmon local box control MSR.\r | |
| 3988 | \r | |
| 3989 | @param ECX MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)\r | |
| 3990 | @param EAX Lower 32-bits of MSR value.\r | |
| 3991 | @param EDX Upper 32-bits of MSR value.\r | |
| 3992 | \r | |
| 3993 | <b>Example usage</b>\r | |
| 3994 | @code\r | |
| 3995 | UINT64 Msr;\r | |
| 3996 | \r | |
| 3997 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);\r | |
| 3998 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);\r | |
| 3999 | @endcode\r | |
| c2aa191b | 4000 | @note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
4001 | **/\r |
| 4002 | #define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20\r | |
| 4003 | \r | |
| 4004 | \r | |
| 4005 | /**\r | |
| 4006 | Package. Uncore C-box 4 perfmon local box status MSR.\r | |
| 4007 | \r | |
| 4008 | @param ECX MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)\r | |
| 4009 | @param EAX Lower 32-bits of MSR value.\r | |
| 4010 | @param EDX Upper 32-bits of MSR value.\r | |
| 4011 | \r | |
| 4012 | <b>Example usage</b>\r | |
| 4013 | @code\r | |
| 4014 | UINT64 Msr;\r | |
| 4015 | \r | |
| 4016 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);\r | |
| 4017 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);\r | |
| 4018 | @endcode\r | |
| c2aa191b | 4019 | @note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
4020 | **/\r |
| 4021 | #define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21\r | |
| 4022 | \r | |
| 4023 | \r | |
| 4024 | /**\r | |
| 4025 | Package. Uncore C-box 4 perfmon local box overflow control MSR.\r | |
| 4026 | \r | |
| 4027 | @param ECX MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)\r | |
| 4028 | @param EAX Lower 32-bits of MSR value.\r | |
| 4029 | @param EDX Upper 32-bits of MSR value.\r | |
| 4030 | \r | |
| 4031 | <b>Example usage</b>\r | |
| 4032 | @code\r | |
| 4033 | UINT64 Msr;\r | |
| 4034 | \r | |
| 4035 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);\r | |
| 4036 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);\r | |
| 4037 | @endcode\r | |
| c2aa191b | 4038 | @note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
4039 | **/\r |
| 4040 | #define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22\r | |
| 4041 | \r | |
| 4042 | \r | |
| 4043 | /**\r | |
| 4044 | Package. Uncore C-box 4 perfmon event select MSR.\r | |
| 4045 | \r | |
| 4046 | @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)\r | |
| 4047 | @param EAX Lower 32-bits of MSR value.\r | |
| 4048 | @param EDX Upper 32-bits of MSR value.\r | |
| 4049 | \r | |
| 4050 | <b>Example usage</b>\r | |
| 4051 | @code\r | |
| 4052 | UINT64 Msr;\r | |
| 4053 | \r | |
| 4054 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);\r | |
| 4055 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);\r | |
| 4056 | @endcode\r | |
| c2aa191b | 4057 | @note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
4058 | **/\r |
| 4059 | #define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30\r | |
| 4060 | \r | |
| 4061 | \r | |
| 4062 | /**\r | |
| 4063 | Package. Uncore C-box 4 perfmon counter MSR.\r | |
| 4064 | \r | |
| 4065 | @param ECX MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)\r | |
| 4066 | @param EAX Lower 32-bits of MSR value.\r | |
| 4067 | @param EDX Upper 32-bits of MSR value.\r | |
| 4068 | \r | |
| 4069 | <b>Example usage</b>\r | |
| 4070 | @code\r | |
| 4071 | UINT64 Msr;\r | |
| 4072 | \r | |
| 4073 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);\r | |
| 4074 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);\r | |
| 4075 | @endcode\r | |
| c2aa191b | 4076 | @note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r |
| bd946618 MK |
4077 | **/\r |
| 4078 | #define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31\r | |
| 4079 | \r | |
| 4080 | \r | |
| 4081 | /**\r | |
| 4082 | Package. Uncore C-box 4 perfmon event select MSR.\r | |
| 4083 | \r | |
| 4084 | @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)\r | |
| 4085 | @param EAX Lower 32-bits of MSR value.\r | |
| 4086 | @param EDX Upper 32-bits of MSR value.\r | |
| 4087 | \r | |
| 4088 | <b>Example usage</b>\r | |
| 4089 | @code\r | |
| 4090 | UINT64 Msr;\r | |
| 4091 | \r | |
| 4092 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);\r | |
| 4093 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);\r | |
| 4094 | @endcode\r | |
| c2aa191b | 4095 | @note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
4096 | **/\r |
| 4097 | #define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32\r | |
| 4098 | \r | |
| 4099 | \r | |
| 4100 | /**\r | |
| 4101 | Package. Uncore C-box 4 perfmon counter MSR.\r | |
| 4102 | \r | |
| 4103 | @param ECX MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)\r | |
| 4104 | @param EAX Lower 32-bits of MSR value.\r | |
| 4105 | @param EDX Upper 32-bits of MSR value.\r | |
| 4106 | \r | |
| 4107 | <b>Example usage</b>\r | |
| 4108 | @code\r | |
| 4109 | UINT64 Msr;\r | |
| 4110 | \r | |
| 4111 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);\r | |
| 4112 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);\r | |
| 4113 | @endcode\r | |
| c2aa191b | 4114 | @note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r |
| bd946618 MK |
4115 | **/\r |
| 4116 | #define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33\r | |
| 4117 | \r | |
| 4118 | \r | |
| 4119 | /**\r | |
| 4120 | Package. Uncore C-box 4 perfmon event select MSR.\r | |
| 4121 | \r | |
| 4122 | @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)\r | |
| 4123 | @param EAX Lower 32-bits of MSR value.\r | |
| 4124 | @param EDX Upper 32-bits of MSR value.\r | |
| 4125 | \r | |
| 4126 | <b>Example usage</b>\r | |
| 4127 | @code\r | |
| 4128 | UINT64 Msr;\r | |
| 4129 | \r | |
| 4130 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);\r | |
| 4131 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);\r | |
| 4132 | @endcode\r | |
| c2aa191b | 4133 | @note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
4134 | **/\r |
| 4135 | #define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34\r | |
| 4136 | \r | |
| 4137 | \r | |
| 4138 | /**\r | |
| 4139 | Package. Uncore C-box 4 perfmon counter MSR.\r | |
| 4140 | \r | |
| 4141 | @param ECX MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)\r | |
| 4142 | @param EAX Lower 32-bits of MSR value.\r | |
| 4143 | @param EDX Upper 32-bits of MSR value.\r | |
| 4144 | \r | |
| 4145 | <b>Example usage</b>\r | |
| 4146 | @code\r | |
| 4147 | UINT64 Msr;\r | |
| 4148 | \r | |
| 4149 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);\r | |
| 4150 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);\r | |
| 4151 | @endcode\r | |
| c2aa191b | 4152 | @note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r |
| bd946618 MK |
4153 | **/\r |
| 4154 | #define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35\r | |
| 4155 | \r | |
| 4156 | \r | |
| 4157 | /**\r | |
| 4158 | Package. Uncore C-box 4 perfmon event select MSR.\r | |
| 4159 | \r | |
| 4160 | @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)\r | |
| 4161 | @param EAX Lower 32-bits of MSR value.\r | |
| 4162 | @param EDX Upper 32-bits of MSR value.\r | |
| 4163 | \r | |
| 4164 | <b>Example usage</b>\r | |
| 4165 | @code\r | |
| 4166 | UINT64 Msr;\r | |
| 4167 | \r | |
| 4168 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);\r | |
| 4169 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);\r | |
| 4170 | @endcode\r | |
| c2aa191b | 4171 | @note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
4172 | **/\r |
| 4173 | #define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36\r | |
| 4174 | \r | |
| 4175 | \r | |
| 4176 | /**\r | |
| 4177 | Package. Uncore C-box 4 perfmon counter MSR.\r | |
| 4178 | \r | |
| 4179 | @param ECX MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)\r | |
| 4180 | @param EAX Lower 32-bits of MSR value.\r | |
| 4181 | @param EDX Upper 32-bits of MSR value.\r | |
| 4182 | \r | |
| 4183 | <b>Example usage</b>\r | |
| 4184 | @code\r | |
| 4185 | UINT64 Msr;\r | |
| 4186 | \r | |
| 4187 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);\r | |
| 4188 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);\r | |
| 4189 | @endcode\r | |
| c2aa191b | 4190 | @note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r |
| bd946618 MK |
4191 | **/\r |
| 4192 | #define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37\r | |
| 4193 | \r | |
| 4194 | \r | |
| 4195 | /**\r | |
| 4196 | Package. Uncore C-box 4 perfmon event select MSR.\r | |
| 4197 | \r | |
| 4198 | @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)\r | |
| 4199 | @param EAX Lower 32-bits of MSR value.\r | |
| 4200 | @param EDX Upper 32-bits of MSR value.\r | |
| 4201 | \r | |
| 4202 | <b>Example usage</b>\r | |
| 4203 | @code\r | |
| 4204 | UINT64 Msr;\r | |
| 4205 | \r | |
| 4206 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);\r | |
| 4207 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);\r | |
| 4208 | @endcode\r | |
| c2aa191b | 4209 | @note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM.\r |
| bd946618 MK |
4210 | **/\r |
| 4211 | #define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38\r | |
| 4212 | \r | |
| 4213 | \r | |
| 4214 | /**\r | |
| 4215 | Package. Uncore C-box 4 perfmon counter MSR.\r | |
| 4216 | \r | |
| 4217 | @param ECX MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)\r | |
| 4218 | @param EAX Lower 32-bits of MSR value.\r | |
| 4219 | @param EDX Upper 32-bits of MSR value.\r | |
| 4220 | \r | |
| 4221 | <b>Example usage</b>\r | |
| 4222 | @code\r | |
| 4223 | UINT64 Msr;\r | |
| 4224 | \r | |
| 4225 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);\r | |
| 4226 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);\r | |
| 4227 | @endcode\r | |
| c2aa191b | 4228 | @note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM.\r |
| bd946618 MK |
4229 | **/\r |
| 4230 | #define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39\r | |
| 4231 | \r | |
| 4232 | \r | |
| 4233 | /**\r | |
| 4234 | Package. Uncore C-box 4 perfmon event select MSR.\r | |
| 4235 | \r | |
| 4236 | @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)\r | |
| 4237 | @param EAX Lower 32-bits of MSR value.\r | |
| 4238 | @param EDX Upper 32-bits of MSR value.\r | |
| 4239 | \r | |
| 4240 | <b>Example usage</b>\r | |
| 4241 | @code\r | |
| 4242 | UINT64 Msr;\r | |
| 4243 | \r | |
| 4244 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);\r | |
| 4245 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);\r | |
| 4246 | @endcode\r | |
| c2aa191b | 4247 | @note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM.\r |
| bd946618 MK |
4248 | **/\r |
| 4249 | #define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A\r | |
| 4250 | \r | |
| 4251 | \r | |
| 4252 | /**\r | |
| 4253 | Package. Uncore C-box 4 perfmon counter MSR.\r | |
| 4254 | \r | |
| 4255 | @param ECX MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)\r | |
| 4256 | @param EAX Lower 32-bits of MSR value.\r | |
| 4257 | @param EDX Upper 32-bits of MSR value.\r | |
| 4258 | \r | |
| 4259 | <b>Example usage</b>\r | |
| 4260 | @code\r | |
| 4261 | UINT64 Msr;\r | |
| 4262 | \r | |
| 4263 | Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);\r | |
| 4264 | AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);\r | |
| 4265 | @endcode\r | |
| c2aa191b | 4266 | @note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM.\r |
| bd946618 MK |
4267 | **/\r |
| 4268 | #define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B\r | |
| 4269 | \r | |
| 4270 | \r | |
| 4271 | /**\r | |
| 4272 | Package. Uncore C-box 2 perfmon local box control MSR.\r | |
| 4273 | \r | |
| 4274 | @param ECX MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)\r | |
| 4275 | @param EAX Lower 32-bits of MSR value.\r | |
| 4276 | @param EDX Upper 32-bits of MSR value.\r | |
| 4277 | \r | |
| 4278 | <b>Example usage</b>\r | |
| 4279 | @code\r | |
| 4280 | UINT64 Msr;\r | |
| 4281 | \r | |
| 4282 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);\r | |
| 4283 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);\r | |
| 4284 | @endcode\r | |
| c2aa191b | 4285 | @note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
4286 | **/\r |
| 4287 | #define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40\r | |
| 4288 | \r | |
| 4289 | \r | |
| 4290 | /**\r | |
| 4291 | Package. Uncore C-box 2 perfmon local box status MSR.\r | |
| 4292 | \r | |
| 4293 | @param ECX MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)\r | |
| 4294 | @param EAX Lower 32-bits of MSR value.\r | |
| 4295 | @param EDX Upper 32-bits of MSR value.\r | |
| 4296 | \r | |
| 4297 | <b>Example usage</b>\r | |
| 4298 | @code\r | |
| 4299 | UINT64 Msr;\r | |
| 4300 | \r | |
| 4301 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);\r | |
| 4302 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);\r | |
| 4303 | @endcode\r | |
| c2aa191b | 4304 | @note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
4305 | **/\r |
| 4306 | #define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41\r | |
| 4307 | \r | |
| 4308 | \r | |
| 4309 | /**\r | |
| 4310 | Package. Uncore C-box 2 perfmon local box overflow control MSR.\r | |
| 4311 | \r | |
| 4312 | @param ECX MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)\r | |
| 4313 | @param EAX Lower 32-bits of MSR value.\r | |
| 4314 | @param EDX Upper 32-bits of MSR value.\r | |
| 4315 | \r | |
| 4316 | <b>Example usage</b>\r | |
| 4317 | @code\r | |
| 4318 | UINT64 Msr;\r | |
| 4319 | \r | |
| 4320 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);\r | |
| 4321 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);\r | |
| 4322 | @endcode\r | |
| c2aa191b | 4323 | @note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
4324 | **/\r |
| 4325 | #define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42\r | |
| 4326 | \r | |
| 4327 | \r | |
| 4328 | /**\r | |
| 4329 | Package. Uncore C-box 2 perfmon event select MSR.\r | |
| 4330 | \r | |
| 4331 | @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)\r | |
| 4332 | @param EAX Lower 32-bits of MSR value.\r | |
| 4333 | @param EDX Upper 32-bits of MSR value.\r | |
| 4334 | \r | |
| 4335 | <b>Example usage</b>\r | |
| 4336 | @code\r | |
| 4337 | UINT64 Msr;\r | |
| 4338 | \r | |
| 4339 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);\r | |
| 4340 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);\r | |
| 4341 | @endcode\r | |
| c2aa191b | 4342 | @note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
4343 | **/\r |
| 4344 | #define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50\r | |
| 4345 | \r | |
| 4346 | \r | |
| 4347 | /**\r | |
| 4348 | Package. Uncore C-box 2 perfmon counter MSR.\r | |
| 4349 | \r | |
| 4350 | @param ECX MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)\r | |
| 4351 | @param EAX Lower 32-bits of MSR value.\r | |
| 4352 | @param EDX Upper 32-bits of MSR value.\r | |
| 4353 | \r | |
| 4354 | <b>Example usage</b>\r | |
| 4355 | @code\r | |
| 4356 | UINT64 Msr;\r | |
| 4357 | \r | |
| 4358 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);\r | |
| 4359 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);\r | |
| 4360 | @endcode\r | |
| c2aa191b | 4361 | @note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r |
| bd946618 MK |
4362 | **/\r |
| 4363 | #define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51\r | |
| 4364 | \r | |
| 4365 | \r | |
| 4366 | /**\r | |
| 4367 | Package. Uncore C-box 2 perfmon event select MSR.\r | |
| 4368 | \r | |
| 4369 | @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)\r | |
| 4370 | @param EAX Lower 32-bits of MSR value.\r | |
| 4371 | @param EDX Upper 32-bits of MSR value.\r | |
| 4372 | \r | |
| 4373 | <b>Example usage</b>\r | |
| 4374 | @code\r | |
| 4375 | UINT64 Msr;\r | |
| 4376 | \r | |
| 4377 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);\r | |
| 4378 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);\r | |
| 4379 | @endcode\r | |
| c2aa191b | 4380 | @note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
4381 | **/\r |
| 4382 | #define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52\r | |
| 4383 | \r | |
| 4384 | \r | |
| 4385 | /**\r | |
| 4386 | Package. Uncore C-box 2 perfmon counter MSR.\r | |
| 4387 | \r | |
| 4388 | @param ECX MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)\r | |
| 4389 | @param EAX Lower 32-bits of MSR value.\r | |
| 4390 | @param EDX Upper 32-bits of MSR value.\r | |
| 4391 | \r | |
| 4392 | <b>Example usage</b>\r | |
| 4393 | @code\r | |
| 4394 | UINT64 Msr;\r | |
| 4395 | \r | |
| 4396 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);\r | |
| 4397 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);\r | |
| 4398 | @endcode\r | |
| c2aa191b | 4399 | @note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r |
| bd946618 MK |
4400 | **/\r |
| 4401 | #define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53\r | |
| 4402 | \r | |
| 4403 | \r | |
| 4404 | /**\r | |
| 4405 | Package. Uncore C-box 2 perfmon event select MSR.\r | |
| 4406 | \r | |
| 4407 | @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)\r | |
| 4408 | @param EAX Lower 32-bits of MSR value.\r | |
| 4409 | @param EDX Upper 32-bits of MSR value.\r | |
| 4410 | \r | |
| 4411 | <b>Example usage</b>\r | |
| 4412 | @code\r | |
| 4413 | UINT64 Msr;\r | |
| 4414 | \r | |
| 4415 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);\r | |
| 4416 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);\r | |
| 4417 | @endcode\r | |
| c2aa191b | 4418 | @note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
4419 | **/\r |
| 4420 | #define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54\r | |
| 4421 | \r | |
| 4422 | \r | |
| 4423 | /**\r | |
| 4424 | Package. Uncore C-box 2 perfmon counter MSR.\r | |
| 4425 | \r | |
| 4426 | @param ECX MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)\r | |
| 4427 | @param EAX Lower 32-bits of MSR value.\r | |
| 4428 | @param EDX Upper 32-bits of MSR value.\r | |
| 4429 | \r | |
| 4430 | <b>Example usage</b>\r | |
| 4431 | @code\r | |
| 4432 | UINT64 Msr;\r | |
| 4433 | \r | |
| 4434 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);\r | |
| 4435 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);\r | |
| 4436 | @endcode\r | |
| c2aa191b | 4437 | @note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r |
| bd946618 MK |
4438 | **/\r |
| 4439 | #define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55\r | |
| 4440 | \r | |
| 4441 | \r | |
| 4442 | /**\r | |
| 4443 | Package. Uncore C-box 2 perfmon event select MSR.\r | |
| 4444 | \r | |
| 4445 | @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)\r | |
| 4446 | @param EAX Lower 32-bits of MSR value.\r | |
| 4447 | @param EDX Upper 32-bits of MSR value.\r | |
| 4448 | \r | |
| 4449 | <b>Example usage</b>\r | |
| 4450 | @code\r | |
| 4451 | UINT64 Msr;\r | |
| 4452 | \r | |
| 4453 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);\r | |
| 4454 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);\r | |
| 4455 | @endcode\r | |
| c2aa191b | 4456 | @note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
4457 | **/\r |
| 4458 | #define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56\r | |
| 4459 | \r | |
| 4460 | \r | |
| 4461 | /**\r | |
| 4462 | Package. Uncore C-box 2 perfmon counter MSR.\r | |
| 4463 | \r | |
| 4464 | @param ECX MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)\r | |
| 4465 | @param EAX Lower 32-bits of MSR value.\r | |
| 4466 | @param EDX Upper 32-bits of MSR value.\r | |
| 4467 | \r | |
| 4468 | <b>Example usage</b>\r | |
| 4469 | @code\r | |
| 4470 | UINT64 Msr;\r | |
| 4471 | \r | |
| 4472 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);\r | |
| 4473 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);\r | |
| 4474 | @endcode\r | |
| c2aa191b | 4475 | @note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r |
| bd946618 MK |
4476 | **/\r |
| 4477 | #define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57\r | |
| 4478 | \r | |
| 4479 | \r | |
| 4480 | /**\r | |
| 4481 | Package. Uncore C-box 2 perfmon event select MSR.\r | |
| 4482 | \r | |
| 4483 | @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)\r | |
| 4484 | @param EAX Lower 32-bits of MSR value.\r | |
| 4485 | @param EDX Upper 32-bits of MSR value.\r | |
| 4486 | \r | |
| 4487 | <b>Example usage</b>\r | |
| 4488 | @code\r | |
| 4489 | UINT64 Msr;\r | |
| 4490 | \r | |
| 4491 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);\r | |
| 4492 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);\r | |
| 4493 | @endcode\r | |
| c2aa191b | 4494 | @note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM.\r |
| bd946618 MK |
4495 | **/\r |
| 4496 | #define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58\r | |
| 4497 | \r | |
| 4498 | \r | |
| 4499 | /**\r | |
| 4500 | Package. Uncore C-box 2 perfmon counter MSR.\r | |
| 4501 | \r | |
| 4502 | @param ECX MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)\r | |
| 4503 | @param EAX Lower 32-bits of MSR value.\r | |
| 4504 | @param EDX Upper 32-bits of MSR value.\r | |
| 4505 | \r | |
| 4506 | <b>Example usage</b>\r | |
| 4507 | @code\r | |
| 4508 | UINT64 Msr;\r | |
| 4509 | \r | |
| 4510 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);\r | |
| 4511 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);\r | |
| 4512 | @endcode\r | |
| c2aa191b | 4513 | @note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM.\r |
| bd946618 MK |
4514 | **/\r |
| 4515 | #define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59\r | |
| 4516 | \r | |
| 4517 | \r | |
| 4518 | /**\r | |
| 4519 | Package. Uncore C-box 2 perfmon event select MSR.\r | |
| 4520 | \r | |
| 4521 | @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)\r | |
| 4522 | @param EAX Lower 32-bits of MSR value.\r | |
| 4523 | @param EDX Upper 32-bits of MSR value.\r | |
| 4524 | \r | |
| 4525 | <b>Example usage</b>\r | |
| 4526 | @code\r | |
| 4527 | UINT64 Msr;\r | |
| 4528 | \r | |
| 4529 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);\r | |
| 4530 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);\r | |
| 4531 | @endcode\r | |
| c2aa191b | 4532 | @note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM.\r |
| bd946618 MK |
4533 | **/\r |
| 4534 | #define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A\r | |
| 4535 | \r | |
| 4536 | \r | |
| 4537 | /**\r | |
| 4538 | Package. Uncore C-box 2 perfmon counter MSR.\r | |
| 4539 | \r | |
| 4540 | @param ECX MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)\r | |
| 4541 | @param EAX Lower 32-bits of MSR value.\r | |
| 4542 | @param EDX Upper 32-bits of MSR value.\r | |
| 4543 | \r | |
| 4544 | <b>Example usage</b>\r | |
| 4545 | @code\r | |
| 4546 | UINT64 Msr;\r | |
| 4547 | \r | |
| 4548 | Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);\r | |
| 4549 | AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);\r | |
| 4550 | @endcode\r | |
| c2aa191b | 4551 | @note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM.\r |
| bd946618 MK |
4552 | **/\r |
| 4553 | #define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B\r | |
| 4554 | \r | |
| 4555 | \r | |
| 4556 | /**\r | |
| 4557 | Package. Uncore C-box 6 perfmon local box control MSR.\r | |
| 4558 | \r | |
| 4559 | @param ECX MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)\r | |
| 4560 | @param EAX Lower 32-bits of MSR value.\r | |
| 4561 | @param EDX Upper 32-bits of MSR value.\r | |
| 4562 | \r | |
| 4563 | <b>Example usage</b>\r | |
| 4564 | @code\r | |
| 4565 | UINT64 Msr;\r | |
| 4566 | \r | |
| 4567 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);\r | |
| 4568 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);\r | |
| 4569 | @endcode\r | |
| c2aa191b | 4570 | @note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
4571 | **/\r |
| 4572 | #define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60\r | |
| 4573 | \r | |
| 4574 | \r | |
| 4575 | /**\r | |
| 4576 | Package. Uncore C-box 6 perfmon local box status MSR.\r | |
| 4577 | \r | |
| 4578 | @param ECX MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)\r | |
| 4579 | @param EAX Lower 32-bits of MSR value.\r | |
| 4580 | @param EDX Upper 32-bits of MSR value.\r | |
| 4581 | \r | |
| 4582 | <b>Example usage</b>\r | |
| 4583 | @code\r | |
| 4584 | UINT64 Msr;\r | |
| 4585 | \r | |
| 4586 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);\r | |
| 4587 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);\r | |
| 4588 | @endcode\r | |
| c2aa191b | 4589 | @note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
4590 | **/\r |
| 4591 | #define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61\r | |
| 4592 | \r | |
| 4593 | \r | |
| 4594 | /**\r | |
| 4595 | Package. Uncore C-box 6 perfmon local box overflow control MSR.\r | |
| 4596 | \r | |
| 4597 | @param ECX MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)\r | |
| 4598 | @param EAX Lower 32-bits of MSR value.\r | |
| 4599 | @param EDX Upper 32-bits of MSR value.\r | |
| 4600 | \r | |
| 4601 | <b>Example usage</b>\r | |
| 4602 | @code\r | |
| 4603 | UINT64 Msr;\r | |
| 4604 | \r | |
| 4605 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);\r | |
| 4606 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);\r | |
| 4607 | @endcode\r | |
| c2aa191b | 4608 | @note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
4609 | **/\r |
| 4610 | #define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62\r | |
| 4611 | \r | |
| 4612 | \r | |
| 4613 | /**\r | |
| 4614 | Package. Uncore C-box 6 perfmon event select MSR.\r | |
| 4615 | \r | |
| 4616 | @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)\r | |
| 4617 | @param EAX Lower 32-bits of MSR value.\r | |
| 4618 | @param EDX Upper 32-bits of MSR value.\r | |
| 4619 | \r | |
| 4620 | <b>Example usage</b>\r | |
| 4621 | @code\r | |
| 4622 | UINT64 Msr;\r | |
| 4623 | \r | |
| 4624 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);\r | |
| 4625 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);\r | |
| 4626 | @endcode\r | |
| c2aa191b | 4627 | @note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
4628 | **/\r |
| 4629 | #define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70\r | |
| 4630 | \r | |
| 4631 | \r | |
| 4632 | /**\r | |
| 4633 | Package. Uncore C-box 6 perfmon counter MSR.\r | |
| 4634 | \r | |
| 4635 | @param ECX MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)\r | |
| 4636 | @param EAX Lower 32-bits of MSR value.\r | |
| 4637 | @param EDX Upper 32-bits of MSR value.\r | |
| 4638 | \r | |
| 4639 | <b>Example usage</b>\r | |
| 4640 | @code\r | |
| 4641 | UINT64 Msr;\r | |
| 4642 | \r | |
| 4643 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);\r | |
| 4644 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);\r | |
| 4645 | @endcode\r | |
| c2aa191b | 4646 | @note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r |
| bd946618 MK |
4647 | **/\r |
| 4648 | #define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71\r | |
| 4649 | \r | |
| 4650 | \r | |
| 4651 | /**\r | |
| 4652 | Package. Uncore C-box 6 perfmon event select MSR.\r | |
| 4653 | \r | |
| 4654 | @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)\r | |
| 4655 | @param EAX Lower 32-bits of MSR value.\r | |
| 4656 | @param EDX Upper 32-bits of MSR value.\r | |
| 4657 | \r | |
| 4658 | <b>Example usage</b>\r | |
| 4659 | @code\r | |
| 4660 | UINT64 Msr;\r | |
| 4661 | \r | |
| 4662 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);\r | |
| 4663 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);\r | |
| 4664 | @endcode\r | |
| c2aa191b | 4665 | @note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
4666 | **/\r |
| 4667 | #define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72\r | |
| 4668 | \r | |
| 4669 | \r | |
| 4670 | /**\r | |
| 4671 | Package. Uncore C-box 6 perfmon counter MSR.\r | |
| 4672 | \r | |
| 4673 | @param ECX MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)\r | |
| 4674 | @param EAX Lower 32-bits of MSR value.\r | |
| 4675 | @param EDX Upper 32-bits of MSR value.\r | |
| 4676 | \r | |
| 4677 | <b>Example usage</b>\r | |
| 4678 | @code\r | |
| 4679 | UINT64 Msr;\r | |
| 4680 | \r | |
| 4681 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);\r | |
| 4682 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);\r | |
| 4683 | @endcode\r | |
| c2aa191b | 4684 | @note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r |
| bd946618 MK |
4685 | **/\r |
| 4686 | #define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73\r | |
| 4687 | \r | |
| 4688 | \r | |
| 4689 | /**\r | |
| 4690 | Package. Uncore C-box 6 perfmon event select MSR.\r | |
| 4691 | \r | |
| 4692 | @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)\r | |
| 4693 | @param EAX Lower 32-bits of MSR value.\r | |
| 4694 | @param EDX Upper 32-bits of MSR value.\r | |
| 4695 | \r | |
| 4696 | <b>Example usage</b>\r | |
| 4697 | @code\r | |
| 4698 | UINT64 Msr;\r | |
| 4699 | \r | |
| 4700 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);\r | |
| 4701 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);\r | |
| 4702 | @endcode\r | |
| c2aa191b | 4703 | @note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
4704 | **/\r |
| 4705 | #define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74\r | |
| 4706 | \r | |
| 4707 | \r | |
| 4708 | /**\r | |
| 4709 | Package. Uncore C-box 6 perfmon counter MSR.\r | |
| 4710 | \r | |
| 4711 | @param ECX MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)\r | |
| 4712 | @param EAX Lower 32-bits of MSR value.\r | |
| 4713 | @param EDX Upper 32-bits of MSR value.\r | |
| 4714 | \r | |
| 4715 | <b>Example usage</b>\r | |
| 4716 | @code\r | |
| 4717 | UINT64 Msr;\r | |
| 4718 | \r | |
| 4719 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);\r | |
| 4720 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);\r | |
| 4721 | @endcode\r | |
| c2aa191b | 4722 | @note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r |
| bd946618 MK |
4723 | **/\r |
| 4724 | #define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75\r | |
| 4725 | \r | |
| 4726 | \r | |
| 4727 | /**\r | |
| 4728 | Package. Uncore C-box 6 perfmon event select MSR.\r | |
| 4729 | \r | |
| 4730 | @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)\r | |
| 4731 | @param EAX Lower 32-bits of MSR value.\r | |
| 4732 | @param EDX Upper 32-bits of MSR value.\r | |
| 4733 | \r | |
| 4734 | <b>Example usage</b>\r | |
| 4735 | @code\r | |
| 4736 | UINT64 Msr;\r | |
| 4737 | \r | |
| 4738 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);\r | |
| 4739 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);\r | |
| 4740 | @endcode\r | |
| c2aa191b | 4741 | @note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
4742 | **/\r |
| 4743 | #define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76\r | |
| 4744 | \r | |
| 4745 | \r | |
| 4746 | /**\r | |
| 4747 | Package. Uncore C-box 6 perfmon counter MSR.\r | |
| 4748 | \r | |
| 4749 | @param ECX MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)\r | |
| 4750 | @param EAX Lower 32-bits of MSR value.\r | |
| 4751 | @param EDX Upper 32-bits of MSR value.\r | |
| 4752 | \r | |
| 4753 | <b>Example usage</b>\r | |
| 4754 | @code\r | |
| 4755 | UINT64 Msr;\r | |
| 4756 | \r | |
| 4757 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);\r | |
| 4758 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);\r | |
| 4759 | @endcode\r | |
| c2aa191b | 4760 | @note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r |
| bd946618 MK |
4761 | **/\r |
| 4762 | #define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77\r | |
| 4763 | \r | |
| 4764 | \r | |
| 4765 | /**\r | |
| 4766 | Package. Uncore C-box 6 perfmon event select MSR.\r | |
| 4767 | \r | |
| 4768 | @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)\r | |
| 4769 | @param EAX Lower 32-bits of MSR value.\r | |
| 4770 | @param EDX Upper 32-bits of MSR value.\r | |
| 4771 | \r | |
| 4772 | <b>Example usage</b>\r | |
| 4773 | @code\r | |
| 4774 | UINT64 Msr;\r | |
| 4775 | \r | |
| 4776 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);\r | |
| 4777 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);\r | |
| 4778 | @endcode\r | |
| c2aa191b | 4779 | @note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM.\r |
| bd946618 MK |
4780 | **/\r |
| 4781 | #define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78\r | |
| 4782 | \r | |
| 4783 | \r | |
| 4784 | /**\r | |
| 4785 | Package. Uncore C-box 6 perfmon counter MSR.\r | |
| 4786 | \r | |
| 4787 | @param ECX MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)\r | |
| 4788 | @param EAX Lower 32-bits of MSR value.\r | |
| 4789 | @param EDX Upper 32-bits of MSR value.\r | |
| 4790 | \r | |
| 4791 | <b>Example usage</b>\r | |
| 4792 | @code\r | |
| 4793 | UINT64 Msr;\r | |
| 4794 | \r | |
| 4795 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);\r | |
| 4796 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);\r | |
| 4797 | @endcode\r | |
| c2aa191b | 4798 | @note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM.\r |
| bd946618 MK |
4799 | **/\r |
| 4800 | #define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79\r | |
| 4801 | \r | |
| 4802 | \r | |
| 4803 | /**\r | |
| 4804 | Package. Uncore C-box 6 perfmon event select MSR.\r | |
| 4805 | \r | |
| 4806 | @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)\r | |
| 4807 | @param EAX Lower 32-bits of MSR value.\r | |
| 4808 | @param EDX Upper 32-bits of MSR value.\r | |
| 4809 | \r | |
| 4810 | <b>Example usage</b>\r | |
| 4811 | @code\r | |
| 4812 | UINT64 Msr;\r | |
| 4813 | \r | |
| 4814 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);\r | |
| 4815 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);\r | |
| 4816 | @endcode\r | |
| c2aa191b | 4817 | @note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM.\r |
| bd946618 MK |
4818 | **/\r |
| 4819 | #define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A\r | |
| 4820 | \r | |
| 4821 | \r | |
| 4822 | /**\r | |
| 4823 | Package. Uncore C-box 6 perfmon counter MSR.\r | |
| 4824 | \r | |
| 4825 | @param ECX MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)\r | |
| 4826 | @param EAX Lower 32-bits of MSR value.\r | |
| 4827 | @param EDX Upper 32-bits of MSR value.\r | |
| 4828 | \r | |
| 4829 | <b>Example usage</b>\r | |
| 4830 | @code\r | |
| 4831 | UINT64 Msr;\r | |
| 4832 | \r | |
| 4833 | Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);\r | |
| 4834 | AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);\r | |
| 4835 | @endcode\r | |
| c2aa191b | 4836 | @note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM.\r |
| bd946618 MK |
4837 | **/\r |
| 4838 | #define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B\r | |
| 4839 | \r | |
| 4840 | \r | |
| 4841 | /**\r | |
| 4842 | Package. Uncore C-box 1 perfmon local box control MSR.\r | |
| 4843 | \r | |
| 4844 | @param ECX MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)\r | |
| 4845 | @param EAX Lower 32-bits of MSR value.\r | |
| 4846 | @param EDX Upper 32-bits of MSR value.\r | |
| 4847 | \r | |
| 4848 | <b>Example usage</b>\r | |
| 4849 | @code\r | |
| 4850 | UINT64 Msr;\r | |
| 4851 | \r | |
| 4852 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);\r | |
| 4853 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);\r | |
| 4854 | @endcode\r | |
| c2aa191b | 4855 | @note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
4856 | **/\r |
| 4857 | #define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80\r | |
| 4858 | \r | |
| 4859 | \r | |
| 4860 | /**\r | |
| 4861 | Package. Uncore C-box 1 perfmon local box status MSR.\r | |
| 4862 | \r | |
| 4863 | @param ECX MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)\r | |
| 4864 | @param EAX Lower 32-bits of MSR value.\r | |
| 4865 | @param EDX Upper 32-bits of MSR value.\r | |
| 4866 | \r | |
| 4867 | <b>Example usage</b>\r | |
| 4868 | @code\r | |
| 4869 | UINT64 Msr;\r | |
| 4870 | \r | |
| 4871 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);\r | |
| 4872 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);\r | |
| 4873 | @endcode\r | |
| c2aa191b | 4874 | @note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
4875 | **/\r |
| 4876 | #define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81\r | |
| 4877 | \r | |
| 4878 | \r | |
| 4879 | /**\r | |
| 4880 | Package. Uncore C-box 1 perfmon local box overflow control MSR.\r | |
| 4881 | \r | |
| 4882 | @param ECX MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)\r | |
| 4883 | @param EAX Lower 32-bits of MSR value.\r | |
| 4884 | @param EDX Upper 32-bits of MSR value.\r | |
| 4885 | \r | |
| 4886 | <b>Example usage</b>\r | |
| 4887 | @code\r | |
| 4888 | UINT64 Msr;\r | |
| 4889 | \r | |
| 4890 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);\r | |
| 4891 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);\r | |
| 4892 | @endcode\r | |
| c2aa191b | 4893 | @note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
4894 | **/\r |
| 4895 | #define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82\r | |
| 4896 | \r | |
| 4897 | \r | |
| 4898 | /**\r | |
| 4899 | Package. Uncore C-box 1 perfmon event select MSR.\r | |
| 4900 | \r | |
| 4901 | @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)\r | |
| 4902 | @param EAX Lower 32-bits of MSR value.\r | |
| 4903 | @param EDX Upper 32-bits of MSR value.\r | |
| 4904 | \r | |
| 4905 | <b>Example usage</b>\r | |
| 4906 | @code\r | |
| 4907 | UINT64 Msr;\r | |
| 4908 | \r | |
| 4909 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);\r | |
| 4910 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);\r | |
| 4911 | @endcode\r | |
| c2aa191b | 4912 | @note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
4913 | **/\r |
| 4914 | #define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90\r | |
| 4915 | \r | |
| 4916 | \r | |
| 4917 | /**\r | |
| 4918 | Package. Uncore C-box 1 perfmon counter MSR.\r | |
| 4919 | \r | |
| 4920 | @param ECX MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)\r | |
| 4921 | @param EAX Lower 32-bits of MSR value.\r | |
| 4922 | @param EDX Upper 32-bits of MSR value.\r | |
| 4923 | \r | |
| 4924 | <b>Example usage</b>\r | |
| 4925 | @code\r | |
| 4926 | UINT64 Msr;\r | |
| 4927 | \r | |
| 4928 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);\r | |
| 4929 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);\r | |
| 4930 | @endcode\r | |
| c2aa191b | 4931 | @note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r |
| bd946618 MK |
4932 | **/\r |
| 4933 | #define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91\r | |
| 4934 | \r | |
| 4935 | \r | |
| 4936 | /**\r | |
| 4937 | Package. Uncore C-box 1 perfmon event select MSR.\r | |
| 4938 | \r | |
| 4939 | @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)\r | |
| 4940 | @param EAX Lower 32-bits of MSR value.\r | |
| 4941 | @param EDX Upper 32-bits of MSR value.\r | |
| 4942 | \r | |
| 4943 | <b>Example usage</b>\r | |
| 4944 | @code\r | |
| 4945 | UINT64 Msr;\r | |
| 4946 | \r | |
| 4947 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);\r | |
| 4948 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);\r | |
| 4949 | @endcode\r | |
| c2aa191b | 4950 | @note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
4951 | **/\r |
| 4952 | #define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92\r | |
| 4953 | \r | |
| 4954 | \r | |
| 4955 | /**\r | |
| 4956 | Package. Uncore C-box 1 perfmon counter MSR.\r | |
| 4957 | \r | |
| 4958 | @param ECX MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)\r | |
| 4959 | @param EAX Lower 32-bits of MSR value.\r | |
| 4960 | @param EDX Upper 32-bits of MSR value.\r | |
| 4961 | \r | |
| 4962 | <b>Example usage</b>\r | |
| 4963 | @code\r | |
| 4964 | UINT64 Msr;\r | |
| 4965 | \r | |
| 4966 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);\r | |
| 4967 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);\r | |
| 4968 | @endcode\r | |
| c2aa191b | 4969 | @note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r |
| bd946618 MK |
4970 | **/\r |
| 4971 | #define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93\r | |
| 4972 | \r | |
| 4973 | \r | |
| 4974 | /**\r | |
| 4975 | Package. Uncore C-box 1 perfmon event select MSR.\r | |
| 4976 | \r | |
| 4977 | @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)\r | |
| 4978 | @param EAX Lower 32-bits of MSR value.\r | |
| 4979 | @param EDX Upper 32-bits of MSR value.\r | |
| 4980 | \r | |
| 4981 | <b>Example usage</b>\r | |
| 4982 | @code\r | |
| 4983 | UINT64 Msr;\r | |
| 4984 | \r | |
| 4985 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);\r | |
| 4986 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);\r | |
| 4987 | @endcode\r | |
| c2aa191b | 4988 | @note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
4989 | **/\r |
| 4990 | #define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94\r | |
| 4991 | \r | |
| 4992 | \r | |
| 4993 | /**\r | |
| 4994 | Package. Uncore C-box 1 perfmon counter MSR.\r | |
| 4995 | \r | |
| 4996 | @param ECX MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)\r | |
| 4997 | @param EAX Lower 32-bits of MSR value.\r | |
| 4998 | @param EDX Upper 32-bits of MSR value.\r | |
| 4999 | \r | |
| 5000 | <b>Example usage</b>\r | |
| 5001 | @code\r | |
| 5002 | UINT64 Msr;\r | |
| 5003 | \r | |
| 5004 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);\r | |
| 5005 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);\r | |
| 5006 | @endcode\r | |
| c2aa191b | 5007 | @note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r |
| bd946618 MK |
5008 | **/\r |
| 5009 | #define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95\r | |
| 5010 | \r | |
| 5011 | \r | |
| 5012 | /**\r | |
| 5013 | Package. Uncore C-box 1 perfmon event select MSR.\r | |
| 5014 | \r | |
| 5015 | @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)\r | |
| 5016 | @param EAX Lower 32-bits of MSR value.\r | |
| 5017 | @param EDX Upper 32-bits of MSR value.\r | |
| 5018 | \r | |
| 5019 | <b>Example usage</b>\r | |
| 5020 | @code\r | |
| 5021 | UINT64 Msr;\r | |
| 5022 | \r | |
| 5023 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);\r | |
| 5024 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);\r | |
| 5025 | @endcode\r | |
| c2aa191b | 5026 | @note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
5027 | **/\r |
| 5028 | #define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96\r | |
| 5029 | \r | |
| 5030 | \r | |
| 5031 | /**\r | |
| 5032 | Package. Uncore C-box 1 perfmon counter MSR.\r | |
| 5033 | \r | |
| 5034 | @param ECX MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)\r | |
| 5035 | @param EAX Lower 32-bits of MSR value.\r | |
| 5036 | @param EDX Upper 32-bits of MSR value.\r | |
| 5037 | \r | |
| 5038 | <b>Example usage</b>\r | |
| 5039 | @code\r | |
| 5040 | UINT64 Msr;\r | |
| 5041 | \r | |
| 5042 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);\r | |
| 5043 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);\r | |
| 5044 | @endcode\r | |
| c2aa191b | 5045 | @note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r |
| bd946618 MK |
5046 | **/\r |
| 5047 | #define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97\r | |
| 5048 | \r | |
| 5049 | \r | |
| 5050 | /**\r | |
| 5051 | Package. Uncore C-box 1 perfmon event select MSR.\r | |
| 5052 | \r | |
| 5053 | @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)\r | |
| 5054 | @param EAX Lower 32-bits of MSR value.\r | |
| 5055 | @param EDX Upper 32-bits of MSR value.\r | |
| 5056 | \r | |
| 5057 | <b>Example usage</b>\r | |
| 5058 | @code\r | |
| 5059 | UINT64 Msr;\r | |
| 5060 | \r | |
| 5061 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);\r | |
| 5062 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);\r | |
| 5063 | @endcode\r | |
| c2aa191b | 5064 | @note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM.\r |
| bd946618 MK |
5065 | **/\r |
| 5066 | #define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98\r | |
| 5067 | \r | |
| 5068 | \r | |
| 5069 | /**\r | |
| 5070 | Package. Uncore C-box 1 perfmon counter MSR.\r | |
| 5071 | \r | |
| 5072 | @param ECX MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)\r | |
| 5073 | @param EAX Lower 32-bits of MSR value.\r | |
| 5074 | @param EDX Upper 32-bits of MSR value.\r | |
| 5075 | \r | |
| 5076 | <b>Example usage</b>\r | |
| 5077 | @code\r | |
| 5078 | UINT64 Msr;\r | |
| 5079 | \r | |
| 5080 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);\r | |
| 5081 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);\r | |
| 5082 | @endcode\r | |
| c2aa191b | 5083 | @note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM.\r |
| bd946618 MK |
5084 | **/\r |
| 5085 | #define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99\r | |
| 5086 | \r | |
| 5087 | \r | |
| 5088 | /**\r | |
| 5089 | Package. Uncore C-box 1 perfmon event select MSR.\r | |
| 5090 | \r | |
| 5091 | @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)\r | |
| 5092 | @param EAX Lower 32-bits of MSR value.\r | |
| 5093 | @param EDX Upper 32-bits of MSR value.\r | |
| 5094 | \r | |
| 5095 | <b>Example usage</b>\r | |
| 5096 | @code\r | |
| 5097 | UINT64 Msr;\r | |
| 5098 | \r | |
| 5099 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);\r | |
| 5100 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);\r | |
| 5101 | @endcode\r | |
| c2aa191b | 5102 | @note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM.\r |
| bd946618 MK |
5103 | **/\r |
| 5104 | #define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A\r | |
| 5105 | \r | |
| 5106 | \r | |
| 5107 | /**\r | |
| 5108 | Package. Uncore C-box 1 perfmon counter MSR.\r | |
| 5109 | \r | |
| 5110 | @param ECX MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)\r | |
| 5111 | @param EAX Lower 32-bits of MSR value.\r | |
| 5112 | @param EDX Upper 32-bits of MSR value.\r | |
| 5113 | \r | |
| 5114 | <b>Example usage</b>\r | |
| 5115 | @code\r | |
| 5116 | UINT64 Msr;\r | |
| 5117 | \r | |
| 5118 | Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);\r | |
| 5119 | AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);\r | |
| 5120 | @endcode\r | |
| c2aa191b | 5121 | @note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM.\r |
| bd946618 MK |
5122 | **/\r |
| 5123 | #define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B\r | |
| 5124 | \r | |
| 5125 | \r | |
| 5126 | /**\r | |
| 5127 | Package. Uncore C-box 5 perfmon local box control MSR.\r | |
| 5128 | \r | |
| 5129 | @param ECX MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)\r | |
| 5130 | @param EAX Lower 32-bits of MSR value.\r | |
| 5131 | @param EDX Upper 32-bits of MSR value.\r | |
| 5132 | \r | |
| 5133 | <b>Example usage</b>\r | |
| 5134 | @code\r | |
| 5135 | UINT64 Msr;\r | |
| 5136 | \r | |
| 5137 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);\r | |
| 5138 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);\r | |
| 5139 | @endcode\r | |
| c2aa191b | 5140 | @note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
5141 | **/\r |
| 5142 | #define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0\r | |
| 5143 | \r | |
| 5144 | \r | |
| 5145 | /**\r | |
| 5146 | Package. Uncore C-box 5 perfmon local box status MSR.\r | |
| 5147 | \r | |
| 5148 | @param ECX MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)\r | |
| 5149 | @param EAX Lower 32-bits of MSR value.\r | |
| 5150 | @param EDX Upper 32-bits of MSR value.\r | |
| 5151 | \r | |
| 5152 | <b>Example usage</b>\r | |
| 5153 | @code\r | |
| 5154 | UINT64 Msr;\r | |
| 5155 | \r | |
| 5156 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);\r | |
| 5157 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);\r | |
| 5158 | @endcode\r | |
| c2aa191b | 5159 | @note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
5160 | **/\r |
| 5161 | #define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1\r | |
| 5162 | \r | |
| 5163 | \r | |
| 5164 | /**\r | |
| 5165 | Package. Uncore C-box 5 perfmon local box overflow control MSR.\r | |
| 5166 | \r | |
| 5167 | @param ECX MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)\r | |
| 5168 | @param EAX Lower 32-bits of MSR value.\r | |
| 5169 | @param EDX Upper 32-bits of MSR value.\r | |
| 5170 | \r | |
| 5171 | <b>Example usage</b>\r | |
| 5172 | @code\r | |
| 5173 | UINT64 Msr;\r | |
| 5174 | \r | |
| 5175 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);\r | |
| 5176 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);\r | |
| 5177 | @endcode\r | |
| c2aa191b | 5178 | @note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
5179 | **/\r |
| 5180 | #define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2\r | |
| 5181 | \r | |
| 5182 | \r | |
| 5183 | /**\r | |
| 5184 | Package. Uncore C-box 5 perfmon event select MSR.\r | |
| 5185 | \r | |
| 5186 | @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)\r | |
| 5187 | @param EAX Lower 32-bits of MSR value.\r | |
| 5188 | @param EDX Upper 32-bits of MSR value.\r | |
| 5189 | \r | |
| 5190 | <b>Example usage</b>\r | |
| 5191 | @code\r | |
| 5192 | UINT64 Msr;\r | |
| 5193 | \r | |
| 5194 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);\r | |
| 5195 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);\r | |
| 5196 | @endcode\r | |
| c2aa191b | 5197 | @note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
5198 | **/\r |
| 5199 | #define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0\r | |
| 5200 | \r | |
| 5201 | \r | |
| 5202 | /**\r | |
| 5203 | Package. Uncore C-box 5 perfmon counter MSR.\r | |
| 5204 | \r | |
| 5205 | @param ECX MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)\r | |
| 5206 | @param EAX Lower 32-bits of MSR value.\r | |
| 5207 | @param EDX Upper 32-bits of MSR value.\r | |
| 5208 | \r | |
| 5209 | <b>Example usage</b>\r | |
| 5210 | @code\r | |
| 5211 | UINT64 Msr;\r | |
| 5212 | \r | |
| 5213 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);\r | |
| 5214 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);\r | |
| 5215 | @endcode\r | |
| c2aa191b | 5216 | @note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r |
| bd946618 MK |
5217 | **/\r |
| 5218 | #define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1\r | |
| 5219 | \r | |
| 5220 | \r | |
| 5221 | /**\r | |
| 5222 | Package. Uncore C-box 5 perfmon event select MSR.\r | |
| 5223 | \r | |
| 5224 | @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)\r | |
| 5225 | @param EAX Lower 32-bits of MSR value.\r | |
| 5226 | @param EDX Upper 32-bits of MSR value.\r | |
| 5227 | \r | |
| 5228 | <b>Example usage</b>\r | |
| 5229 | @code\r | |
| 5230 | UINT64 Msr;\r | |
| 5231 | \r | |
| 5232 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);\r | |
| 5233 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);\r | |
| 5234 | @endcode\r | |
| c2aa191b | 5235 | @note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
5236 | **/\r |
| 5237 | #define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2\r | |
| 5238 | \r | |
| 5239 | \r | |
| 5240 | /**\r | |
| 5241 | Package. Uncore C-box 5 perfmon counter MSR.\r | |
| 5242 | \r | |
| 5243 | @param ECX MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)\r | |
| 5244 | @param EAX Lower 32-bits of MSR value.\r | |
| 5245 | @param EDX Upper 32-bits of MSR value.\r | |
| 5246 | \r | |
| 5247 | <b>Example usage</b>\r | |
| 5248 | @code\r | |
| 5249 | UINT64 Msr;\r | |
| 5250 | \r | |
| 5251 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);\r | |
| 5252 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);\r | |
| 5253 | @endcode\r | |
| c2aa191b | 5254 | @note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r |
| bd946618 MK |
5255 | **/\r |
| 5256 | #define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3\r | |
| 5257 | \r | |
| 5258 | \r | |
| 5259 | /**\r | |
| 5260 | Package. Uncore C-box 5 perfmon event select MSR.\r | |
| 5261 | \r | |
| 5262 | @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)\r | |
| 5263 | @param EAX Lower 32-bits of MSR value.\r | |
| 5264 | @param EDX Upper 32-bits of MSR value.\r | |
| 5265 | \r | |
| 5266 | <b>Example usage</b>\r | |
| 5267 | @code\r | |
| 5268 | UINT64 Msr;\r | |
| 5269 | \r | |
| 5270 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);\r | |
| 5271 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);\r | |
| 5272 | @endcode\r | |
| c2aa191b | 5273 | @note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
5274 | **/\r |
| 5275 | #define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4\r | |
| 5276 | \r | |
| 5277 | \r | |
| 5278 | /**\r | |
| 5279 | Package. Uncore C-box 5 perfmon counter MSR.\r | |
| 5280 | \r | |
| 5281 | @param ECX MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)\r | |
| 5282 | @param EAX Lower 32-bits of MSR value.\r | |
| 5283 | @param EDX Upper 32-bits of MSR value.\r | |
| 5284 | \r | |
| 5285 | <b>Example usage</b>\r | |
| 5286 | @code\r | |
| 5287 | UINT64 Msr;\r | |
| 5288 | \r | |
| 5289 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);\r | |
| 5290 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);\r | |
| 5291 | @endcode\r | |
| c2aa191b | 5292 | @note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r |
| bd946618 MK |
5293 | **/\r |
| 5294 | #define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5\r | |
| 5295 | \r | |
| 5296 | \r | |
| 5297 | /**\r | |
| 5298 | Package. Uncore C-box 5 perfmon event select MSR.\r | |
| 5299 | \r | |
| 5300 | @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)\r | |
| 5301 | @param EAX Lower 32-bits of MSR value.\r | |
| 5302 | @param EDX Upper 32-bits of MSR value.\r | |
| 5303 | \r | |
| 5304 | <b>Example usage</b>\r | |
| 5305 | @code\r | |
| 5306 | UINT64 Msr;\r | |
| 5307 | \r | |
| 5308 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);\r | |
| 5309 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);\r | |
| 5310 | @endcode\r | |
| c2aa191b | 5311 | @note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
5312 | **/\r |
| 5313 | #define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6\r | |
| 5314 | \r | |
| 5315 | \r | |
| 5316 | /**\r | |
| 5317 | Package. Uncore C-box 5 perfmon counter MSR.\r | |
| 5318 | \r | |
| 5319 | @param ECX MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)\r | |
| 5320 | @param EAX Lower 32-bits of MSR value.\r | |
| 5321 | @param EDX Upper 32-bits of MSR value.\r | |
| 5322 | \r | |
| 5323 | <b>Example usage</b>\r | |
| 5324 | @code\r | |
| 5325 | UINT64 Msr;\r | |
| 5326 | \r | |
| 5327 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);\r | |
| 5328 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);\r | |
| 5329 | @endcode\r | |
| c2aa191b | 5330 | @note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r |
| bd946618 MK |
5331 | **/\r |
| 5332 | #define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7\r | |
| 5333 | \r | |
| 5334 | \r | |
| 5335 | /**\r | |
| 5336 | Package. Uncore C-box 5 perfmon event select MSR.\r | |
| 5337 | \r | |
| 5338 | @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)\r | |
| 5339 | @param EAX Lower 32-bits of MSR value.\r | |
| 5340 | @param EDX Upper 32-bits of MSR value.\r | |
| 5341 | \r | |
| 5342 | <b>Example usage</b>\r | |
| 5343 | @code\r | |
| 5344 | UINT64 Msr;\r | |
| 5345 | \r | |
| 5346 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);\r | |
| 5347 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);\r | |
| 5348 | @endcode\r | |
| c2aa191b | 5349 | @note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM.\r |
| bd946618 MK |
5350 | **/\r |
| 5351 | #define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8\r | |
| 5352 | \r | |
| 5353 | \r | |
| 5354 | /**\r | |
| 5355 | Package. Uncore C-box 5 perfmon counter MSR.\r | |
| 5356 | \r | |
| 5357 | @param ECX MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)\r | |
| 5358 | @param EAX Lower 32-bits of MSR value.\r | |
| 5359 | @param EDX Upper 32-bits of MSR value.\r | |
| 5360 | \r | |
| 5361 | <b>Example usage</b>\r | |
| 5362 | @code\r | |
| 5363 | UINT64 Msr;\r | |
| 5364 | \r | |
| 5365 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);\r | |
| 5366 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);\r | |
| 5367 | @endcode\r | |
| c2aa191b | 5368 | @note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM.\r |
| bd946618 MK |
5369 | **/\r |
| 5370 | #define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9\r | |
| 5371 | \r | |
| 5372 | \r | |
| 5373 | /**\r | |
| 5374 | Package. Uncore C-box 5 perfmon event select MSR.\r | |
| 5375 | \r | |
| 5376 | @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)\r | |
| 5377 | @param EAX Lower 32-bits of MSR value.\r | |
| 5378 | @param EDX Upper 32-bits of MSR value.\r | |
| 5379 | \r | |
| 5380 | <b>Example usage</b>\r | |
| 5381 | @code\r | |
| 5382 | UINT64 Msr;\r | |
| 5383 | \r | |
| 5384 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);\r | |
| 5385 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);\r | |
| 5386 | @endcode\r | |
| c2aa191b | 5387 | @note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM.\r |
| bd946618 MK |
5388 | **/\r |
| 5389 | #define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA\r | |
| 5390 | \r | |
| 5391 | \r | |
| 5392 | /**\r | |
| 5393 | Package. Uncore C-box 5 perfmon counter MSR.\r | |
| 5394 | \r | |
| 5395 | @param ECX MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)\r | |
| 5396 | @param EAX Lower 32-bits of MSR value.\r | |
| 5397 | @param EDX Upper 32-bits of MSR value.\r | |
| 5398 | \r | |
| 5399 | <b>Example usage</b>\r | |
| 5400 | @code\r | |
| 5401 | UINT64 Msr;\r | |
| 5402 | \r | |
| 5403 | Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);\r | |
| 5404 | AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);\r | |
| 5405 | @endcode\r | |
| c2aa191b | 5406 | @note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM.\r |
| bd946618 MK |
5407 | **/\r |
| 5408 | #define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB\r | |
| 5409 | \r | |
| 5410 | \r | |
| 5411 | /**\r | |
| 5412 | Package. Uncore C-box 3 perfmon local box control MSR.\r | |
| 5413 | \r | |
| 5414 | @param ECX MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)\r | |
| 5415 | @param EAX Lower 32-bits of MSR value.\r | |
| 5416 | @param EDX Upper 32-bits of MSR value.\r | |
| 5417 | \r | |
| 5418 | <b>Example usage</b>\r | |
| 5419 | @code\r | |
| 5420 | UINT64 Msr;\r | |
| 5421 | \r | |
| 5422 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);\r | |
| 5423 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);\r | |
| 5424 | @endcode\r | |
| c2aa191b | 5425 | @note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
5426 | **/\r |
| 5427 | #define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0\r | |
| 5428 | \r | |
| 5429 | \r | |
| 5430 | /**\r | |
| 5431 | Package. Uncore C-box 3 perfmon local box status MSR.\r | |
| 5432 | \r | |
| 5433 | @param ECX MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)\r | |
| 5434 | @param EAX Lower 32-bits of MSR value.\r | |
| 5435 | @param EDX Upper 32-bits of MSR value.\r | |
| 5436 | \r | |
| 5437 | <b>Example usage</b>\r | |
| 5438 | @code\r | |
| 5439 | UINT64 Msr;\r | |
| 5440 | \r | |
| 5441 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);\r | |
| 5442 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);\r | |
| 5443 | @endcode\r | |
| c2aa191b | 5444 | @note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
5445 | **/\r |
| 5446 | #define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1\r | |
| 5447 | \r | |
| 5448 | \r | |
| 5449 | /**\r | |
| 5450 | Package. Uncore C-box 3 perfmon local box overflow control MSR.\r | |
| 5451 | \r | |
| 5452 | @param ECX MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)\r | |
| 5453 | @param EAX Lower 32-bits of MSR value.\r | |
| 5454 | @param EDX Upper 32-bits of MSR value.\r | |
| 5455 | \r | |
| 5456 | <b>Example usage</b>\r | |
| 5457 | @code\r | |
| 5458 | UINT64 Msr;\r | |
| 5459 | \r | |
| 5460 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);\r | |
| 5461 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);\r | |
| 5462 | @endcode\r | |
| c2aa191b | 5463 | @note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
5464 | **/\r |
| 5465 | #define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2\r | |
| 5466 | \r | |
| 5467 | \r | |
| 5468 | /**\r | |
| 5469 | Package. Uncore C-box 3 perfmon event select MSR.\r | |
| 5470 | \r | |
| 5471 | @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)\r | |
| 5472 | @param EAX Lower 32-bits of MSR value.\r | |
| 5473 | @param EDX Upper 32-bits of MSR value.\r | |
| 5474 | \r | |
| 5475 | <b>Example usage</b>\r | |
| 5476 | @code\r | |
| 5477 | UINT64 Msr;\r | |
| 5478 | \r | |
| 5479 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);\r | |
| 5480 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);\r | |
| 5481 | @endcode\r | |
| c2aa191b | 5482 | @note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
5483 | **/\r |
| 5484 | #define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0\r | |
| 5485 | \r | |
| 5486 | \r | |
| 5487 | /**\r | |
| 5488 | Package. Uncore C-box 3 perfmon counter MSR.\r | |
| 5489 | \r | |
| 5490 | @param ECX MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)\r | |
| 5491 | @param EAX Lower 32-bits of MSR value.\r | |
| 5492 | @param EDX Upper 32-bits of MSR value.\r | |
| 5493 | \r | |
| 5494 | <b>Example usage</b>\r | |
| 5495 | @code\r | |
| 5496 | UINT64 Msr;\r | |
| 5497 | \r | |
| 5498 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);\r | |
| 5499 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);\r | |
| 5500 | @endcode\r | |
| c2aa191b | 5501 | @note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r |
| bd946618 MK |
5502 | **/\r |
| 5503 | #define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1\r | |
| 5504 | \r | |
| 5505 | \r | |
| 5506 | /**\r | |
| 5507 | Package. Uncore C-box 3 perfmon event select MSR.\r | |
| 5508 | \r | |
| 5509 | @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)\r | |
| 5510 | @param EAX Lower 32-bits of MSR value.\r | |
| 5511 | @param EDX Upper 32-bits of MSR value.\r | |
| 5512 | \r | |
| 5513 | <b>Example usage</b>\r | |
| 5514 | @code\r | |
| 5515 | UINT64 Msr;\r | |
| 5516 | \r | |
| 5517 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);\r | |
| 5518 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);\r | |
| 5519 | @endcode\r | |
| c2aa191b | 5520 | @note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
5521 | **/\r |
| 5522 | #define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2\r | |
| 5523 | \r | |
| 5524 | \r | |
| 5525 | /**\r | |
| 5526 | Package. Uncore C-box 3 perfmon counter MSR.\r | |
| 5527 | \r | |
| 5528 | @param ECX MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)\r | |
| 5529 | @param EAX Lower 32-bits of MSR value.\r | |
| 5530 | @param EDX Upper 32-bits of MSR value.\r | |
| 5531 | \r | |
| 5532 | <b>Example usage</b>\r | |
| 5533 | @code\r | |
| 5534 | UINT64 Msr;\r | |
| 5535 | \r | |
| 5536 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);\r | |
| 5537 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);\r | |
| 5538 | @endcode\r | |
| c2aa191b | 5539 | @note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r |
| bd946618 MK |
5540 | **/\r |
| 5541 | #define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3\r | |
| 5542 | \r | |
| 5543 | \r | |
| 5544 | /**\r | |
| 5545 | Package. Uncore C-box 3 perfmon event select MSR.\r | |
| 5546 | \r | |
| 5547 | @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)\r | |
| 5548 | @param EAX Lower 32-bits of MSR value.\r | |
| 5549 | @param EDX Upper 32-bits of MSR value.\r | |
| 5550 | \r | |
| 5551 | <b>Example usage</b>\r | |
| 5552 | @code\r | |
| 5553 | UINT64 Msr;\r | |
| 5554 | \r | |
| 5555 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);\r | |
| 5556 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);\r | |
| 5557 | @endcode\r | |
| c2aa191b | 5558 | @note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
5559 | **/\r |
| 5560 | #define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4\r | |
| 5561 | \r | |
| 5562 | \r | |
| 5563 | /**\r | |
| 5564 | Package. Uncore C-box 3 perfmon counter MSR.\r | |
| 5565 | \r | |
| 5566 | @param ECX MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)\r | |
| 5567 | @param EAX Lower 32-bits of MSR value.\r | |
| 5568 | @param EDX Upper 32-bits of MSR value.\r | |
| 5569 | \r | |
| 5570 | <b>Example usage</b>\r | |
| 5571 | @code\r | |
| 5572 | UINT64 Msr;\r | |
| 5573 | \r | |
| 5574 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);\r | |
| 5575 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);\r | |
| 5576 | @endcode\r | |
| c2aa191b | 5577 | @note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r |
| bd946618 MK |
5578 | **/\r |
| 5579 | #define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5\r | |
| 5580 | \r | |
| 5581 | \r | |
| 5582 | /**\r | |
| 5583 | Package. Uncore C-box 3 perfmon event select MSR.\r | |
| 5584 | \r | |
| 5585 | @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)\r | |
| 5586 | @param EAX Lower 32-bits of MSR value.\r | |
| 5587 | @param EDX Upper 32-bits of MSR value.\r | |
| 5588 | \r | |
| 5589 | <b>Example usage</b>\r | |
| 5590 | @code\r | |
| 5591 | UINT64 Msr;\r | |
| 5592 | \r | |
| 5593 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);\r | |
| 5594 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);\r | |
| 5595 | @endcode\r | |
| c2aa191b | 5596 | @note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
5597 | **/\r |
| 5598 | #define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6\r | |
| 5599 | \r | |
| 5600 | \r | |
| 5601 | /**\r | |
| 5602 | Package. Uncore C-box 3 perfmon counter MSR.\r | |
| 5603 | \r | |
| 5604 | @param ECX MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)\r | |
| 5605 | @param EAX Lower 32-bits of MSR value.\r | |
| 5606 | @param EDX Upper 32-bits of MSR value.\r | |
| 5607 | \r | |
| 5608 | <b>Example usage</b>\r | |
| 5609 | @code\r | |
| 5610 | UINT64 Msr;\r | |
| 5611 | \r | |
| 5612 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);\r | |
| 5613 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);\r | |
| 5614 | @endcode\r | |
| c2aa191b | 5615 | @note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r |
| bd946618 MK |
5616 | **/\r |
| 5617 | #define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7\r | |
| 5618 | \r | |
| 5619 | \r | |
| 5620 | /**\r | |
| 5621 | Package. Uncore C-box 3 perfmon event select MSR.\r | |
| 5622 | \r | |
| 5623 | @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)\r | |
| 5624 | @param EAX Lower 32-bits of MSR value.\r | |
| 5625 | @param EDX Upper 32-bits of MSR value.\r | |
| 5626 | \r | |
| 5627 | <b>Example usage</b>\r | |
| 5628 | @code\r | |
| 5629 | UINT64 Msr;\r | |
| 5630 | \r | |
| 5631 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);\r | |
| 5632 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);\r | |
| 5633 | @endcode\r | |
| c2aa191b | 5634 | @note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM.\r |
| bd946618 MK |
5635 | **/\r |
| 5636 | #define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8\r | |
| 5637 | \r | |
| 5638 | \r | |
| 5639 | /**\r | |
| 5640 | Package. Uncore C-box 3 perfmon counter MSR.\r | |
| 5641 | \r | |
| 5642 | @param ECX MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)\r | |
| 5643 | @param EAX Lower 32-bits of MSR value.\r | |
| 5644 | @param EDX Upper 32-bits of MSR value.\r | |
| 5645 | \r | |
| 5646 | <b>Example usage</b>\r | |
| 5647 | @code\r | |
| 5648 | UINT64 Msr;\r | |
| 5649 | \r | |
| 5650 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);\r | |
| 5651 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);\r | |
| 5652 | @endcode\r | |
| c2aa191b | 5653 | @note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM.\r |
| bd946618 MK |
5654 | **/\r |
| 5655 | #define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9\r | |
| 5656 | \r | |
| 5657 | \r | |
| 5658 | /**\r | |
| 5659 | Package. Uncore C-box 3 perfmon event select MSR.\r | |
| 5660 | \r | |
| 5661 | @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)\r | |
| 5662 | @param EAX Lower 32-bits of MSR value.\r | |
| 5663 | @param EDX Upper 32-bits of MSR value.\r | |
| 5664 | \r | |
| 5665 | <b>Example usage</b>\r | |
| 5666 | @code\r | |
| 5667 | UINT64 Msr;\r | |
| 5668 | \r | |
| 5669 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);\r | |
| 5670 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);\r | |
| 5671 | @endcode\r | |
| c2aa191b | 5672 | @note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM.\r |
| bd946618 MK |
5673 | **/\r |
| 5674 | #define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA\r | |
| 5675 | \r | |
| 5676 | \r | |
| 5677 | /**\r | |
| 5678 | Package. Uncore C-box 3 perfmon counter MSR.\r | |
| 5679 | \r | |
| 5680 | @param ECX MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)\r | |
| 5681 | @param EAX Lower 32-bits of MSR value.\r | |
| 5682 | @param EDX Upper 32-bits of MSR value.\r | |
| 5683 | \r | |
| 5684 | <b>Example usage</b>\r | |
| 5685 | @code\r | |
| 5686 | UINT64 Msr;\r | |
| 5687 | \r | |
| 5688 | Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);\r | |
| 5689 | AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);\r | |
| 5690 | @endcode\r | |
| c2aa191b | 5691 | @note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM.\r |
| bd946618 MK |
5692 | **/\r |
| 5693 | #define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB\r | |
| 5694 | \r | |
| 5695 | \r | |
| 5696 | /**\r | |
| 5697 | Package. Uncore C-box 7 perfmon local box control MSR.\r | |
| 5698 | \r | |
| 5699 | @param ECX MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)\r | |
| 5700 | @param EAX Lower 32-bits of MSR value.\r | |
| 5701 | @param EDX Upper 32-bits of MSR value.\r | |
| 5702 | \r | |
| 5703 | <b>Example usage</b>\r | |
| 5704 | @code\r | |
| 5705 | UINT64 Msr;\r | |
| 5706 | \r | |
| 5707 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);\r | |
| 5708 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);\r | |
| 5709 | @endcode\r | |
| c2aa191b | 5710 | @note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
5711 | **/\r |
| 5712 | #define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0\r | |
| 5713 | \r | |
| 5714 | \r | |
| 5715 | /**\r | |
| 5716 | Package. Uncore C-box 7 perfmon local box status MSR.\r | |
| 5717 | \r | |
| 5718 | @param ECX MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)\r | |
| 5719 | @param EAX Lower 32-bits of MSR value.\r | |
| 5720 | @param EDX Upper 32-bits of MSR value.\r | |
| 5721 | \r | |
| 5722 | <b>Example usage</b>\r | |
| 5723 | @code\r | |
| 5724 | UINT64 Msr;\r | |
| 5725 | \r | |
| 5726 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);\r | |
| 5727 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);\r | |
| 5728 | @endcode\r | |
| c2aa191b | 5729 | @note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
5730 | **/\r |
| 5731 | #define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1\r | |
| 5732 | \r | |
| 5733 | \r | |
| 5734 | /**\r | |
| 5735 | Package. Uncore C-box 7 perfmon local box overflow control MSR.\r | |
| 5736 | \r | |
| 5737 | @param ECX MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)\r | |
| 5738 | @param EAX Lower 32-bits of MSR value.\r | |
| 5739 | @param EDX Upper 32-bits of MSR value.\r | |
| 5740 | \r | |
| 5741 | <b>Example usage</b>\r | |
| 5742 | @code\r | |
| 5743 | UINT64 Msr;\r | |
| 5744 | \r | |
| 5745 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);\r | |
| 5746 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);\r | |
| 5747 | @endcode\r | |
| c2aa191b | 5748 | @note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
5749 | **/\r |
| 5750 | #define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2\r | |
| 5751 | \r | |
| 5752 | \r | |
| 5753 | /**\r | |
| 5754 | Package. Uncore C-box 7 perfmon event select MSR.\r | |
| 5755 | \r | |
| 5756 | @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)\r | |
| 5757 | @param EAX Lower 32-bits of MSR value.\r | |
| 5758 | @param EDX Upper 32-bits of MSR value.\r | |
| 5759 | \r | |
| 5760 | <b>Example usage</b>\r | |
| 5761 | @code\r | |
| 5762 | UINT64 Msr;\r | |
| 5763 | \r | |
| 5764 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);\r | |
| 5765 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);\r | |
| 5766 | @endcode\r | |
| c2aa191b | 5767 | @note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
5768 | **/\r |
| 5769 | #define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0\r | |
| 5770 | \r | |
| 5771 | \r | |
| 5772 | /**\r | |
| 5773 | Package. Uncore C-box 7 perfmon counter MSR.\r | |
| 5774 | \r | |
| 5775 | @param ECX MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)\r | |
| 5776 | @param EAX Lower 32-bits of MSR value.\r | |
| 5777 | @param EDX Upper 32-bits of MSR value.\r | |
| 5778 | \r | |
| 5779 | <b>Example usage</b>\r | |
| 5780 | @code\r | |
| 5781 | UINT64 Msr;\r | |
| 5782 | \r | |
| 5783 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);\r | |
| 5784 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);\r | |
| 5785 | @endcode\r | |
| c2aa191b | 5786 | @note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r |
| bd946618 MK |
5787 | **/\r |
| 5788 | #define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1\r | |
| 5789 | \r | |
| 5790 | \r | |
| 5791 | /**\r | |
| 5792 | Package. Uncore C-box 7 perfmon event select MSR.\r | |
| 5793 | \r | |
| 5794 | @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)\r | |
| 5795 | @param EAX Lower 32-bits of MSR value.\r | |
| 5796 | @param EDX Upper 32-bits of MSR value.\r | |
| 5797 | \r | |
| 5798 | <b>Example usage</b>\r | |
| 5799 | @code\r | |
| 5800 | UINT64 Msr;\r | |
| 5801 | \r | |
| 5802 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);\r | |
| 5803 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);\r | |
| 5804 | @endcode\r | |
| c2aa191b | 5805 | @note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
5806 | **/\r |
| 5807 | #define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2\r | |
| 5808 | \r | |
| 5809 | \r | |
| 5810 | /**\r | |
| 5811 | Package. Uncore C-box 7 perfmon counter MSR.\r | |
| 5812 | \r | |
| 5813 | @param ECX MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)\r | |
| 5814 | @param EAX Lower 32-bits of MSR value.\r | |
| 5815 | @param EDX Upper 32-bits of MSR value.\r | |
| 5816 | \r | |
| 5817 | <b>Example usage</b>\r | |
| 5818 | @code\r | |
| 5819 | UINT64 Msr;\r | |
| 5820 | \r | |
| 5821 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);\r | |
| 5822 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);\r | |
| 5823 | @endcode\r | |
| c2aa191b | 5824 | @note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r |
| bd946618 MK |
5825 | **/\r |
| 5826 | #define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3\r | |
| 5827 | \r | |
| 5828 | \r | |
| 5829 | /**\r | |
| 5830 | Package. Uncore C-box 7 perfmon event select MSR.\r | |
| 5831 | \r | |
| 5832 | @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)\r | |
| 5833 | @param EAX Lower 32-bits of MSR value.\r | |
| 5834 | @param EDX Upper 32-bits of MSR value.\r | |
| 5835 | \r | |
| 5836 | <b>Example usage</b>\r | |
| 5837 | @code\r | |
| 5838 | UINT64 Msr;\r | |
| 5839 | \r | |
| 5840 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);\r | |
| 5841 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);\r | |
| 5842 | @endcode\r | |
| c2aa191b | 5843 | @note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
5844 | **/\r |
| 5845 | #define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4\r | |
| 5846 | \r | |
| 5847 | \r | |
| 5848 | /**\r | |
| 5849 | Package. Uncore C-box 7 perfmon counter MSR.\r | |
| 5850 | \r | |
| 5851 | @param ECX MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)\r | |
| 5852 | @param EAX Lower 32-bits of MSR value.\r | |
| 5853 | @param EDX Upper 32-bits of MSR value.\r | |
| 5854 | \r | |
| 5855 | <b>Example usage</b>\r | |
| 5856 | @code\r | |
| 5857 | UINT64 Msr;\r | |
| 5858 | \r | |
| 5859 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);\r | |
| 5860 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);\r | |
| 5861 | @endcode\r | |
| c2aa191b | 5862 | @note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r |
| bd946618 MK |
5863 | **/\r |
| 5864 | #define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5\r | |
| 5865 | \r | |
| 5866 | \r | |
| 5867 | /**\r | |
| 5868 | Package. Uncore C-box 7 perfmon event select MSR.\r | |
| 5869 | \r | |
| 5870 | @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)\r | |
| 5871 | @param EAX Lower 32-bits of MSR value.\r | |
| 5872 | @param EDX Upper 32-bits of MSR value.\r | |
| 5873 | \r | |
| 5874 | <b>Example usage</b>\r | |
| 5875 | @code\r | |
| 5876 | UINT64 Msr;\r | |
| 5877 | \r | |
| 5878 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);\r | |
| 5879 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);\r | |
| 5880 | @endcode\r | |
| c2aa191b | 5881 | @note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
5882 | **/\r |
| 5883 | #define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6\r | |
| 5884 | \r | |
| 5885 | \r | |
| 5886 | /**\r | |
| 5887 | Package. Uncore C-box 7 perfmon counter MSR.\r | |
| 5888 | \r | |
| 5889 | @param ECX MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)\r | |
| 5890 | @param EAX Lower 32-bits of MSR value.\r | |
| 5891 | @param EDX Upper 32-bits of MSR value.\r | |
| 5892 | \r | |
| 5893 | <b>Example usage</b>\r | |
| 5894 | @code\r | |
| 5895 | UINT64 Msr;\r | |
| 5896 | \r | |
| 5897 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);\r | |
| 5898 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);\r | |
| 5899 | @endcode\r | |
| c2aa191b | 5900 | @note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r |
| bd946618 MK |
5901 | **/\r |
| 5902 | #define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7\r | |
| 5903 | \r | |
| 5904 | \r | |
| 5905 | /**\r | |
| 5906 | Package. Uncore C-box 7 perfmon event select MSR.\r | |
| 5907 | \r | |
| 5908 | @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)\r | |
| 5909 | @param EAX Lower 32-bits of MSR value.\r | |
| 5910 | @param EDX Upper 32-bits of MSR value.\r | |
| 5911 | \r | |
| 5912 | <b>Example usage</b>\r | |
| 5913 | @code\r | |
| 5914 | UINT64 Msr;\r | |
| 5915 | \r | |
| 5916 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);\r | |
| 5917 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);\r | |
| 5918 | @endcode\r | |
| c2aa191b | 5919 | @note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM.\r |
| bd946618 MK |
5920 | **/\r |
| 5921 | #define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8\r | |
| 5922 | \r | |
| 5923 | \r | |
| 5924 | /**\r | |
| 5925 | Package. Uncore C-box 7 perfmon counter MSR.\r | |
| 5926 | \r | |
| 5927 | @param ECX MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)\r | |
| 5928 | @param EAX Lower 32-bits of MSR value.\r | |
| 5929 | @param EDX Upper 32-bits of MSR value.\r | |
| 5930 | \r | |
| 5931 | <b>Example usage</b>\r | |
| 5932 | @code\r | |
| 5933 | UINT64 Msr;\r | |
| 5934 | \r | |
| 5935 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);\r | |
| 5936 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);\r | |
| 5937 | @endcode\r | |
| c2aa191b | 5938 | @note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM.\r |
| bd946618 MK |
5939 | **/\r |
| 5940 | #define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9\r | |
| 5941 | \r | |
| 5942 | \r | |
| 5943 | /**\r | |
| 5944 | Package. Uncore C-box 7 perfmon event select MSR.\r | |
| 5945 | \r | |
| 5946 | @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)\r | |
| 5947 | @param EAX Lower 32-bits of MSR value.\r | |
| 5948 | @param EDX Upper 32-bits of MSR value.\r | |
| 5949 | \r | |
| 5950 | <b>Example usage</b>\r | |
| 5951 | @code\r | |
| 5952 | UINT64 Msr;\r | |
| 5953 | \r | |
| 5954 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);\r | |
| 5955 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);\r | |
| 5956 | @endcode\r | |
| c2aa191b | 5957 | @note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM.\r |
| bd946618 MK |
5958 | **/\r |
| 5959 | #define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA\r | |
| 5960 | \r | |
| 5961 | \r | |
| 5962 | /**\r | |
| 5963 | Package. Uncore C-box 7 perfmon counter MSR.\r | |
| 5964 | \r | |
| 5965 | @param ECX MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)\r | |
| 5966 | @param EAX Lower 32-bits of MSR value.\r | |
| 5967 | @param EDX Upper 32-bits of MSR value.\r | |
| 5968 | \r | |
| 5969 | <b>Example usage</b>\r | |
| 5970 | @code\r | |
| 5971 | UINT64 Msr;\r | |
| 5972 | \r | |
| 5973 | Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);\r | |
| 5974 | AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);\r | |
| 5975 | @endcode\r | |
| c2aa191b | 5976 | @note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM.\r |
| bd946618 MK |
5977 | **/\r |
| 5978 | #define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB\r | |
| 5979 | \r | |
| 5980 | \r | |
| 5981 | /**\r | |
| 5982 | Package. Uncore R-box 0 perfmon local box control MSR.\r | |
| 5983 | \r | |
| 5984 | @param ECX MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)\r | |
| 5985 | @param EAX Lower 32-bits of MSR value.\r | |
| 5986 | @param EDX Upper 32-bits of MSR value.\r | |
| 5987 | \r | |
| 5988 | <b>Example usage</b>\r | |
| 5989 | @code\r | |
| 5990 | UINT64 Msr;\r | |
| 5991 | \r | |
| 5992 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);\r | |
| 5993 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);\r | |
| 5994 | @endcode\r | |
| c2aa191b | 5995 | @note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
5996 | **/\r |
| 5997 | #define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00\r | |
| 5998 | \r | |
| 5999 | \r | |
| 6000 | /**\r | |
| 6001 | Package. Uncore R-box 0 perfmon local box status MSR.\r | |
| 6002 | \r | |
| 6003 | @param ECX MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)\r | |
| 6004 | @param EAX Lower 32-bits of MSR value.\r | |
| 6005 | @param EDX Upper 32-bits of MSR value.\r | |
| 6006 | \r | |
| 6007 | <b>Example usage</b>\r | |
| 6008 | @code\r | |
| 6009 | UINT64 Msr;\r | |
| 6010 | \r | |
| 6011 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);\r | |
| 6012 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);\r | |
| 6013 | @endcode\r | |
| c2aa191b | 6014 | @note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
6015 | **/\r |
| 6016 | #define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01\r | |
| 6017 | \r | |
| 6018 | \r | |
| 6019 | /**\r | |
| 6020 | Package. Uncore R-box 0 perfmon local box overflow control MSR.\r | |
| 6021 | \r | |
| 6022 | @param ECX MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)\r | |
| 6023 | @param EAX Lower 32-bits of MSR value.\r | |
| 6024 | @param EDX Upper 32-bits of MSR value.\r | |
| 6025 | \r | |
| 6026 | <b>Example usage</b>\r | |
| 6027 | @code\r | |
| 6028 | UINT64 Msr;\r | |
| 6029 | \r | |
| 6030 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);\r | |
| 6031 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);\r | |
| 6032 | @endcode\r | |
| c2aa191b | 6033 | @note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
6034 | **/\r |
| 6035 | #define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02\r | |
| 6036 | \r | |
| 6037 | \r | |
| 6038 | /**\r | |
| 6039 | Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.\r | |
| 6040 | \r | |
| 6041 | @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)\r | |
| 6042 | @param EAX Lower 32-bits of MSR value.\r | |
| 6043 | @param EDX Upper 32-bits of MSR value.\r | |
| 6044 | \r | |
| 6045 | <b>Example usage</b>\r | |
| 6046 | @code\r | |
| 6047 | UINT64 Msr;\r | |
| 6048 | \r | |
| 6049 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);\r | |
| 6050 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);\r | |
| 6051 | @endcode\r | |
| c2aa191b | 6052 | @note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM.\r |
| bd946618 MK |
6053 | **/\r |
| 6054 | #define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04\r | |
| 6055 | \r | |
| 6056 | \r | |
| 6057 | /**\r | |
| 6058 | Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.\r | |
| 6059 | \r | |
| 6060 | @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)\r | |
| 6061 | @param EAX Lower 32-bits of MSR value.\r | |
| 6062 | @param EDX Upper 32-bits of MSR value.\r | |
| 6063 | \r | |
| 6064 | <b>Example usage</b>\r | |
| 6065 | @code\r | |
| 6066 | UINT64 Msr;\r | |
| 6067 | \r | |
| 6068 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);\r | |
| 6069 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);\r | |
| 6070 | @endcode\r | |
| c2aa191b | 6071 | @note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM.\r |
| bd946618 MK |
6072 | **/\r |
| 6073 | #define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05\r | |
| 6074 | \r | |
| 6075 | \r | |
| 6076 | /**\r | |
| 6077 | Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.\r | |
| 6078 | \r | |
| 6079 | @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)\r | |
| 6080 | @param EAX Lower 32-bits of MSR value.\r | |
| 6081 | @param EDX Upper 32-bits of MSR value.\r | |
| 6082 | \r | |
| 6083 | <b>Example usage</b>\r | |
| 6084 | @code\r | |
| 6085 | UINT64 Msr;\r | |
| 6086 | \r | |
| 6087 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);\r | |
| 6088 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);\r | |
| 6089 | @endcode\r | |
| c2aa191b | 6090 | @note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM.\r |
| bd946618 MK |
6091 | **/\r |
| 6092 | #define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06\r | |
| 6093 | \r | |
| 6094 | \r | |
| 6095 | /**\r | |
| 6096 | Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.\r | |
| 6097 | \r | |
| 6098 | @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)\r | |
| 6099 | @param EAX Lower 32-bits of MSR value.\r | |
| 6100 | @param EDX Upper 32-bits of MSR value.\r | |
| 6101 | \r | |
| 6102 | <b>Example usage</b>\r | |
| 6103 | @code\r | |
| 6104 | UINT64 Msr;\r | |
| 6105 | \r | |
| 6106 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);\r | |
| 6107 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);\r | |
| 6108 | @endcode\r | |
| c2aa191b | 6109 | @note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM.\r |
| bd946618 MK |
6110 | **/\r |
| 6111 | #define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07\r | |
| 6112 | \r | |
| 6113 | \r | |
| 6114 | /**\r | |
| 6115 | Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.\r | |
| 6116 | \r | |
| 6117 | @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)\r | |
| 6118 | @param EAX Lower 32-bits of MSR value.\r | |
| 6119 | @param EDX Upper 32-bits of MSR value.\r | |
| 6120 | \r | |
| 6121 | <b>Example usage</b>\r | |
| 6122 | @code\r | |
| 6123 | UINT64 Msr;\r | |
| 6124 | \r | |
| 6125 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);\r | |
| 6126 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);\r | |
| 6127 | @endcode\r | |
| c2aa191b | 6128 | @note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM.\r |
| bd946618 MK |
6129 | **/\r |
| 6130 | #define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08\r | |
| 6131 | \r | |
| 6132 | \r | |
| 6133 | /**\r | |
| 6134 | Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.\r | |
| 6135 | \r | |
| 6136 | @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)\r | |
| 6137 | @param EAX Lower 32-bits of MSR value.\r | |
| 6138 | @param EDX Upper 32-bits of MSR value.\r | |
| 6139 | \r | |
| 6140 | <b>Example usage</b>\r | |
| 6141 | @code\r | |
| 6142 | UINT64 Msr;\r | |
| 6143 | \r | |
| 6144 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);\r | |
| 6145 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);\r | |
| 6146 | @endcode\r | |
| c2aa191b | 6147 | @note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM.\r |
| bd946618 MK |
6148 | **/\r |
| 6149 | #define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09\r | |
| 6150 | \r | |
| 6151 | \r | |
| 6152 | /**\r | |
| 6153 | Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.\r | |
| 6154 | \r | |
| 6155 | @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)\r | |
| 6156 | @param EAX Lower 32-bits of MSR value.\r | |
| 6157 | @param EDX Upper 32-bits of MSR value.\r | |
| 6158 | \r | |
| 6159 | <b>Example usage</b>\r | |
| 6160 | @code\r | |
| 6161 | UINT64 Msr;\r | |
| 6162 | \r | |
| 6163 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);\r | |
| 6164 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);\r | |
| 6165 | @endcode\r | |
| c2aa191b | 6166 | @note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM.\r |
| bd946618 MK |
6167 | **/\r |
| 6168 | #define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A\r | |
| 6169 | \r | |
| 6170 | \r | |
| 6171 | /**\r | |
| 6172 | Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.\r | |
| 6173 | \r | |
| 6174 | @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)\r | |
| 6175 | @param EAX Lower 32-bits of MSR value.\r | |
| 6176 | @param EDX Upper 32-bits of MSR value.\r | |
| 6177 | \r | |
| 6178 | <b>Example usage</b>\r | |
| 6179 | @code\r | |
| 6180 | UINT64 Msr;\r | |
| 6181 | \r | |
| 6182 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);\r | |
| 6183 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);\r | |
| 6184 | @endcode\r | |
| c2aa191b | 6185 | @note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM.\r |
| bd946618 MK |
6186 | **/\r |
| 6187 | #define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B\r | |
| 6188 | \r | |
| 6189 | \r | |
| 6190 | /**\r | |
| 6191 | Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.\r | |
| 6192 | \r | |
| 6193 | @param ECX MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)\r | |
| 6194 | @param EAX Lower 32-bits of MSR value.\r | |
| 6195 | @param EDX Upper 32-bits of MSR value.\r | |
| 6196 | \r | |
| 6197 | <b>Example usage</b>\r | |
| 6198 | @code\r | |
| 6199 | UINT64 Msr;\r | |
| 6200 | \r | |
| 6201 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);\r | |
| 6202 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);\r | |
| 6203 | @endcode\r | |
| c2aa191b | 6204 | @note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM.\r |
| bd946618 MK |
6205 | **/\r |
| 6206 | #define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C\r | |
| 6207 | \r | |
| 6208 | \r | |
| 6209 | /**\r | |
| 6210 | Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.\r | |
| 6211 | \r | |
| 6212 | @param ECX MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)\r | |
| 6213 | @param EAX Lower 32-bits of MSR value.\r | |
| 6214 | @param EDX Upper 32-bits of MSR value.\r | |
| 6215 | \r | |
| 6216 | <b>Example usage</b>\r | |
| 6217 | @code\r | |
| 6218 | UINT64 Msr;\r | |
| 6219 | \r | |
| 6220 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);\r | |
| 6221 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);\r | |
| 6222 | @endcode\r | |
| c2aa191b | 6223 | @note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM.\r |
| bd946618 MK |
6224 | **/\r |
| 6225 | #define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D\r | |
| 6226 | \r | |
| 6227 | \r | |
| 6228 | /**\r | |
| 6229 | Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.\r | |
| 6230 | \r | |
| 6231 | @param ECX MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)\r | |
| 6232 | @param EAX Lower 32-bits of MSR value.\r | |
| 6233 | @param EDX Upper 32-bits of MSR value.\r | |
| 6234 | \r | |
| 6235 | <b>Example usage</b>\r | |
| 6236 | @code\r | |
| 6237 | UINT64 Msr;\r | |
| 6238 | \r | |
| 6239 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);\r | |
| 6240 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);\r | |
| 6241 | @endcode\r | |
| c2aa191b | 6242 | @note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM.\r |
| bd946618 MK |
6243 | **/\r |
| 6244 | #define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E\r | |
| 6245 | \r | |
| 6246 | \r | |
| 6247 | /**\r | |
| 6248 | Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.\r | |
| 6249 | \r | |
| 6250 | @param ECX MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)\r | |
| 6251 | @param EAX Lower 32-bits of MSR value.\r | |
| 6252 | @param EDX Upper 32-bits of MSR value.\r | |
| 6253 | \r | |
| 6254 | <b>Example usage</b>\r | |
| 6255 | @code\r | |
| 6256 | UINT64 Msr;\r | |
| 6257 | \r | |
| 6258 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);\r | |
| 6259 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);\r | |
| 6260 | @endcode\r | |
| c2aa191b | 6261 | @note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM.\r |
| bd946618 MK |
6262 | **/\r |
| 6263 | #define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F\r | |
| 6264 | \r | |
| 6265 | \r | |
| 6266 | /**\r | |
| 6267 | Package. Uncore R-box 0 perfmon event select MSR.\r | |
| 6268 | \r | |
| 6269 | @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)\r | |
| 6270 | @param EAX Lower 32-bits of MSR value.\r | |
| 6271 | @param EDX Upper 32-bits of MSR value.\r | |
| 6272 | \r | |
| 6273 | <b>Example usage</b>\r | |
| 6274 | @code\r | |
| 6275 | UINT64 Msr;\r | |
| 6276 | \r | |
| 6277 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);\r | |
| 6278 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);\r | |
| 6279 | @endcode\r | |
| c2aa191b | 6280 | @note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM.\r |
| bd946618 MK |
6281 | **/\r |
| 6282 | #define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10\r | |
| 6283 | \r | |
| 6284 | \r | |
| 6285 | /**\r | |
| 6286 | Package. Uncore R-box 0 perfmon counter MSR.\r | |
| 6287 | \r | |
| 6288 | @param ECX MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)\r | |
| 6289 | @param EAX Lower 32-bits of MSR value.\r | |
| 6290 | @param EDX Upper 32-bits of MSR value.\r | |
| 6291 | \r | |
| 6292 | <b>Example usage</b>\r | |
| 6293 | @code\r | |
| 6294 | UINT64 Msr;\r | |
| 6295 | \r | |
| 6296 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);\r | |
| 6297 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);\r | |
| 6298 | @endcode\r | |
| c2aa191b | 6299 | @note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM.\r |
| bd946618 MK |
6300 | **/\r |
| 6301 | #define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11\r | |
| 6302 | \r | |
| 6303 | \r | |
| 6304 | /**\r | |
| 6305 | Package. Uncore R-box 0 perfmon event select MSR.\r | |
| 6306 | \r | |
| 6307 | @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)\r | |
| 6308 | @param EAX Lower 32-bits of MSR value.\r | |
| 6309 | @param EDX Upper 32-bits of MSR value.\r | |
| 6310 | \r | |
| 6311 | <b>Example usage</b>\r | |
| 6312 | @code\r | |
| 6313 | UINT64 Msr;\r | |
| 6314 | \r | |
| 6315 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);\r | |
| 6316 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);\r | |
| 6317 | @endcode\r | |
| c2aa191b | 6318 | @note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM.\r |
| bd946618 MK |
6319 | **/\r |
| 6320 | #define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12\r | |
| 6321 | \r | |
| 6322 | \r | |
| 6323 | /**\r | |
| 6324 | Package. Uncore R-box 0 perfmon counter MSR.\r | |
| 6325 | \r | |
| 6326 | @param ECX MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)\r | |
| 6327 | @param EAX Lower 32-bits of MSR value.\r | |
| 6328 | @param EDX Upper 32-bits of MSR value.\r | |
| 6329 | \r | |
| 6330 | <b>Example usage</b>\r | |
| 6331 | @code\r | |
| 6332 | UINT64 Msr;\r | |
| 6333 | \r | |
| 6334 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);\r | |
| 6335 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);\r | |
| 6336 | @endcode\r | |
| c2aa191b | 6337 | @note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM.\r |
| bd946618 MK |
6338 | **/\r |
| 6339 | #define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13\r | |
| 6340 | \r | |
| 6341 | \r | |
| 6342 | /**\r | |
| 6343 | Package. Uncore R-box 0 perfmon event select MSR.\r | |
| 6344 | \r | |
| 6345 | @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)\r | |
| 6346 | @param EAX Lower 32-bits of MSR value.\r | |
| 6347 | @param EDX Upper 32-bits of MSR value.\r | |
| 6348 | \r | |
| 6349 | <b>Example usage</b>\r | |
| 6350 | @code\r | |
| 6351 | UINT64 Msr;\r | |
| 6352 | \r | |
| 6353 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);\r | |
| 6354 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);\r | |
| 6355 | @endcode\r | |
| c2aa191b | 6356 | @note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM.\r |
| bd946618 MK |
6357 | **/\r |
| 6358 | #define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14\r | |
| 6359 | \r | |
| 6360 | \r | |
| 6361 | /**\r | |
| 6362 | Package. Uncore R-box 0 perfmon counter MSR.\r | |
| 6363 | \r | |
| 6364 | @param ECX MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)\r | |
| 6365 | @param EAX Lower 32-bits of MSR value.\r | |
| 6366 | @param EDX Upper 32-bits of MSR value.\r | |
| 6367 | \r | |
| 6368 | <b>Example usage</b>\r | |
| 6369 | @code\r | |
| 6370 | UINT64 Msr;\r | |
| 6371 | \r | |
| 6372 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);\r | |
| 6373 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);\r | |
| 6374 | @endcode\r | |
| c2aa191b | 6375 | @note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM.\r |
| bd946618 MK |
6376 | **/\r |
| 6377 | #define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15\r | |
| 6378 | \r | |
| 6379 | \r | |
| 6380 | /**\r | |
| 6381 | Package. Uncore R-box 0 perfmon event select MSR.\r | |
| 6382 | \r | |
| 6383 | @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)\r | |
| 6384 | @param EAX Lower 32-bits of MSR value.\r | |
| 6385 | @param EDX Upper 32-bits of MSR value.\r | |
| 6386 | \r | |
| 6387 | <b>Example usage</b>\r | |
| 6388 | @code\r | |
| 6389 | UINT64 Msr;\r | |
| 6390 | \r | |
| 6391 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);\r | |
| 6392 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);\r | |
| 6393 | @endcode\r | |
| c2aa191b | 6394 | @note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM.\r |
| bd946618 MK |
6395 | **/\r |
| 6396 | #define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16\r | |
| 6397 | \r | |
| 6398 | \r | |
| 6399 | /**\r | |
| 6400 | Package. Uncore R-box 0 perfmon counter MSR.\r | |
| 6401 | \r | |
| 6402 | @param ECX MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)\r | |
| 6403 | @param EAX Lower 32-bits of MSR value.\r | |
| 6404 | @param EDX Upper 32-bits of MSR value.\r | |
| 6405 | \r | |
| 6406 | <b>Example usage</b>\r | |
| 6407 | @code\r | |
| 6408 | UINT64 Msr;\r | |
| 6409 | \r | |
| 6410 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);\r | |
| 6411 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);\r | |
| 6412 | @endcode\r | |
| c2aa191b | 6413 | @note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM.\r |
| bd946618 MK |
6414 | **/\r |
| 6415 | #define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17\r | |
| 6416 | \r | |
| 6417 | \r | |
| 6418 | /**\r | |
| 6419 | Package. Uncore R-box 0 perfmon event select MSR.\r | |
| 6420 | \r | |
| 6421 | @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)\r | |
| 6422 | @param EAX Lower 32-bits of MSR value.\r | |
| 6423 | @param EDX Upper 32-bits of MSR value.\r | |
| 6424 | \r | |
| 6425 | <b>Example usage</b>\r | |
| 6426 | @code\r | |
| 6427 | UINT64 Msr;\r | |
| 6428 | \r | |
| 6429 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);\r | |
| 6430 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);\r | |
| 6431 | @endcode\r | |
| c2aa191b | 6432 | @note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM.\r |
| bd946618 MK |
6433 | **/\r |
| 6434 | #define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18\r | |
| 6435 | \r | |
| 6436 | \r | |
| 6437 | /**\r | |
| 6438 | Package. Uncore R-box 0 perfmon counter MSR.\r | |
| 6439 | \r | |
| 6440 | @param ECX MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)\r | |
| 6441 | @param EAX Lower 32-bits of MSR value.\r | |
| 6442 | @param EDX Upper 32-bits of MSR value.\r | |
| 6443 | \r | |
| 6444 | <b>Example usage</b>\r | |
| 6445 | @code\r | |
| 6446 | UINT64 Msr;\r | |
| 6447 | \r | |
| 6448 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);\r | |
| 6449 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);\r | |
| 6450 | @endcode\r | |
| c2aa191b | 6451 | @note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM.\r |
| bd946618 MK |
6452 | **/\r |
| 6453 | #define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19\r | |
| 6454 | \r | |
| 6455 | \r | |
| 6456 | /**\r | |
| 6457 | Package. Uncore R-box 0 perfmon event select MSR.\r | |
| 6458 | \r | |
| 6459 | @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)\r | |
| 6460 | @param EAX Lower 32-bits of MSR value.\r | |
| 6461 | @param EDX Upper 32-bits of MSR value.\r | |
| 6462 | \r | |
| 6463 | <b>Example usage</b>\r | |
| 6464 | @code\r | |
| 6465 | UINT64 Msr;\r | |
| 6466 | \r | |
| 6467 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);\r | |
| 6468 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);\r | |
| 6469 | @endcode\r | |
| c2aa191b | 6470 | @note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM.\r |
| bd946618 MK |
6471 | **/\r |
| 6472 | #define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A\r | |
| 6473 | \r | |
| 6474 | \r | |
| 6475 | /**\r | |
| 6476 | Package. Uncore R-box 0 perfmon counter MSR.\r | |
| 6477 | \r | |
| 6478 | @param ECX MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)\r | |
| 6479 | @param EAX Lower 32-bits of MSR value.\r | |
| 6480 | @param EDX Upper 32-bits of MSR value.\r | |
| 6481 | \r | |
| 6482 | <b>Example usage</b>\r | |
| 6483 | @code\r | |
| 6484 | UINT64 Msr;\r | |
| 6485 | \r | |
| 6486 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);\r | |
| 6487 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);\r | |
| 6488 | @endcode\r | |
| c2aa191b | 6489 | @note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM.\r |
| bd946618 MK |
6490 | **/\r |
| 6491 | #define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B\r | |
| 6492 | \r | |
| 6493 | \r | |
| 6494 | /**\r | |
| 6495 | Package. Uncore R-box 0 perfmon event select MSR.\r | |
| 6496 | \r | |
| 6497 | @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)\r | |
| 6498 | @param EAX Lower 32-bits of MSR value.\r | |
| 6499 | @param EDX Upper 32-bits of MSR value.\r | |
| 6500 | \r | |
| 6501 | <b>Example usage</b>\r | |
| 6502 | @code\r | |
| 6503 | UINT64 Msr;\r | |
| 6504 | \r | |
| 6505 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);\r | |
| 6506 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);\r | |
| 6507 | @endcode\r | |
| c2aa191b | 6508 | @note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM.\r |
| bd946618 MK |
6509 | **/\r |
| 6510 | #define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C\r | |
| 6511 | \r | |
| 6512 | \r | |
| 6513 | /**\r | |
| 6514 | Package. Uncore R-box 0 perfmon counter MSR.\r | |
| 6515 | \r | |
| 6516 | @param ECX MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)\r | |
| 6517 | @param EAX Lower 32-bits of MSR value.\r | |
| 6518 | @param EDX Upper 32-bits of MSR value.\r | |
| 6519 | \r | |
| 6520 | <b>Example usage</b>\r | |
| 6521 | @code\r | |
| 6522 | UINT64 Msr;\r | |
| 6523 | \r | |
| 6524 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);\r | |
| 6525 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);\r | |
| 6526 | @endcode\r | |
| c2aa191b | 6527 | @note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM.\r |
| bd946618 MK |
6528 | **/\r |
| 6529 | #define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D\r | |
| 6530 | \r | |
| 6531 | \r | |
| 6532 | /**\r | |
| 6533 | Package. Uncore R-box 0 perfmon event select MSR.\r | |
| 6534 | \r | |
| 6535 | @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)\r | |
| 6536 | @param EAX Lower 32-bits of MSR value.\r | |
| 6537 | @param EDX Upper 32-bits of MSR value.\r | |
| 6538 | \r | |
| 6539 | <b>Example usage</b>\r | |
| 6540 | @code\r | |
| 6541 | UINT64 Msr;\r | |
| 6542 | \r | |
| 6543 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);\r | |
| 6544 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);\r | |
| 6545 | @endcode\r | |
| c2aa191b | 6546 | @note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM.\r |
| bd946618 MK |
6547 | **/\r |
| 6548 | #define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E\r | |
| 6549 | \r | |
| 6550 | \r | |
| 6551 | /**\r | |
| 6552 | Package. Uncore R-box 0 perfmon counter MSR.\r | |
| 6553 | \r | |
| 6554 | @param ECX MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)\r | |
| 6555 | @param EAX Lower 32-bits of MSR value.\r | |
| 6556 | @param EDX Upper 32-bits of MSR value.\r | |
| 6557 | \r | |
| 6558 | <b>Example usage</b>\r | |
| 6559 | @code\r | |
| 6560 | UINT64 Msr;\r | |
| 6561 | \r | |
| 6562 | Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);\r | |
| 6563 | AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);\r | |
| 6564 | @endcode\r | |
| c2aa191b | 6565 | @note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM.\r |
| bd946618 MK |
6566 | **/\r |
| 6567 | #define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F\r | |
| 6568 | \r | |
| 6569 | \r | |
| 6570 | /**\r | |
| 6571 | Package. Uncore R-box 1 perfmon local box control MSR.\r | |
| 6572 | \r | |
| 6573 | @param ECX MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)\r | |
| 6574 | @param EAX Lower 32-bits of MSR value.\r | |
| 6575 | @param EDX Upper 32-bits of MSR value.\r | |
| 6576 | \r | |
| 6577 | <b>Example usage</b>\r | |
| 6578 | @code\r | |
| 6579 | UINT64 Msr;\r | |
| 6580 | \r | |
| 6581 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);\r | |
| 6582 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);\r | |
| 6583 | @endcode\r | |
| c2aa191b | 6584 | @note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM.\r |
| bd946618 MK |
6585 | **/\r |
| 6586 | #define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20\r | |
| 6587 | \r | |
| 6588 | \r | |
| 6589 | /**\r | |
| 6590 | Package. Uncore R-box 1 perfmon local box status MSR.\r | |
| 6591 | \r | |
| 6592 | @param ECX MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)\r | |
| 6593 | @param EAX Lower 32-bits of MSR value.\r | |
| 6594 | @param EDX Upper 32-bits of MSR value.\r | |
| 6595 | \r | |
| 6596 | <b>Example usage</b>\r | |
| 6597 | @code\r | |
| 6598 | UINT64 Msr;\r | |
| 6599 | \r | |
| 6600 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);\r | |
| 6601 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);\r | |
| 6602 | @endcode\r | |
| c2aa191b | 6603 | @note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM.\r |
| bd946618 MK |
6604 | **/\r |
| 6605 | #define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21\r | |
| 6606 | \r | |
| 6607 | \r | |
| 6608 | /**\r | |
| 6609 | Package. Uncore R-box 1 perfmon local box overflow control MSR.\r | |
| 6610 | \r | |
| 6611 | @param ECX MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)\r | |
| 6612 | @param EAX Lower 32-bits of MSR value.\r | |
| 6613 | @param EDX Upper 32-bits of MSR value.\r | |
| 6614 | \r | |
| 6615 | <b>Example usage</b>\r | |
| 6616 | @code\r | |
| 6617 | UINT64 Msr;\r | |
| 6618 | \r | |
| 6619 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);\r | |
| 6620 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);\r | |
| 6621 | @endcode\r | |
| c2aa191b | 6622 | @note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM.\r |
| bd946618 MK |
6623 | **/\r |
| 6624 | #define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22\r | |
| 6625 | \r | |
| 6626 | \r | |
| 6627 | /**\r | |
| 6628 | Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.\r | |
| 6629 | \r | |
| 6630 | @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)\r | |
| 6631 | @param EAX Lower 32-bits of MSR value.\r | |
| 6632 | @param EDX Upper 32-bits of MSR value.\r | |
| 6633 | \r | |
| 6634 | <b>Example usage</b>\r | |
| 6635 | @code\r | |
| 6636 | UINT64 Msr;\r | |
| 6637 | \r | |
| 6638 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);\r | |
| 6639 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);\r | |
| 6640 | @endcode\r | |
| c2aa191b | 6641 | @note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM.\r |
| bd946618 MK |
6642 | **/\r |
| 6643 | #define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24\r | |
| 6644 | \r | |
| 6645 | \r | |
| 6646 | /**\r | |
| 6647 | Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.\r | |
| 6648 | \r | |
| 6649 | @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)\r | |
| 6650 | @param EAX Lower 32-bits of MSR value.\r | |
| 6651 | @param EDX Upper 32-bits of MSR value.\r | |
| 6652 | \r | |
| 6653 | <b>Example usage</b>\r | |
| 6654 | @code\r | |
| 6655 | UINT64 Msr;\r | |
| 6656 | \r | |
| 6657 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);\r | |
| 6658 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);\r | |
| 6659 | @endcode\r | |
| c2aa191b | 6660 | @note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM.\r |
| bd946618 MK |
6661 | **/\r |
| 6662 | #define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25\r | |
| 6663 | \r | |
| 6664 | \r | |
| 6665 | /**\r | |
| 6666 | Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.\r | |
| 6667 | \r | |
| 6668 | @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)\r | |
| 6669 | @param EAX Lower 32-bits of MSR value.\r | |
| 6670 | @param EDX Upper 32-bits of MSR value.\r | |
| 6671 | \r | |
| 6672 | <b>Example usage</b>\r | |
| 6673 | @code\r | |
| 6674 | UINT64 Msr;\r | |
| 6675 | \r | |
| 6676 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);\r | |
| 6677 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);\r | |
| 6678 | @endcode\r | |
| c2aa191b | 6679 | @note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM.\r |
| bd946618 MK |
6680 | **/\r |
| 6681 | #define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26\r | |
| 6682 | \r | |
| 6683 | \r | |
| 6684 | /**\r | |
| 6685 | Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.\r | |
| 6686 | \r | |
| 6687 | @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)\r | |
| 6688 | @param EAX Lower 32-bits of MSR value.\r | |
| 6689 | @param EDX Upper 32-bits of MSR value.\r | |
| 6690 | \r | |
| 6691 | <b>Example usage</b>\r | |
| 6692 | @code\r | |
| 6693 | UINT64 Msr;\r | |
| 6694 | \r | |
| 6695 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);\r | |
| 6696 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);\r | |
| 6697 | @endcode\r | |
| c2aa191b | 6698 | @note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM.\r |
| bd946618 MK |
6699 | **/\r |
| 6700 | #define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27\r | |
| 6701 | \r | |
| 6702 | \r | |
| 6703 | /**\r | |
| 6704 | Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.\r | |
| 6705 | \r | |
| 6706 | @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)\r | |
| 6707 | @param EAX Lower 32-bits of MSR value.\r | |
| 6708 | @param EDX Upper 32-bits of MSR value.\r | |
| 6709 | \r | |
| 6710 | <b>Example usage</b>\r | |
| 6711 | @code\r | |
| 6712 | UINT64 Msr;\r | |
| 6713 | \r | |
| 6714 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);\r | |
| 6715 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);\r | |
| 6716 | @endcode\r | |
| c2aa191b | 6717 | @note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM.\r |
| bd946618 MK |
6718 | **/\r |
| 6719 | #define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28\r | |
| 6720 | \r | |
| 6721 | \r | |
| 6722 | /**\r | |
| 6723 | Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.\r | |
| 6724 | \r | |
| 6725 | @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)\r | |
| 6726 | @param EAX Lower 32-bits of MSR value.\r | |
| 6727 | @param EDX Upper 32-bits of MSR value.\r | |
| 6728 | \r | |
| 6729 | <b>Example usage</b>\r | |
| 6730 | @code\r | |
| 6731 | UINT64 Msr;\r | |
| 6732 | \r | |
| 6733 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);\r | |
| 6734 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);\r | |
| 6735 | @endcode\r | |
| c2aa191b | 6736 | @note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM.\r |
| bd946618 MK |
6737 | **/\r |
| 6738 | #define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29\r | |
| 6739 | \r | |
| 6740 | \r | |
| 6741 | /**\r | |
| 6742 | Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.\r | |
| 6743 | \r | |
| 6744 | @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)\r | |
| 6745 | @param EAX Lower 32-bits of MSR value.\r | |
| 6746 | @param EDX Upper 32-bits of MSR value.\r | |
| 6747 | \r | |
| 6748 | <b>Example usage</b>\r | |
| 6749 | @code\r | |
| 6750 | UINT64 Msr;\r | |
| 6751 | \r | |
| 6752 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);\r | |
| 6753 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);\r | |
| 6754 | @endcode\r | |
| c2aa191b | 6755 | @note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM.\r |
| bd946618 MK |
6756 | **/\r |
| 6757 | #define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A\r | |
| 6758 | \r | |
| 6759 | \r | |
| 6760 | /**\r | |
| 6761 | Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.\r | |
| 6762 | \r | |
| 6763 | @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)\r | |
| 6764 | @param EAX Lower 32-bits of MSR value.\r | |
| 6765 | @param EDX Upper 32-bits of MSR value.\r | |
| 6766 | \r | |
| 6767 | <b>Example usage</b>\r | |
| 6768 | @code\r | |
| 6769 | UINT64 Msr;\r | |
| 6770 | \r | |
| 6771 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);\r | |
| 6772 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);\r | |
| 6773 | @endcode\r | |
| c2aa191b | 6774 | @note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM.\r |
| bd946618 MK |
6775 | **/\r |
| 6776 | #define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B\r | |
| 6777 | \r | |
| 6778 | \r | |
| 6779 | /**\r | |
| 6780 | Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.\r | |
| 6781 | \r | |
| 6782 | @param ECX MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)\r | |
| 6783 | @param EAX Lower 32-bits of MSR value.\r | |
| 6784 | @param EDX Upper 32-bits of MSR value.\r | |
| 6785 | \r | |
| 6786 | <b>Example usage</b>\r | |
| 6787 | @code\r | |
| 6788 | UINT64 Msr;\r | |
| 6789 | \r | |
| 6790 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);\r | |
| 6791 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);\r | |
| 6792 | @endcode\r | |
| c2aa191b | 6793 | @note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM.\r |
| bd946618 MK |
6794 | **/\r |
| 6795 | #define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C\r | |
| 6796 | \r | |
| 6797 | \r | |
| 6798 | /**\r | |
| 6799 | Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.\r | |
| 6800 | \r | |
| 6801 | @param ECX MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)\r | |
| 6802 | @param EAX Lower 32-bits of MSR value.\r | |
| 6803 | @param EDX Upper 32-bits of MSR value.\r | |
| 6804 | \r | |
| 6805 | <b>Example usage</b>\r | |
| 6806 | @code\r | |
| 6807 | UINT64 Msr;\r | |
| 6808 | \r | |
| 6809 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);\r | |
| 6810 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);\r | |
| 6811 | @endcode\r | |
| c2aa191b | 6812 | @note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM.\r |
| bd946618 MK |
6813 | **/\r |
| 6814 | #define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D\r | |
| 6815 | \r | |
| 6816 | \r | |
| 6817 | /**\r | |
| 6818 | Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.\r | |
| 6819 | \r | |
| 6820 | @param ECX MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)\r | |
| 6821 | @param EAX Lower 32-bits of MSR value.\r | |
| 6822 | @param EDX Upper 32-bits of MSR value.\r | |
| 6823 | \r | |
| 6824 | <b>Example usage</b>\r | |
| 6825 | @code\r | |
| 6826 | UINT64 Msr;\r | |
| 6827 | \r | |
| 6828 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);\r | |
| 6829 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);\r | |
| 6830 | @endcode\r | |
| c2aa191b | 6831 | @note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM.\r |
| bd946618 MK |
6832 | **/\r |
| 6833 | #define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E\r | |
| 6834 | \r | |
| 6835 | \r | |
| 6836 | /**\r | |
| 6837 | Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.\r | |
| 6838 | \r | |
| 6839 | @param ECX MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)\r | |
| 6840 | @param EAX Lower 32-bits of MSR value.\r | |
| 6841 | @param EDX Upper 32-bits of MSR value.\r | |
| 6842 | \r | |
| 6843 | <b>Example usage</b>\r | |
| 6844 | @code\r | |
| 6845 | UINT64 Msr;\r | |
| 6846 | \r | |
| 6847 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);\r | |
| 6848 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);\r | |
| 6849 | @endcode\r | |
| c2aa191b | 6850 | @note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM.\r |
| bd946618 MK |
6851 | **/\r |
| 6852 | #define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F\r | |
| 6853 | \r | |
| 6854 | \r | |
| 6855 | /**\r | |
| 6856 | Package. Uncore R-box 1 perfmon event select MSR.\r | |
| 6857 | \r | |
| 6858 | @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)\r | |
| 6859 | @param EAX Lower 32-bits of MSR value.\r | |
| 6860 | @param EDX Upper 32-bits of MSR value.\r | |
| 6861 | \r | |
| 6862 | <b>Example usage</b>\r | |
| 6863 | @code\r | |
| 6864 | UINT64 Msr;\r | |
| 6865 | \r | |
| 6866 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);\r | |
| 6867 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);\r | |
| 6868 | @endcode\r | |
| c2aa191b | 6869 | @note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM.\r |
| bd946618 MK |
6870 | **/\r |
| 6871 | #define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30\r | |
| 6872 | \r | |
| 6873 | \r | |
| 6874 | /**\r | |
| 6875 | Package. Uncore R-box 1 perfmon counter MSR.\r | |
| 6876 | \r | |
| 6877 | @param ECX MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)\r | |
| 6878 | @param EAX Lower 32-bits of MSR value.\r | |
| 6879 | @param EDX Upper 32-bits of MSR value.\r | |
| 6880 | \r | |
| 6881 | <b>Example usage</b>\r | |
| 6882 | @code\r | |
| 6883 | UINT64 Msr;\r | |
| 6884 | \r | |
| 6885 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);\r | |
| 6886 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);\r | |
| 6887 | @endcode\r | |
| c2aa191b | 6888 | @note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM.\r |
| bd946618 MK |
6889 | **/\r |
| 6890 | #define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31\r | |
| 6891 | \r | |
| 6892 | \r | |
| 6893 | /**\r | |
| 6894 | Package. Uncore R-box 1 perfmon event select MSR.\r | |
| 6895 | \r | |
| 6896 | @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)\r | |
| 6897 | @param EAX Lower 32-bits of MSR value.\r | |
| 6898 | @param EDX Upper 32-bits of MSR value.\r | |
| 6899 | \r | |
| 6900 | <b>Example usage</b>\r | |
| 6901 | @code\r | |
| 6902 | UINT64 Msr;\r | |
| 6903 | \r | |
| 6904 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);\r | |
| 6905 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);\r | |
| 6906 | @endcode\r | |
| c2aa191b | 6907 | @note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM.\r |
| bd946618 MK |
6908 | **/\r |
| 6909 | #define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32\r | |
| 6910 | \r | |
| 6911 | \r | |
| 6912 | /**\r | |
| 6913 | Package. Uncore R-box 1 perfmon counter MSR.\r | |
| 6914 | \r | |
| 6915 | @param ECX MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)\r | |
| 6916 | @param EAX Lower 32-bits of MSR value.\r | |
| 6917 | @param EDX Upper 32-bits of MSR value.\r | |
| 6918 | \r | |
| 6919 | <b>Example usage</b>\r | |
| 6920 | @code\r | |
| 6921 | UINT64 Msr;\r | |
| 6922 | \r | |
| 6923 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);\r | |
| 6924 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);\r | |
| 6925 | @endcode\r | |
| c2aa191b | 6926 | @note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM.\r |
| bd946618 MK |
6927 | **/\r |
| 6928 | #define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33\r | |
| 6929 | \r | |
| 6930 | \r | |
| 6931 | /**\r | |
| 6932 | Package. Uncore R-box 1 perfmon event select MSR.\r | |
| 6933 | \r | |
| 6934 | @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)\r | |
| 6935 | @param EAX Lower 32-bits of MSR value.\r | |
| 6936 | @param EDX Upper 32-bits of MSR value.\r | |
| 6937 | \r | |
| 6938 | <b>Example usage</b>\r | |
| 6939 | @code\r | |
| 6940 | UINT64 Msr;\r | |
| 6941 | \r | |
| 6942 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);\r | |
| 6943 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);\r | |
| 6944 | @endcode\r | |
| c2aa191b | 6945 | @note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM.\r |
| bd946618 MK |
6946 | **/\r |
| 6947 | #define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34\r | |
| 6948 | \r | |
| 6949 | \r | |
| 6950 | /**\r | |
| 6951 | Package. Uncore R-box 1 perfmon counter MSR.\r | |
| 6952 | \r | |
| 6953 | @param ECX MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)\r | |
| 6954 | @param EAX Lower 32-bits of MSR value.\r | |
| 6955 | @param EDX Upper 32-bits of MSR value.\r | |
| 6956 | \r | |
| 6957 | <b>Example usage</b>\r | |
| 6958 | @code\r | |
| 6959 | UINT64 Msr;\r | |
| 6960 | \r | |
| 6961 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);\r | |
| 6962 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);\r | |
| 6963 | @endcode\r | |
| c2aa191b | 6964 | @note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM.\r |
| bd946618 MK |
6965 | **/\r |
| 6966 | #define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35\r | |
| 6967 | \r | |
| 6968 | \r | |
| 6969 | /**\r | |
| 6970 | Package. Uncore R-box 1 perfmon event select MSR.\r | |
| 6971 | \r | |
| 6972 | @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)\r | |
| 6973 | @param EAX Lower 32-bits of MSR value.\r | |
| 6974 | @param EDX Upper 32-bits of MSR value.\r | |
| 6975 | \r | |
| 6976 | <b>Example usage</b>\r | |
| 6977 | @code\r | |
| 6978 | UINT64 Msr;\r | |
| 6979 | \r | |
| 6980 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);\r | |
| 6981 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);\r | |
| 6982 | @endcode\r | |
| c2aa191b | 6983 | @note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM.\r |
| bd946618 MK |
6984 | **/\r |
| 6985 | #define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36\r | |
| 6986 | \r | |
| 6987 | \r | |
| 6988 | /**\r | |
| 6989 | Package. Uncore R-box 1 perfmon counter MSR.\r | |
| 6990 | \r | |
| 6991 | @param ECX MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)\r | |
| 6992 | @param EAX Lower 32-bits of MSR value.\r | |
| 6993 | @param EDX Upper 32-bits of MSR value.\r | |
| 6994 | \r | |
| 6995 | <b>Example usage</b>\r | |
| 6996 | @code\r | |
| 6997 | UINT64 Msr;\r | |
| 6998 | \r | |
| 6999 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);\r | |
| 7000 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);\r | |
| 7001 | @endcode\r | |
| c2aa191b | 7002 | @note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM.\r |
| bd946618 MK |
7003 | **/\r |
| 7004 | #define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37\r | |
| 7005 | \r | |
| 7006 | \r | |
| 7007 | /**\r | |
| 7008 | Package. Uncore R-box 1 perfmon event select MSR.\r | |
| 7009 | \r | |
| 7010 | @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)\r | |
| 7011 | @param EAX Lower 32-bits of MSR value.\r | |
| 7012 | @param EDX Upper 32-bits of MSR value.\r | |
| 7013 | \r | |
| 7014 | <b>Example usage</b>\r | |
| 7015 | @code\r | |
| 7016 | UINT64 Msr;\r | |
| 7017 | \r | |
| 7018 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);\r | |
| 7019 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);\r | |
| 7020 | @endcode\r | |
| c2aa191b | 7021 | @note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM.\r |
| bd946618 MK |
7022 | **/\r |
| 7023 | #define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38\r | |
| 7024 | \r | |
| 7025 | \r | |
| 7026 | /**\r | |
| 7027 | Package. Uncore R-box 1 perfmon counter MSR.\r | |
| 7028 | \r | |
| 7029 | @param ECX MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)\r | |
| 7030 | @param EAX Lower 32-bits of MSR value.\r | |
| 7031 | @param EDX Upper 32-bits of MSR value.\r | |
| 7032 | \r | |
| 7033 | <b>Example usage</b>\r | |
| 7034 | @code\r | |
| 7035 | UINT64 Msr;\r | |
| 7036 | \r | |
| 7037 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);\r | |
| 7038 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);\r | |
| 7039 | @endcode\r | |
| c2aa191b | 7040 | @note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM.\r |
| bd946618 MK |
7041 | **/\r |
| 7042 | #define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39\r | |
| 7043 | \r | |
| 7044 | \r | |
| 7045 | /**\r | |
| 7046 | Package. Uncore R-box 1 perfmon event select MSR.\r | |
| 7047 | \r | |
| 7048 | @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)\r | |
| 7049 | @param EAX Lower 32-bits of MSR value.\r | |
| 7050 | @param EDX Upper 32-bits of MSR value.\r | |
| 7051 | \r | |
| 7052 | <b>Example usage</b>\r | |
| 7053 | @code\r | |
| 7054 | UINT64 Msr;\r | |
| 7055 | \r | |
| 7056 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);\r | |
| 7057 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);\r | |
| 7058 | @endcode\r | |
| c2aa191b | 7059 | @note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM.\r |
| bd946618 MK |
7060 | **/\r |
| 7061 | #define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A\r | |
| 7062 | \r | |
| 7063 | \r | |
| 7064 | /**\r | |
| 7065 | Package. Uncore R-box 1perfmon counter MSR.\r | |
| 7066 | \r | |
| 7067 | @param ECX MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)\r | |
| 7068 | @param EAX Lower 32-bits of MSR value.\r | |
| 7069 | @param EDX Upper 32-bits of MSR value.\r | |
| 7070 | \r | |
| 7071 | <b>Example usage</b>\r | |
| 7072 | @code\r | |
| 7073 | UINT64 Msr;\r | |
| 7074 | \r | |
| 7075 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);\r | |
| 7076 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);\r | |
| 7077 | @endcode\r | |
| c2aa191b | 7078 | @note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM.\r |
| bd946618 MK |
7079 | **/\r |
| 7080 | #define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B\r | |
| 7081 | \r | |
| 7082 | \r | |
| 7083 | /**\r | |
| 7084 | Package. Uncore R-box 1 perfmon event select MSR.\r | |
| 7085 | \r | |
| 7086 | @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)\r | |
| 7087 | @param EAX Lower 32-bits of MSR value.\r | |
| 7088 | @param EDX Upper 32-bits of MSR value.\r | |
| 7089 | \r | |
| 7090 | <b>Example usage</b>\r | |
| 7091 | @code\r | |
| 7092 | UINT64 Msr;\r | |
| 7093 | \r | |
| 7094 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);\r | |
| 7095 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);\r | |
| 7096 | @endcode\r | |
| c2aa191b | 7097 | @note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM.\r |
| bd946618 MK |
7098 | **/\r |
| 7099 | #define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C\r | |
| 7100 | \r | |
| 7101 | \r | |
| 7102 | /**\r | |
| 7103 | Package. Uncore R-box 1 perfmon counter MSR.\r | |
| 7104 | \r | |
| 7105 | @param ECX MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)\r | |
| 7106 | @param EAX Lower 32-bits of MSR value.\r | |
| 7107 | @param EDX Upper 32-bits of MSR value.\r | |
| 7108 | \r | |
| 7109 | <b>Example usage</b>\r | |
| 7110 | @code\r | |
| 7111 | UINT64 Msr;\r | |
| 7112 | \r | |
| 7113 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);\r | |
| 7114 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);\r | |
| 7115 | @endcode\r | |
| c2aa191b | 7116 | @note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM.\r |
| bd946618 MK |
7117 | **/\r |
| 7118 | #define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D\r | |
| 7119 | \r | |
| 7120 | \r | |
| 7121 | /**\r | |
| 7122 | Package. Uncore R-box 1 perfmon event select MSR.\r | |
| 7123 | \r | |
| 7124 | @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)\r | |
| 7125 | @param EAX Lower 32-bits of MSR value.\r | |
| 7126 | @param EDX Upper 32-bits of MSR value.\r | |
| 7127 | \r | |
| 7128 | <b>Example usage</b>\r | |
| 7129 | @code\r | |
| 7130 | UINT64 Msr;\r | |
| 7131 | \r | |
| 7132 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);\r | |
| 7133 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);\r | |
| 7134 | @endcode\r | |
| c2aa191b | 7135 | @note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM.\r |
| bd946618 MK |
7136 | **/\r |
| 7137 | #define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E\r | |
| 7138 | \r | |
| 7139 | \r | |
| 7140 | /**\r | |
| 7141 | Package. Uncore R-box 1 perfmon counter MSR.\r | |
| 7142 | \r | |
| 7143 | @param ECX MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)\r | |
| 7144 | @param EAX Lower 32-bits of MSR value.\r | |
| 7145 | @param EDX Upper 32-bits of MSR value.\r | |
| 7146 | \r | |
| 7147 | <b>Example usage</b>\r | |
| 7148 | @code\r | |
| 7149 | UINT64 Msr;\r | |
| 7150 | \r | |
| 7151 | Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);\r | |
| 7152 | AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);\r | |
| 7153 | @endcode\r | |
| c2aa191b | 7154 | @note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM.\r |
| bd946618 MK |
7155 | **/\r |
| 7156 | #define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F\r | |
| 7157 | \r | |
| 7158 | \r | |
| 7159 | /**\r | |
| 7160 | Package. Uncore B-box 0 perfmon local box match MSR.\r | |
| 7161 | \r | |
| 7162 | @param ECX MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)\r | |
| 7163 | @param EAX Lower 32-bits of MSR value.\r | |
| 7164 | @param EDX Upper 32-bits of MSR value.\r | |
| 7165 | \r | |
| 7166 | <b>Example usage</b>\r | |
| 7167 | @code\r | |
| 7168 | UINT64 Msr;\r | |
| 7169 | \r | |
| 7170 | Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);\r | |
| 7171 | AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);\r | |
| 7172 | @endcode\r | |
| c2aa191b | 7173 | @note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM.\r |
| bd946618 MK |
7174 | **/\r |
| 7175 | #define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45\r | |
| 7176 | \r | |
| 7177 | \r | |
| 7178 | /**\r | |
| 7179 | Package. Uncore B-box 0 perfmon local box mask MSR.\r | |
| 7180 | \r | |
| 7181 | @param ECX MSR_NEHALEM_B0_PMON_MASK (0x00000E46)\r | |
| 7182 | @param EAX Lower 32-bits of MSR value.\r | |
| 7183 | @param EDX Upper 32-bits of MSR value.\r | |
| 7184 | \r | |
| 7185 | <b>Example usage</b>\r | |
| 7186 | @code\r | |
| 7187 | UINT64 Msr;\r | |
| 7188 | \r | |
| 7189 | Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);\r | |
| 7190 | AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);\r | |
| 7191 | @endcode\r | |
| c2aa191b | 7192 | @note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM.\r |
| bd946618 MK |
7193 | **/\r |
| 7194 | #define MSR_NEHALEM_B0_PMON_MASK 0x00000E46\r | |
| 7195 | \r | |
| 7196 | \r | |
| 7197 | /**\r | |
| 7198 | Package. Uncore S-box 0 perfmon local box match MSR.\r | |
| 7199 | \r | |
| 7200 | @param ECX MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)\r | |
| 7201 | @param EAX Lower 32-bits of MSR value.\r | |
| 7202 | @param EDX Upper 32-bits of MSR value.\r | |
| 7203 | \r | |
| 7204 | <b>Example usage</b>\r | |
| 7205 | @code\r | |
| 7206 | UINT64 Msr;\r | |
| 7207 | \r | |
| 7208 | Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);\r | |
| 7209 | AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);\r | |
| 7210 | @endcode\r | |
| c2aa191b | 7211 | @note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM.\r |
| bd946618 MK |
7212 | **/\r |
| 7213 | #define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49\r | |
| 7214 | \r | |
| 7215 | \r | |
| 7216 | /**\r | |
| 7217 | Package. Uncore S-box 0 perfmon local box mask MSR.\r | |
| 7218 | \r | |
| 7219 | @param ECX MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)\r | |
| 7220 | @param EAX Lower 32-bits of MSR value.\r | |
| 7221 | @param EDX Upper 32-bits of MSR value.\r | |
| 7222 | \r | |
| 7223 | <b>Example usage</b>\r | |
| 7224 | @code\r | |
| 7225 | UINT64 Msr;\r | |
| 7226 | \r | |
| 7227 | Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);\r | |
| 7228 | AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);\r | |
| 7229 | @endcode\r | |
| c2aa191b | 7230 | @note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM.\r |
| bd946618 MK |
7231 | **/\r |
| 7232 | #define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A\r | |
| 7233 | \r | |
| 7234 | \r | |
| 7235 | /**\r | |
| 7236 | Package. Uncore B-box 1 perfmon local box match MSR.\r | |
| 7237 | \r | |
| 7238 | @param ECX MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)\r | |
| 7239 | @param EAX Lower 32-bits of MSR value.\r | |
| 7240 | @param EDX Upper 32-bits of MSR value.\r | |
| 7241 | \r | |
| 7242 | <b>Example usage</b>\r | |
| 7243 | @code\r | |
| 7244 | UINT64 Msr;\r | |
| 7245 | \r | |
| 7246 | Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);\r | |
| 7247 | AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);\r | |
| 7248 | @endcode\r | |
| c2aa191b | 7249 | @note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM.\r |
| bd946618 MK |
7250 | **/\r |
| 7251 | #define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D\r | |
| 7252 | \r | |
| 7253 | \r | |
| 7254 | /**\r | |
| 7255 | Package. Uncore B-box 1 perfmon local box mask MSR.\r | |
| 7256 | \r | |
| 7257 | @param ECX MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)\r | |
| 7258 | @param EAX Lower 32-bits of MSR value.\r | |
| 7259 | @param EDX Upper 32-bits of MSR value.\r | |
| 7260 | \r | |
| 7261 | <b>Example usage</b>\r | |
| 7262 | @code\r | |
| 7263 | UINT64 Msr;\r | |
| 7264 | \r | |
| 7265 | Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);\r | |
| 7266 | AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);\r | |
| 7267 | @endcode\r | |
| c2aa191b | 7268 | @note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM.\r |
| bd946618 MK |
7269 | **/\r |
| 7270 | #define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E\r | |
| 7271 | \r | |
| 7272 | \r | |
| 7273 | /**\r | |
| 7274 | Package. Uncore M-box 0 perfmon local box address match/mask config MSR.\r | |
| 7275 | \r | |
| 7276 | @param ECX MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)\r | |
| 7277 | @param EAX Lower 32-bits of MSR value.\r | |
| 7278 | @param EDX Upper 32-bits of MSR value.\r | |
| 7279 | \r | |
| 7280 | <b>Example usage</b>\r | |
| 7281 | @code\r | |
| 7282 | UINT64 Msr;\r | |
| 7283 | \r | |
| 7284 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);\r | |
| 7285 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);\r | |
| 7286 | @endcode\r | |
| c2aa191b | 7287 | @note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM.\r |
| bd946618 MK |
7288 | **/\r |
| 7289 | #define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54\r | |
| 7290 | \r | |
| 7291 | \r | |
| 7292 | /**\r | |
| 7293 | Package. Uncore M-box 0 perfmon local box address match MSR.\r | |
| 7294 | \r | |
| 7295 | @param ECX MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)\r | |
| 7296 | @param EAX Lower 32-bits of MSR value.\r | |
| 7297 | @param EDX Upper 32-bits of MSR value.\r | |
| 7298 | \r | |
| 7299 | <b>Example usage</b>\r | |
| 7300 | @code\r | |
| 7301 | UINT64 Msr;\r | |
| 7302 | \r | |
| 7303 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);\r | |
| 7304 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);\r | |
| 7305 | @endcode\r | |
| c2aa191b | 7306 | @note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM.\r |
| bd946618 MK |
7307 | **/\r |
| 7308 | #define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55\r | |
| 7309 | \r | |
| 7310 | \r | |
| 7311 | /**\r | |
| 7312 | Package. Uncore M-box 0 perfmon local box address mask MSR.\r | |
| 7313 | \r | |
| 7314 | @param ECX MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)\r | |
| 7315 | @param EAX Lower 32-bits of MSR value.\r | |
| 7316 | @param EDX Upper 32-bits of MSR value.\r | |
| 7317 | \r | |
| 7318 | <b>Example usage</b>\r | |
| 7319 | @code\r | |
| 7320 | UINT64 Msr;\r | |
| 7321 | \r | |
| 7322 | Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);\r | |
| 7323 | AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);\r | |
| 7324 | @endcode\r | |
| c2aa191b | 7325 | @note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM.\r |
| bd946618 MK |
7326 | **/\r |
| 7327 | #define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56\r | |
| 7328 | \r | |
| 7329 | \r | |
| 7330 | /**\r | |
| 7331 | Package. Uncore S-box 1 perfmon local box match MSR.\r | |
| 7332 | \r | |
| 7333 | @param ECX MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)\r | |
| 7334 | @param EAX Lower 32-bits of MSR value.\r | |
| 7335 | @param EDX Upper 32-bits of MSR value.\r | |
| 7336 | \r | |
| 7337 | <b>Example usage</b>\r | |
| 7338 | @code\r | |
| 7339 | UINT64 Msr;\r | |
| 7340 | \r | |
| 7341 | Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);\r | |
| 7342 | AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);\r | |
| 7343 | @endcode\r | |
| c2aa191b | 7344 | @note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM.\r |
| bd946618 MK |
7345 | **/\r |
| 7346 | #define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59\r | |
| 7347 | \r | |
| 7348 | \r | |
| 7349 | /**\r | |
| 7350 | Package. Uncore S-box 1 perfmon local box mask MSR.\r | |
| 7351 | \r | |
| 7352 | @param ECX MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)\r | |
| 7353 | @param EAX Lower 32-bits of MSR value.\r | |
| 7354 | @param EDX Upper 32-bits of MSR value.\r | |
| 7355 | \r | |
| 7356 | <b>Example usage</b>\r | |
| 7357 | @code\r | |
| 7358 | UINT64 Msr;\r | |
| 7359 | \r | |
| 7360 | Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);\r | |
| 7361 | AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);\r | |
| 7362 | @endcode\r | |
| c2aa191b | 7363 | @note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM.\r |
| bd946618 MK |
7364 | **/\r |
| 7365 | #define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A\r | |
| 7366 | \r | |
| 7367 | \r | |
| 7368 | /**\r | |
| 7369 | Package. Uncore M-box 1 perfmon local box address match/mask config MSR.\r | |
| 7370 | \r | |
| 7371 | @param ECX MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)\r | |
| 7372 | @param EAX Lower 32-bits of MSR value.\r | |
| 7373 | @param EDX Upper 32-bits of MSR value.\r | |
| 7374 | \r | |
| 7375 | <b>Example usage</b>\r | |
| 7376 | @code\r | |
| 7377 | UINT64 Msr;\r | |
| 7378 | \r | |
| 7379 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);\r | |
| 7380 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);\r | |
| 7381 | @endcode\r | |
| c2aa191b | 7382 | @note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM.\r |
| bd946618 MK |
7383 | **/\r |
| 7384 | #define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C\r | |
| 7385 | \r | |
| 7386 | \r | |
| 7387 | /**\r | |
| 7388 | Package. Uncore M-box 1 perfmon local box address match MSR.\r | |
| 7389 | \r | |
| 7390 | @param ECX MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)\r | |
| 7391 | @param EAX Lower 32-bits of MSR value.\r | |
| 7392 | @param EDX Upper 32-bits of MSR value.\r | |
| 7393 | \r | |
| 7394 | <b>Example usage</b>\r | |
| 7395 | @code\r | |
| 7396 | UINT64 Msr;\r | |
| 7397 | \r | |
| 7398 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);\r | |
| 7399 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);\r | |
| 7400 | @endcode\r | |
| c2aa191b | 7401 | @note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM.\r |
| bd946618 MK |
7402 | **/\r |
| 7403 | #define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D\r | |
| 7404 | \r | |
| 7405 | \r | |
| 7406 | /**\r | |
| 7407 | Package. Uncore M-box 1 perfmon local box address mask MSR.\r | |
| 7408 | \r | |
| 7409 | @param ECX MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)\r | |
| 7410 | @param EAX Lower 32-bits of MSR value.\r | |
| 7411 | @param EDX Upper 32-bits of MSR value.\r | |
| 7412 | \r | |
| 7413 | <b>Example usage</b>\r | |
| 7414 | @code\r | |
| 7415 | UINT64 Msr;\r | |
| 7416 | \r | |
| 7417 | Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);\r | |
| 7418 | AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);\r | |
| 7419 | @endcode\r | |
| c2aa191b | 7420 | @note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM.\r |
| bd946618 MK |
7421 | **/\r |
| 7422 | #define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E\r | |
| 7423 | \r | |
| 7424 | #endif\r |