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1 | /** @file\r |
2 | STM Resource Descriptor\r | |
3 | \r | |
4 | Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php.\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | @par Specification Reference:\r | |
14 | SMI Transfer Monitor (STM) User Guide Revision 1.00\r | |
15 | \r | |
16 | **/\r | |
17 | \r | |
18 | #ifndef _STM_RESOURCE_DESCRIPTOR_H_\r | |
19 | #define _STM_RESOURCE_DESCRIPTOR_H_\r | |
20 | \r | |
21 | #pragma pack (1)\r | |
22 | \r | |
23 | /**\r | |
24 | STM Resource Descriptor Header\r | |
25 | **/\r | |
26 | typedef struct {\r | |
27 | UINT32 RscType;\r | |
28 | UINT16 Length;\r | |
29 | UINT16 ReturnStatus:1;\r | |
30 | UINT16 Reserved:14;\r | |
31 | UINT16 IgnoreResource:1;\r | |
32 | } STM_RSC_DESC_HEADER;\r | |
33 | \r | |
34 | /**\r | |
35 | Define values for the RscType field of #STM_RSC_DESC_HEADER\r | |
36 | @{\r | |
37 | **/\r | |
38 | #define END_OF_RESOURCES 0\r | |
39 | #define MEM_RANGE 1\r | |
40 | #define IO_RANGE 2\r | |
41 | #define MMIO_RANGE 3\r | |
42 | #define MACHINE_SPECIFIC_REG 4\r | |
43 | #define PCI_CFG_RANGE 5\r | |
44 | #define TRAPPED_IO_RANGE 6\r | |
45 | #define ALL_RESOURCES 7\r | |
46 | #define REGISTER_VIOLATION 8\r | |
47 | #define MAX_DESC_TYPE 8\r | |
48 | /// @}\r | |
49 | \r | |
50 | /**\r | |
51 | STM Resource End Descriptor\r | |
52 | **/\r | |
53 | typedef struct {\r | |
54 | STM_RSC_DESC_HEADER Hdr;\r | |
55 | UINT64 ResourceListContinuation;\r | |
56 | } STM_RSC_END;\r | |
57 | \r | |
58 | /**\r | |
59 | STM Resource Memory Descriptor\r | |
60 | **/\r | |
61 | typedef struct {\r | |
62 | STM_RSC_DESC_HEADER Hdr;\r | |
63 | UINT64 Base;\r | |
64 | UINT64 Length;\r | |
65 | UINT32 RWXAttributes:3;\r | |
66 | UINT32 Reserved:29;\r | |
67 | UINT32 Reserved_2;\r | |
68 | } STM_RSC_MEM_DESC;\r | |
69 | \r | |
70 | /**\r | |
71 | Define values for the RWXAttributes field of #STM_RSC_MEM_DESC\r | |
72 | @{\r | |
73 | **/\r | |
74 | #define STM_RSC_MEM_R 0x1\r | |
75 | #define STM_RSC_MEM_W 0x2\r | |
76 | #define STM_RSC_MEM_X 0x4\r | |
77 | /// @}\r | |
78 | \r | |
79 | /**\r | |
80 | STM Resource I/O Descriptor\r | |
81 | **/\r | |
82 | typedef struct {\r | |
83 | STM_RSC_DESC_HEADER Hdr;\r | |
84 | UINT16 Base;\r | |
85 | UINT16 Length;\r | |
86 | UINT32 Reserved;\r | |
87 | } STM_RSC_IO_DESC;\r | |
88 | \r | |
89 | /**\r | |
90 | STM Resource MMIO Descriptor\r | |
91 | **/\r | |
92 | typedef struct {\r | |
93 | STM_RSC_DESC_HEADER Hdr;\r | |
94 | UINT64 Base;\r | |
95 | UINT64 Length;\r | |
96 | UINT32 RWXAttributes:3;\r | |
97 | UINT32 Reserved:29;\r | |
98 | UINT32 Reserved_2;\r | |
99 | } STM_RSC_MMIO_DESC;\r | |
100 | \r | |
101 | /**\r | |
102 | Define values for the RWXAttributes field of #STM_RSC_MMIO_DESC\r | |
103 | @{\r | |
104 | **/\r | |
105 | #define STM_RSC_MMIO_R 0x1\r | |
106 | #define STM_RSC_MMIO_W 0x2\r | |
107 | #define STM_RSC_MMIO_X 0x4\r | |
108 | /// @}\r | |
109 | \r | |
110 | /**\r | |
111 | STM Resource MSR Descriptor\r | |
112 | **/\r | |
113 | typedef struct {\r | |
114 | STM_RSC_DESC_HEADER Hdr;\r | |
115 | UINT32 MsrIndex;\r | |
116 | UINT32 KernelModeProcessing:1;\r | |
117 | UINT32 Reserved:31;\r | |
118 | UINT64 ReadMask;\r | |
119 | UINT64 WriteMask;\r | |
120 | } STM_RSC_MSR_DESC;\r | |
121 | \r | |
122 | /**\r | |
123 | STM PCI Device Path node used for the PciDevicePath field of\r | |
124 | #STM_RSC_PCI_CFG_DESC\r | |
125 | **/\r | |
126 | typedef struct {\r | |
127 | ///\r | |
128 | /// Must be 1, indicating Hardware Device Path\r | |
129 | ///\r | |
130 | UINT8 Type;\r | |
131 | ///\r | |
132 | /// Must be 1, indicating PCI\r | |
133 | ///\r | |
134 | UINT8 Subtype;\r | |
135 | ///\r | |
136 | /// sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6\r | |
137 | ///\r | |
138 | UINT16 Length;\r | |
139 | UINT8 PciFunction;\r | |
140 | UINT8 PciDevice;\r | |
141 | } STM_PCI_DEVICE_PATH_NODE;\r | |
142 | \r | |
143 | /**\r | |
144 | STM Resource PCI Configuration Descriptor\r | |
145 | **/\r | |
146 | typedef struct {\r | |
147 | STM_RSC_DESC_HEADER Hdr;\r | |
148 | UINT16 RWAttributes:2;\r | |
149 | UINT16 Reserved:14;\r | |
150 | UINT16 Base;\r | |
151 | UINT16 Length;\r | |
152 | UINT8 OriginatingBusNumber;\r | |
153 | UINT8 LastNodeIndex;\r | |
154 | STM_PCI_DEVICE_PATH_NODE PciDevicePath[1];\r | |
155 | //STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1];\r | |
156 | } STM_RSC_PCI_CFG_DESC;\r | |
157 | \r | |
158 | /**\r | |
159 | Define values for the RWAttributes field of #STM_RSC_PCI_CFG_DESC\r | |
160 | @{\r | |
161 | **/\r | |
162 | #define STM_RSC_PCI_CFG_R 0x1\r | |
163 | #define STM_RSC_PCI_CFG_W 0x2\r | |
164 | /// @}\r | |
165 | \r | |
166 | /**\r | |
167 | STM Resource Trapped I/O Descriptor\r | |
168 | **/\r | |
169 | typedef struct {\r | |
170 | STM_RSC_DESC_HEADER Hdr;\r | |
171 | UINT16 Base;\r | |
172 | UINT16 Length;\r | |
173 | UINT16 In:1;\r | |
174 | UINT16 Out:1;\r | |
175 | UINT16 Api:1;\r | |
176 | UINT16 Reserved1:13;\r | |
177 | UINT16 Reserved2;\r | |
178 | } STM_RSC_TRAPPED_IO_DESC;\r | |
179 | \r | |
180 | /**\r | |
181 | STM Resource All Descriptor\r | |
182 | **/\r | |
183 | typedef struct {\r | |
184 | STM_RSC_DESC_HEADER Hdr;\r | |
185 | } STM_RSC_ALL_RESOURCES_DESC;\r | |
186 | \r | |
187 | /**\r | |
188 | STM Register Volation Descriptor\r | |
189 | **/\r | |
190 | typedef struct {\r | |
191 | STM_RSC_DESC_HEADER Hdr;\r | |
192 | UINT32 RegisterType;\r | |
193 | UINT32 Reserved;\r | |
194 | UINT64 ReadMask;\r | |
195 | UINT64 WriteMask;\r | |
196 | } STM_REGISTER_VIOLATION_DESC;\r | |
197 | \r | |
198 | /**\r | |
199 | Enum values for the RWAttributes field of #STM_REGISTER_VIOLATION_DESC\r | |
200 | **/\r | |
201 | typedef enum {\r | |
202 | StmRegisterCr0,\r | |
203 | StmRegisterCr2,\r | |
204 | StmRegisterCr3,\r | |
205 | StmRegisterCr4,\r | |
206 | StmRegisterCr8,\r | |
207 | StmRegisterMax,\r | |
208 | } STM_REGISTER_VIOLATION_TYPE;\r | |
209 | \r | |
210 | /**\r | |
211 | Union of all STM resource types\r | |
212 | **/\r | |
213 | typedef union {\r | |
214 | STM_RSC_DESC_HEADER Header;\r | |
215 | STM_RSC_END End;\r | |
216 | STM_RSC_MEM_DESC Mem;\r | |
217 | STM_RSC_IO_DESC Io;\r | |
218 | STM_RSC_MMIO_DESC Mmio;\r | |
219 | STM_RSC_MSR_DESC Msr;\r | |
220 | STM_RSC_PCI_CFG_DESC PciCfg;\r | |
221 | STM_RSC_TRAPPED_IO_DESC TrappedIo;\r | |
222 | STM_RSC_ALL_RESOURCES_DESC All;\r | |
223 | STM_REGISTER_VIOLATION_DESC RegisterViolation;\r | |
224 | } STM_RSC;\r | |
225 | \r | |
226 | #pragma pack ()\r | |
227 | \r | |
228 | #endif\r |