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1 | ;------------------------------------------------------------------------------\r |
2 | ;*\r | |
5b78f30d | 3 | ;* Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r |
f893042d LG |
4 | ;* This program and the accompanying materials\r |
5 | ;* are licensed and made available under the terms and conditions of the BSD License\r | |
6 | ;* which accompanies this distribution. The full text of the license may be found at\r | |
7 | ;* http://opensource.org/licenses/bsd-license.php\r | |
8 | ;*\r | |
9 | ;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | ;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | ;*\r | |
12 | ;*\r | |
13 | ;------------------------------------------------------------------------------\r | |
14 | \r | |
5b78f30d | 15 | SECTION .rodata\r |
f893042d LG |
16 | \r |
17 | ;\r | |
18 | ; Float control word initial value:\r | |
19 | ; all exceptions masked, double-precision, round-to-nearest\r | |
20 | ;\r | |
21 | mFpuControlWord: DW 0x27F\r | |
22 | ;\r | |
23 | ; Multimedia-extensions control word:\r | |
24 | ; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r | |
25 | ;\r | |
26 | mMmxControlWord: DD 0x1F80\r | |
27 | \r | |
28 | SECTION .text\r | |
29 | \r | |
30 | ;\r | |
31 | ; Initializes floating point units for requirement of UEFI specification.\r | |
32 | ;\r | |
33 | ; This function initializes floating-point control word to 0x027F (all exceptions\r | |
34 | ; masked,double-precision, round-to-nearest) and multimedia-extensions control word\r | |
35 | ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r | |
36 | ; for masked underflow).\r | |
37 | ;\r | |
38 | global ASM_PFX(InitializeFloatingPointUnits)\r | |
39 | ASM_PFX(InitializeFloatingPointUnits):\r | |
40 | \r | |
41 | push ebx\r | |
42 | \r | |
43 | ;\r | |
44 | ; Initialize floating point units\r | |
45 | ;\r | |
46 | finit\r | |
47 | fldcw [mFpuControlWord]\r | |
48 | \r | |
49 | ;\r | |
50 | ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r | |
51 | ; whether the processor supports SSE instruction.\r | |
52 | ;\r | |
53 | mov eax, 1\r | |
54 | cpuid\r | |
55 | bt edx, 25\r | |
56 | jnc Done\r | |
57 | \r | |
58 | ;\r | |
59 | ; Set OSFXSR bit 9 in CR4\r | |
60 | ;\r | |
61 | mov eax, cr4\r | |
62 | or eax, BIT9\r | |
63 | mov cr4, eax\r | |
64 | \r | |
65 | ;\r | |
66 | ; The processor should support SSE instruction and we can use\r | |
67 | ; ldmxcsr instruction\r | |
68 | ;\r | |
69 | ldmxcsr [mMmxControlWord]\r | |
70 | Done:\r | |
71 | pop ebx\r | |
72 | \r | |
73 | ret\r | |
74 | \r |