]>
Commit | Line | Data |
---|---|---|
80c4b236 JF |
1 | /** @file\r |
2 | Machine Check features.\r | |
3 | \r | |
dc7363f8 | 4 | Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r |
80c4b236 JF |
5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include "CpuCommonFeatures.h"\r | |
16 | \r | |
17 | /**\r | |
18 | Detects if Machine Check Exception feature supported on current processor.\r | |
19 | \r | |
20 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
21 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
22 | structure for the CPU executing this function.\r | |
23 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
24 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
25 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
26 | RegisterCpuFeature().\r | |
27 | \r | |
28 | @retval TRUE Machine Check Exception feature is supported.\r | |
29 | @retval FALSE Machine Check Exception feature is not supported.\r | |
30 | \r | |
31 | @note This service could be called by BSP/APs.\r | |
32 | **/\r | |
33 | BOOLEAN\r | |
34 | EFIAPI\r | |
35 | MceSupport (\r | |
36 | IN UINTN ProcessorNumber,\r | |
37 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
38 | IN VOID *ConfigData OPTIONAL\r | |
39 | )\r | |
40 | {\r | |
41 | return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCE == 1);\r | |
42 | }\r | |
43 | \r | |
44 | /**\r | |
45 | Initializes Machine Check Exception feature to specific state.\r | |
46 | \r | |
47 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
48 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
49 | structure for the CPU executing this function.\r | |
50 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
51 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
52 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
53 | RegisterCpuFeature().\r | |
54 | @param[in] State If TRUE, then the Machine Check Exception feature must be enabled.\r | |
55 | If FALSE, then the Machine Check Exception feature must be disabled.\r | |
56 | \r | |
57 | @retval RETURN_SUCCESS Machine Check Exception feature is initialized.\r | |
58 | \r | |
59 | @note This service could be called by BSP only.\r | |
60 | **/\r | |
61 | RETURN_STATUS\r | |
62 | EFIAPI\r | |
63 | MceInitialize (\r | |
64 | IN UINTN ProcessorNumber,\r | |
65 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
66 | IN VOID *ConfigData, OPTIONAL\r | |
67 | IN BOOLEAN State\r | |
68 | )\r | |
69 | {\r | |
70 | //\r | |
71 | // Set MCE bit in CR4\r | |
72 | //\r | |
73 | CPU_REGISTER_TABLE_WRITE_FIELD (\r | |
74 | ProcessorNumber,\r | |
75 | ControlRegister,\r | |
76 | 4,\r | |
77 | IA32_CR4,\r | |
78 | Bits.MCE,\r | |
79 | (State) ? 1 : 0\r | |
80 | );\r | |
81 | return RETURN_SUCCESS;\r | |
82 | }\r | |
83 | \r | |
84 | /**\r | |
85 | Detects if Machine Check Architecture feature supported on current processor.\r | |
86 | \r | |
87 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
88 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
89 | structure for the CPU executing this function.\r | |
90 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
91 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
92 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
93 | RegisterCpuFeature().\r | |
94 | \r | |
95 | @retval TRUE Machine Check Architecture feature is supported.\r | |
96 | @retval FALSE Machine Check Architecture feature is not supported.\r | |
97 | \r | |
98 | @note This service could be called by BSP/APs.\r | |
99 | **/\r | |
100 | BOOLEAN\r | |
101 | EFIAPI\r | |
102 | McaSupport (\r | |
103 | IN UINTN ProcessorNumber,\r | |
104 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
105 | IN VOID *ConfigData OPTIONAL\r | |
106 | )\r | |
107 | {\r | |
57d1afc8 SB |
108 | if (!MceSupport (ProcessorNumber, CpuInfo, ConfigData)) {\r |
109 | return FALSE;\r | |
110 | }\r | |
80c4b236 JF |
111 | return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCA == 1);\r |
112 | }\r | |
113 | \r | |
114 | /**\r | |
115 | Initializes Machine Check Architecture feature to specific state.\r | |
116 | \r | |
117 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
118 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
119 | structure for the CPU executing this function.\r | |
120 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
121 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
122 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
123 | RegisterCpuFeature().\r | |
124 | @param[in] State If TRUE, then the Machine Check Architecture feature must be enabled.\r | |
125 | If FALSE, then the Machine Check Architecture feature must be disabled.\r | |
126 | \r | |
127 | @retval RETURN_SUCCESS Machine Check Architecture feature is initialized.\r | |
128 | \r | |
129 | @note This service could be called by BSP only.\r | |
130 | **/\r | |
131 | RETURN_STATUS\r | |
132 | EFIAPI\r | |
133 | McaInitialize (\r | |
134 | IN UINTN ProcessorNumber,\r | |
135 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
136 | IN VOID *ConfigData, OPTIONAL\r | |
137 | IN BOOLEAN State\r | |
138 | )\r | |
139 | {\r | |
140 | MSR_IA32_MCG_CAP_REGISTER McgCap;\r | |
141 | UINT32 BankIndex;\r | |
142 | \r | |
d28daadd ED |
143 | //\r |
144 | // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is core for below processor type, only program\r | |
145 | // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 in each core.\r | |
146 | //\r | |
147 | if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
148 | IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
149 | IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
150 | IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
151 | IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
152 | IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
153 | IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r | |
154 | if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r | |
155 | return RETURN_SUCCESS;\r | |
156 | }\r | |
157 | }\r | |
158 | \r | |
159 | //\r | |
160 | // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is package for below processor type, only program\r | |
161 | // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 core 0 in each package.\r | |
162 | //\r | |
163 | if (IS_NEHALEM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r | |
164 | if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {\r | |
165 | return RETURN_SUCCESS;\r | |
166 | }\r | |
167 | }\r | |
168 | \r | |
e01d92d4 | 169 | if (State) {\r |
dc7363f8 RN |
170 | McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r |
171 | for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {\r | |
80c4b236 JF |
172 | CPU_REGISTER_TABLE_WRITE64 (\r |
173 | ProcessorNumber,\r | |
174 | Msr,\r | |
dc7363f8 RN |
175 | MSR_IA32_MC0_CTL + BankIndex * 4,\r |
176 | MAX_UINT64\r | |
80c4b236 JF |
177 | );\r |
178 | }\r | |
dc7363f8 RN |
179 | \r |
180 | if (PcdGetBool (PcdIsPowerOnReset)) {\r | |
181 | for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {\r | |
182 | CPU_REGISTER_TABLE_WRITE64 (\r | |
183 | ProcessorNumber,\r | |
184 | Msr,\r | |
185 | MSR_IA32_MC0_STATUS + BankIndex * 4,\r | |
186 | 0\r | |
187 | );\r | |
188 | }\r | |
189 | }\r | |
80c4b236 JF |
190 | }\r |
191 | \r | |
192 | return RETURN_SUCCESS;\r | |
193 | }\r | |
194 | \r | |
195 | /**\r | |
196 | Detects if IA32_MCG_CTL feature supported on current processor.\r | |
197 | \r | |
198 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
199 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
200 | structure for the CPU executing this function.\r | |
201 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
202 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
203 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
204 | RegisterCpuFeature().\r | |
205 | \r | |
206 | @retval TRUE IA32_MCG_CTL feature is supported.\r | |
207 | @retval FALSE IA32_MCG_CTL feature is not supported.\r | |
208 | \r | |
209 | @note This service could be called by BSP/APs.\r | |
210 | **/\r | |
211 | BOOLEAN\r | |
212 | EFIAPI\r | |
213 | McgCtlSupport (\r | |
214 | IN UINTN ProcessorNumber,\r | |
215 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
216 | IN VOID *ConfigData OPTIONAL\r | |
217 | )\r | |
218 | {\r | |
219 | MSR_IA32_MCG_CAP_REGISTER McgCap;\r | |
220 | \r | |
221 | if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {\r | |
222 | return FALSE;\r | |
223 | }\r | |
224 | McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r | |
225 | return (McgCap.Bits.MCG_CTL_P == 1);\r | |
226 | }\r | |
227 | \r | |
228 | /**\r | |
229 | Initializes IA32_MCG_CTL feature to specific state.\r | |
230 | \r | |
231 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
232 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
233 | structure for the CPU executing this function.\r | |
234 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
235 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
236 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
237 | RegisterCpuFeature().\r | |
238 | @param[in] State If TRUE, then the IA32_MCG_CTL feature must be enabled.\r | |
239 | If FALSE, then the IA32_MCG_CTL feature must be disabled.\r | |
240 | \r | |
241 | @retval RETURN_SUCCESS IA32_MCG_CTL feature is initialized.\r | |
242 | \r | |
243 | @note This service could be called by BSP only.\r | |
244 | **/\r | |
245 | RETURN_STATUS\r | |
246 | EFIAPI\r | |
247 | McgCtlInitialize (\r | |
248 | IN UINTN ProcessorNumber,\r | |
249 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
250 | IN VOID *ConfigData, OPTIONAL\r | |
251 | IN BOOLEAN State\r | |
252 | )\r | |
253 | {\r | |
254 | CPU_REGISTER_TABLE_WRITE64 (\r | |
255 | ProcessorNumber,\r | |
256 | Msr,\r | |
257 | MSR_IA32_MCG_CTL,\r | |
258 | (State)? MAX_UINT64 : 0\r | |
259 | );\r | |
260 | return RETURN_SUCCESS;\r | |
261 | }\r | |
262 | \r | |
306a5bcc | 263 | /**\r |
7367cc6c | 264 | Detects if Local machine check exception feature supported on current\r |
306a5bcc ED |
265 | processor.\r |
266 | \r | |
267 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
268 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
269 | structure for the CPU executing this function.\r | |
270 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
271 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
272 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
273 | RegisterCpuFeature().\r | |
274 | \r | |
275 | @retval TRUE Local machine check exception feature is supported.\r | |
276 | @retval FALSE Local machine check exception feature is not supported.\r | |
277 | \r | |
278 | @note This service could be called by BSP/APs.\r | |
279 | **/\r | |
280 | BOOLEAN\r | |
281 | EFIAPI\r | |
282 | LmceSupport (\r | |
283 | IN UINTN ProcessorNumber,\r | |
284 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
285 | IN VOID *ConfigData OPTIONAL\r | |
286 | )\r | |
287 | {\r | |
288 | MSR_IA32_MCG_CAP_REGISTER McgCap;\r | |
289 | \r | |
290 | if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {\r | |
291 | return FALSE;\r | |
292 | }\r | |
293 | \r | |
294 | McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r | |
295 | if (ProcessorNumber == 0) {\r | |
296 | DEBUG ((EFI_D_INFO, "LMCE eanble = %x\n", (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0)));\r | |
297 | }\r | |
298 | return (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0);\r | |
299 | }\r | |
300 | \r | |
301 | /**\r | |
302 | Initializes Local machine check exception feature to specific state.\r | |
303 | \r | |
304 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
305 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
306 | structure for the CPU executing this function.\r | |
307 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
308 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
309 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
310 | RegisterCpuFeature().\r | |
311 | @param[in] State If TRUE, then the Local machine check exception\r | |
312 | feature must be enabled.\r | |
313 | If FALSE, then the Local machine check exception\r | |
314 | feature must be disabled.\r | |
315 | \r | |
316 | @retval RETURN_SUCCESS Local machine check exception feature is initialized.\r | |
317 | \r | |
318 | **/\r | |
319 | RETURN_STATUS\r | |
320 | EFIAPI\r | |
321 | LmceInitialize (\r | |
322 | IN UINTN ProcessorNumber,\r | |
323 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
324 | IN VOID *ConfigData, OPTIONAL\r | |
325 | IN BOOLEAN State\r | |
326 | )\r | |
327 | {\r | |
328 | MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister;\r | |
329 | \r | |
d28daadd | 330 | //\r |
2b0c1994 | 331 | // The scope of FastStrings bit in the MSR_IA32_MISC_ENABLE is core for below processor type, only program\r |
d28daadd ED |
332 | // MSR_IA32_MISC_ENABLE for thread 0 in each core.\r |
333 | //\r | |
334 | if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
335 | IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
336 | IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r | |
337 | if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r | |
338 | return RETURN_SUCCESS;\r | |
339 | }\r | |
340 | }\r | |
341 | \r | |
306a5bcc ED |
342 | ASSERT (ConfigData != NULL);\r |
343 | MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;\r | |
344 | if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {\r | |
345 | CPU_REGISTER_TABLE_WRITE_FIELD (\r | |
346 | ProcessorNumber,\r | |
347 | Msr,\r | |
348 | MSR_IA32_FEATURE_CONTROL,\r | |
349 | MSR_IA32_FEATURE_CONTROL_REGISTER,\r | |
350 | Bits.LmceOn,\r | |
351 | (State) ? 1 : 0\r | |
352 | );\r | |
353 | }\r | |
354 | return RETURN_SUCCESS;\r | |
355 | }\r |