[mirror_edk2.git] / UefiCpuPkg / Library / CpuExceptionHandlerLib / UnitTest / Ia32 / ArchExceptionHandlerTestAsm.nasm

;------------------------------------------------------------------------------\r
;\r
; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;\r
;   ArchExceptionHandlerTestAsm.nasm\r
;\r
; Abstract:\r
;\r
;   ia32 CPU Exception Handler Lib Unit test\r
;\r
;------------------------------------------------------------------------------\r
\r
    SECTION .text\r
\r
struc GENERAL_REGISTER_IA32\r
  .Edi:    resd    1\r
  .Esi:    resd    1\r
  .Ebx:    resd    1\r
  .Edx:    resd    1\r
  .Ecx:    resd    1\r
  .Eax:    resd    1\r
\r
endstruc\r
\r
extern ASM_PFX(mExpectedContextInHandler)\r
extern ASM_PFX(mActualContextAfterException)\r
extern ASM_PFX(mFaultInstructionLength)\r
\r
;------------------------------------------------------------------------------\r
; VOID\r
; EFIAPI\r
; TriggerGPException (\r
;  UINTN  Cr4ReservedBit\r
;  );\r
;------------------------------------------------------------------------------\r
global ASM_PFX(TriggerGPException)\r
ASM_PFX(TriggerGPException):\r
    ;\r
    ; Set reserved bit 15 of cr4 to 1\r
    ;\r
    lea  ecx, [ASM_PFX(mFaultInstructionLength)]\r
    mov  dword[ecx], TriggerGPExceptionAfter - TriggerGPExceptionBefore\r
    mov  ecx, dword [esp + 0x4]\r
TriggerGPExceptionBefore:\r
    mov  cr4, ecx\r
TriggerGPExceptionAfter:\r
    ret\r
\r
;------------------------------------------------------------------------------\r
; VOID\r
; EFIAPI\r
; TriggerPFException (\r
;  UINTN  PfAddress\r
;  );\r
;------------------------------------------------------------------------------\r
global ASM_PFX(TriggerPFException)\r
ASM_PFX(TriggerPFException):\r
    lea  ecx, [ASM_PFX(mFaultInstructionLength)]\r
    mov  dword[ecx], TriggerPFExceptionAfter - TriggerPFExceptionBefore\r
    mov  ecx, dword [esp + 0x4]\r
TriggerPFExceptionBefore:\r
    mov  dword[ecx], 0x1\r
TriggerPFExceptionAfter:\r
    ret\r
\r
;------------------------------------------------------------------------------\r
; ModifyEcxInGlobalBeforeException;\r
; This function is writed by assebly code because it's only called in this file.\r
; It's used to set Ecx in mExpectedContextInHandler for different exception.\r
;------------------------------------------------------------------------------\r
global ASM_PFX(ModifyEcxInGlobalBeforeException)\r
ASM_PFX(ModifyEcxInGlobalBeforeException):\r
    push eax\r
    lea  eax, [ASM_PFX(mExpectedContextInHandler)]\r
    mov  [eax + GENERAL_REGISTER_IA32.Ecx], ecx\r
    pop  eax\r
    ret\r
\r
;------------------------------------------------------------------------------\r
;VOID\r
;EFIAPI\r
;AsmTestConsistencyOfCpuContext (\r
;  IN  EFI_EXCEPTION_TYPE ExceptionType\r
;  IN  UINTN              FaultParameter   OPTIONAL\r
;  );\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmTestConsistencyOfCpuContext)\r
ASM_PFX(AsmTestConsistencyOfCpuContext):\r
    ;\r
    ; push 7 general register plus 4 bytes\r
    ;\r
    pushad\r
\r
    ;\r
    ; Modify register to mExpectedContextInHandler. Do not handle Esp and Ebp.\r
    ; CpuExceptionHandlerLib doesn't set Esp and Esp register to the value in SystemContext.\r
    ;\r
    lea eax, [ASM_PFX(mExpectedContextInHandler)]\r
    mov edi, [eax + GENERAL_REGISTER_IA32.Edi]\r
    mov esi, [eax + GENERAL_REGISTER_IA32.Esi]\r
    mov ebx, [eax + GENERAL_REGISTER_IA32.Ebx]\r
    mov edx, [eax + GENERAL_REGISTER_IA32.Edx]\r
    ;\r
    ; Set ecx to ExceptionType\r
    ;\r
    mov ecx, dword [esp + 0x24]\r
    mov eax, [eax + GENERAL_REGISTER_IA32.Eax]\r
\r
    cmp  ecx, 0xd\r
    jz   GPException\r
    cmp  ecx, 0xe\r
    jz   PFException\r
    jmp  INTnException\r
\r
PFException:\r
    mov  ecx, dword [esp + 0x28]                    ; Set ecx to PFAddress.\r
    call ASM_PFX(ModifyEcxInGlobalBeforeException)  ; Set mExpectedContextInHandler.Ecx to PFAddress.\r
    push ecx                                        ; Push PfAddress into stack.\r
    call ASM_PFX(TriggerPFException)\r
    jmp  AfterException\r
\r
GPException:\r
    mov  ecx, dword [esp + 0x28]                    ; Set ecx to CR4_RESERVED_BIT.\r
    call ASM_PFX(ModifyEcxInGlobalBeforeException)  ; Set mExpectedContextInHandler.Ecx to CR4_RESERVED_BIT.\r
    push ecx                                        ; Push CR4_RESERVED_BIT into stack.\r
    call ASM_PFX(TriggerGPException)\r
    jmp  AfterException\r
\r
INTnException:\r
    call ASM_PFX(ModifyEcxInGlobalBeforeException)  ; Set mExpectedContextInHandler.Ecx to ExceptionType.\r
    push ecx                                        ; Push ExceptionType into stack.\r
    call ASM_PFX(TriggerINTnException)\r
\r
AfterException:\r
    ;\r
    ; Save register in mActualContextAfterException.\r
    ;\r
    push eax\r
    lea  eax, [ASM_PFX(mActualContextAfterException)]\r
    mov  [eax + GENERAL_REGISTER_IA32.Edi], edi\r
    mov  [eax + GENERAL_REGISTER_IA32.Esi], esi\r
    mov  [eax + GENERAL_REGISTER_IA32.Ebx], ebx\r
    mov  [eax + GENERAL_REGISTER_IA32.Edx], edx\r
    mov  [eax + GENERAL_REGISTER_IA32.Ecx], ecx\r
    pop  ecx\r
    mov  [eax + GENERAL_REGISTER_IA32.Eax], ecx\r
    add  esp, 4\r
\r
    ;\r
    ; restore original register\r
    ;\r
    popad\r
    ret\r
\r
;------------------------------------------------------------------------------\r
; VOID\r
; EFIAPI\r
; TriggerStackOverflow (\r
;  VOID\r
;  );\r
;------------------------------------------------------------------------------\r
global ASM_PFX(TriggerStackOverflow)\r
ASM_PFX(TriggerStackOverflow):\r
    lea  ecx, [ASM_PFX(mFaultInstructionLength)]\r
    mov  dword[ecx], TriggerCpuStackGuardAfter - TriggerCpuStackGuardBefore\r
TriggerCpuStackGuardBefore:\r
    ;\r
    ; Clear CR0.TS since it is set after return from a nested DF\r
    ;\r
    call TriggerCpuStackGuardBefore\r
    clts\r
TriggerCpuStackGuardAfter:\r
    ret\r
\r
;------------------------------------------------------------------------------\r
; VOID\r
; EFIAPI\r
; TriggerINTnException (\r
;  IN  EFI_EXCEPTION_TYPE ExceptionType\r
;  );\r
;------------------------------------------------------------------------------\r
global ASM_PFX(TriggerINTnException)\r
ASM_PFX(TriggerINTnException):\r
    push eax\r
    push edx\r
    lea  eax, [AsmTriggerException1 - AsmTriggerException0]\r
    mov  ecx, dword [esp + 0xc]\r
    push ecx\r
    mul  ecx\r
    mov  ecx, AsmTriggerException0\r
    add  eax, ecx\r
    pop  ecx\r
    pop  edx\r
    jmp  eax\r
    ;\r
    ; eax = AsmTriggerException0 + (AsmTriggerException1 - AsmTriggerException0) * ecx\r
    ;\r
%assign Vector 0\r
%rep  22\r
AsmTriggerException %+ Vector:\r
    pop eax\r
    INT Vector\r
    ret\r
%assign Vector Vector+1\r
%endrep\r
Commit	Line	Data
055eaacc TD	1	;------------------------------------------------------------------------------\r
	2	;\r
	3	; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>\r
	4	; SPDX-License-Identifier: BSD-2-Clause-Patent\r
	5	;\r
	6	; Module Name:\r
	7	;\r
	8	; ArchExceptionHandlerTestAsm.nasm\r
	9	;\r
	10	; Abstract:\r
	11	;\r
	12	; ia32 CPU Exception Handler Lib Unit test\r
	13	;\r
	14	;------------------------------------------------------------------------------\r
	15	\r
	16	SECTION .text\r
	17	\r
	18	struc GENERAL_REGISTER_IA32\r
	19	.Edi: resd 1\r
	20	.Esi: resd 1\r
	21	.Ebx: resd 1\r
	22	.Edx: resd 1\r
	23	.Ecx: resd 1\r
	24	.Eax: resd 1\r
	25	\r
	26	endstruc\r
	27	\r
	28	extern ASM_PFX(mExpectedContextInHandler)\r
	29	extern ASM_PFX(mActualContextAfterException)\r
	30	extern ASM_PFX(mFaultInstructionLength)\r
	31	\r
	32	;------------------------------------------------------------------------------\r
	33	; VOID\r
	34	; EFIAPI\r
	35	; TriggerGPException (\r
	36	; UINTN Cr4ReservedBit\r
	37	; );\r
	38	;------------------------------------------------------------------------------\r
	39	global ASM_PFX(TriggerGPException)\r
	40	ASM_PFX(TriggerGPException):\r
	41	;\r
	42	; Set reserved bit 15 of cr4 to 1\r
	43	;\r
	44	lea ecx, [ASM_PFX(mFaultInstructionLength)]\r
	45	mov dword[ecx], TriggerGPExceptionAfter - TriggerGPExceptionBefore\r
	46	mov ecx, dword [esp + 0x4]\r
	47	TriggerGPExceptionBefore:\r
	48	mov cr4, ecx\r
	49	TriggerGPExceptionAfter:\r
	50	ret\r
	51	\r
	52	;------------------------------------------------------------------------------\r
	53	; VOID\r
	54	; EFIAPI\r
	55	; TriggerPFException (\r
	56	; UINTN PfAddress\r
	57	; );\r
	58	;------------------------------------------------------------------------------\r
	59	global ASM_PFX(TriggerPFException)\r
	60	ASM_PFX(TriggerPFException):\r
	61	lea ecx, [ASM_PFX(mFaultInstructionLength)]\r
	62	mov dword[ecx], TriggerPFExceptionAfter - TriggerPFExceptionBefore\r
	63	mov ecx, dword [esp + 0x4]\r
	64	TriggerPFExceptionBefore:\r
65	mov dword[ecx], 0x1\r
66	TriggerPFExceptionAfter:\r
67	ret\r
68	\r
69	;------------------------------------------------------------------------------\r
70	; ModifyEcxInGlobalBeforeException;\r
71	; This function is writed by assebly code because it's only called in this file.\r
72	; It's used to set Ecx in mExpectedContextInHandler for different exception.\r
73	;------------------------------------------------------------------------------\r
74	global ASM_PFX(ModifyEcxInGlobalBeforeException)\r
75	ASM_PFX(ModifyEcxInGlobalBeforeException):\r
76	push eax\r
77	lea eax, [ASM_PFX(mExpectedContextInHandler)]\r
78	mov [eax + GENERAL_REGISTER_IA32.Ecx], ecx\r
79	pop eax\r
80	ret\r
81	\r
82	;------------------------------------------------------------------------------\r
83	;VOID\r
84	;EFIAPI\r
85	;AsmTestConsistencyOfCpuContext (\r
86	; IN EFI_EXCEPTION_TYPE ExceptionType\r
87	; IN UINTN FaultParameter OPTIONAL\r
88	; );\r
89	;------------------------------------------------------------------------------\r
90	global ASM_PFX(AsmTestConsistencyOfCpuContext)\r
91	ASM_PFX(AsmTestConsistencyOfCpuContext):\r
92	;\r
93	; push 7 general register plus 4 bytes\r
94	;\r
95	pushad\r
96	\r
97	;\r
98	; Modify register to mExpectedContextInHandler. Do not handle Esp and Ebp.\r
99	; CpuExceptionHandlerLib doesn't set Esp and Esp register to the value in SystemContext.\r
100	;\r
101	lea eax, [ASM_PFX(mExpectedContextInHandler)]\r
102	mov edi, [eax + GENERAL_REGISTER_IA32.Edi]\r
103	mov esi, [eax + GENERAL_REGISTER_IA32.Esi]\r
104	mov ebx, [eax + GENERAL_REGISTER_IA32.Ebx]\r
105	mov edx, [eax + GENERAL_REGISTER_IA32.Edx]\r
106	;\r
107	; Set ecx to ExceptionType\r
108	;\r
109	mov ecx, dword [esp + 0x24]\r
110	mov eax, [eax + GENERAL_REGISTER_IA32.Eax]\r
111	\r
112	cmp ecx, 0xd\r
113	jz GPException\r
114	cmp ecx, 0xe\r
115	jz PFException\r
116	jmp INTnException\r
117	\r
118	PFException:\r
119	mov ecx, dword [esp + 0x28] ; Set ecx to PFAddress.\r
120	call ASM_PFX(ModifyEcxInGlobalBeforeException) ; Set mExpectedContextInHandler.Ecx to PFAddress.\r
121	push ecx ; Push PfAddress into stack.\r
122	call ASM_PFX(TriggerPFException)\r
123	jmp AfterException\r
124	\r
125	GPException:\r
126	mov ecx, dword [esp + 0x28] ; Set ecx to CR4_RESERVED_BIT.\r
127	call ASM_PFX(ModifyEcxInGlobalBeforeException) ; Set mExpectedContextInHandler.Ecx to CR4_RESERVED_BIT.\r
128	push ecx ; Push CR4_RESERVED_BIT into stack.\r
129	call ASM_PFX(TriggerGPException)\r
130	jmp AfterException\r
131	\r
132	INTnException:\r
133	call ASM_PFX(ModifyEcxInGlobalBeforeException) ; Set mExpectedContextInHandler.Ecx to ExceptionType.\r
134	push ecx ; Push ExceptionType into stack.\r
135	call ASM_PFX(TriggerINTnException)\r
136	\r
137	AfterException:\r
138	;\r
139	; Save register in mActualContextAfterException.\r
140	;\r
141	push eax\r
142	lea eax, [ASM_PFX(mActualContextAfterException)]\r
143	mov [eax + GENERAL_REGISTER_IA32.Edi], edi\r
144	mov [eax + GENERAL_REGISTER_IA32.Esi], esi\r
145	mov [eax + GENERAL_REGISTER_IA32.Ebx], ebx\r
146	mov [eax + GENERAL_REGISTER_IA32.Edx], edx\r
147	mov [eax + GENERAL_REGISTER_IA32.Ecx], ecx\r
148	pop ecx\r
149	mov [eax + GENERAL_REGISTER_IA32.Eax], ecx\r
150	add esp, 4\r
151	\r
152	;\r
153	; restore original register\r
154	;\r
155	popad\r
156	ret\r
157	\r
158	;------------------------------------------------------------------------------\r
159	; VOID\r
160	; EFIAPI\r
161	; TriggerStackOverflow (\r
162	; VOID\r
163	; );\r
164	;------------------------------------------------------------------------------\r
165	global ASM_PFX(TriggerStackOverflow)\r
166	ASM_PFX(TriggerStackOverflow):\r
167	lea ecx, [ASM_PFX(mFaultInstructionLength)]\r
168	mov dword[ecx], TriggerCpuStackGuardAfter - TriggerCpuStackGuardBefore\r
169	TriggerCpuStackGuardBefore:\r
170	;\r
171	; Clear CR0.TS since it is set after return from a nested DF\r
172	;\r
173	call TriggerCpuStackGuardBefore\r
174	clts\r
175	TriggerCpuStackGuardAfter:\r
176	ret\r
177	\r
178	;------------------------------------------------------------------------------\r
179	; VOID\r
180	; EFIAPI\r
181	; TriggerINTnException (\r
182	; IN EFI_EXCEPTION_TYPE ExceptionType\r
183	; );\r
184	;------------------------------------------------------------------------------\r
185	global ASM_PFX(TriggerINTnException)\r
186	ASM_PFX(TriggerINTnException):\r
187	push eax\r
188	push edx\r
189	lea eax, [AsmTriggerException1 - AsmTriggerException0]\r
190	mov ecx, dword [esp + 0xc]\r
191	push ecx\r
192	mul ecx\r
193	mov ecx, AsmTriggerException0\r
194	add eax, ecx\r
195	pop ecx\r
196	pop edx\r
197	jmp eax\r
198	;\r
199	; eax = AsmTriggerException0 + (AsmTriggerException1 - AsmTriggerException0) * ecx\r
200	;\r
201	%assign Vector 0\r
202	%rep 22\r
203	AsmTriggerException %+ Vector:\r
204	pop eax\r
205	INT Vector\r
206	ret\r
207	%assign Vector Vector+1\r
208	%endrep\r