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529a5a86 MK |
1 | /** @file\r |
2 | Enable SMM profile.\r | |
3 | \r | |
3eb69b08 | 4 | Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>\r |
241f9149 LD |
5 | Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r |
6 | \r | |
0acd8697 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
529a5a86 MK |
8 | \r |
9 | **/\r | |
10 | \r | |
11 | #include "PiSmmCpuDxeSmm.h"\r | |
12 | #include "SmmProfileInternal.h"\r | |
13 | \r | |
14 | UINT32 mSmmProfileCr3;\r | |
15 | \r | |
16 | SMM_PROFILE_HEADER *mSmmProfileBase;\r | |
17 | MSR_DS_AREA_STRUCT *mMsrDsAreaBase;\r | |
18 | //\r | |
19 | // The buffer to store SMM profile data.\r | |
20 | //\r | |
21 | UINTN mSmmProfileSize;\r | |
22 | \r | |
23 | //\r | |
24 | // The buffer to enable branch trace store.\r | |
25 | //\r | |
26 | UINTN mMsrDsAreaSize = SMM_PROFILE_DTS_SIZE;\r | |
27 | \r | |
3c5ce64f LE |
28 | //\r |
29 | // The flag indicates if execute-disable is supported by processor.\r | |
30 | //\r | |
31 | BOOLEAN mXdSupported = TRUE;\r | |
32 | \r | |
529a5a86 MK |
33 | //\r |
34 | // The flag indicates if execute-disable is enabled on processor.\r | |
35 | //\r | |
36 | BOOLEAN mXdEnabled = FALSE;\r | |
37 | \r | |
38 | //\r | |
39 | // The flag indicates if BTS is supported by processor.\r | |
40 | //\r | |
a46a4c90 | 41 | BOOLEAN mBtsSupported = TRUE;\r |
529a5a86 MK |
42 | \r |
43 | //\r | |
44 | // The flag indicates if SMM profile starts to record data.\r | |
45 | //\r | |
46 | BOOLEAN mSmmProfileStart = FALSE;\r | |
47 | \r | |
09afd9a4 JW |
48 | //\r |
49 | // The flag indicates if #DB will be setup in #PF handler.\r | |
50 | //\r | |
51 | BOOLEAN mSetupDebugTrap = FALSE;\r | |
52 | \r | |
529a5a86 MK |
53 | //\r |
54 | // Record the page fault exception count for one instruction execution.\r | |
55 | //\r | |
56 | UINTN *mPFEntryCount;\r | |
57 | \r | |
58 | UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];\r | |
59 | UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];\r | |
60 | \r | |
61 | MSR_DS_AREA_STRUCT **mMsrDsArea;\r | |
62 | BRANCH_TRACE_RECORD **mMsrBTSRecord;\r | |
63 | UINTN mBTSRecordNumber;\r | |
64 | PEBS_RECORD **mMsrPEBSRecord;\r | |
65 | \r | |
66 | //\r | |
67 | // These memory ranges are always present, they does not generate the access type of page fault exception,\r | |
68 | // but they possibly generate instruction fetch type of page fault exception.\r | |
69 | //\r | |
70 | MEMORY_PROTECTION_RANGE *mProtectionMemRange = NULL;\r | |
71 | UINTN mProtectionMemRangeCount = 0;\r | |
72 | \r | |
73 | //\r | |
74 | // Some predefined memory ranges.\r | |
75 | //\r | |
76 | MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = {\r | |
77 | //\r | |
78 | // SMRAM range (to be fixed in runtime).\r | |
79 | // It is always present and instruction fetches are allowed.\r | |
80 | //\r | |
81 | {{0x00000000, 0x00000000},TRUE,FALSE},\r | |
82 | \r | |
83 | //\r | |
84 | // SMM profile data range( to be fixed in runtime).\r | |
85 | // It is always present and instruction fetches are not allowed.\r | |
86 | //\r | |
87 | {{0x00000000, 0x00000000},TRUE,TRUE},\r | |
88 | \r | |
ee584389 JF |
89 | //\r |
90 | // SMRAM ranges not covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz (to be fixed in runtime).\r | |
91 | // It is always present and instruction fetches are allowed.\r | |
92 | // {{0x00000000, 0x00000000},TRUE,FALSE},\r | |
93 | //\r | |
94 | \r | |
529a5a86 MK |
95 | //\r |
96 | // Future extended range could be added here.\r | |
97 | //\r | |
98 | \r | |
99 | //\r | |
100 | // PCI MMIO ranges (to be added in runtime).\r | |
101 | // They are always present and instruction fetches are not allowed.\r | |
102 | //\r | |
103 | };\r | |
104 | \r | |
105 | //\r | |
106 | // These memory ranges are mapped by 4KB-page instead of 2MB-page.\r | |
107 | //\r | |
108 | MEMORY_RANGE *mSplitMemRange = NULL;\r | |
109 | UINTN mSplitMemRangeCount = 0;\r | |
110 | \r | |
111 | //\r | |
112 | // SMI command port.\r | |
113 | //\r | |
114 | UINT32 mSmiCommandPort;\r | |
115 | \r | |
116 | /**\r | |
117 | Disable branch trace store.\r | |
118 | \r | |
119 | **/\r | |
120 | VOID\r | |
121 | DisableBTS (\r | |
122 | VOID\r | |
123 | )\r | |
124 | {\r | |
125 | AsmMsrAnd64 (MSR_DEBUG_CTL, ~((UINT64)(MSR_DEBUG_CTL_BTS | MSR_DEBUG_CTL_TR)));\r | |
126 | }\r | |
127 | \r | |
128 | /**\r | |
129 | Enable branch trace store.\r | |
130 | \r | |
131 | **/\r | |
132 | VOID\r | |
133 | EnableBTS (\r | |
134 | VOID\r | |
135 | )\r | |
136 | {\r | |
137 | AsmMsrOr64 (MSR_DEBUG_CTL, (MSR_DEBUG_CTL_BTS | MSR_DEBUG_CTL_TR));\r | |
138 | }\r | |
139 | \r | |
140 | /**\r | |
141 | Get CPU Index from APIC ID.\r | |
142 | \r | |
143 | **/\r | |
144 | UINTN\r | |
145 | GetCpuIndex (\r | |
146 | VOID\r | |
147 | )\r | |
148 | {\r | |
149 | UINTN Index;\r | |
150 | UINT32 ApicId;\r | |
151 | \r | |
152 | ApicId = GetApicId ();\r | |
153 | \r | |
bb767506 | 154 | for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r |
529a5a86 MK |
155 | if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == ApicId) {\r |
156 | return Index;\r | |
157 | }\r | |
158 | }\r | |
159 | ASSERT (FALSE);\r | |
160 | return 0;\r | |
161 | }\r | |
162 | \r | |
163 | /**\r | |
164 | Get the source of IP after execute-disable exception is triggered.\r | |
165 | \r | |
166 | @param CpuIndex The index of CPU.\r | |
167 | @param DestinationIP The destination address.\r | |
168 | \r | |
169 | **/\r | |
170 | UINT64\r | |
171 | GetSourceFromDestinationOnBts (\r | |
172 | UINTN CpuIndex,\r | |
173 | UINT64 DestinationIP\r | |
174 | )\r | |
175 | {\r | |
176 | BRANCH_TRACE_RECORD *CurrentBTSRecord;\r | |
177 | UINTN Index;\r | |
178 | BOOLEAN FirstMatch;\r | |
179 | \r | |
180 | FirstMatch = FALSE;\r | |
181 | \r | |
182 | CurrentBTSRecord = (BRANCH_TRACE_RECORD *)mMsrDsArea[CpuIndex]->BTSIndex;\r | |
183 | for (Index = 0; Index < mBTSRecordNumber; Index++) {\r | |
184 | if ((UINTN)CurrentBTSRecord < (UINTN)mMsrBTSRecord[CpuIndex]) {\r | |
185 | //\r | |
186 | // Underflow\r | |
187 | //\r | |
188 | CurrentBTSRecord = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[CpuIndex]->BTSAbsoluteMaximum - 1);\r | |
189 | CurrentBTSRecord --;\r | |
190 | }\r | |
191 | if (CurrentBTSRecord->LastBranchTo == DestinationIP) {\r | |
192 | //\r | |
193 | // Good! find 1st one, then find 2nd one.\r | |
194 | //\r | |
195 | if (!FirstMatch) {\r | |
196 | //\r | |
197 | // The first one is DEBUG exception\r | |
198 | //\r | |
199 | FirstMatch = TRUE;\r | |
200 | } else {\r | |
201 | //\r | |
202 | // Good find proper one.\r | |
203 | //\r | |
204 | return CurrentBTSRecord->LastBranchFrom;\r | |
205 | }\r | |
206 | }\r | |
207 | CurrentBTSRecord--;\r | |
208 | }\r | |
209 | \r | |
210 | return 0;\r | |
211 | }\r | |
212 | \r | |
213 | /**\r | |
214 | SMM profile specific INT 1 (single-step) exception handler.\r | |
215 | \r | |
216 | @param InterruptType Defines the type of interrupt or exception that\r | |
217 | occurred on the processor.This parameter is processor architecture specific.\r | |
218 | @param SystemContext A pointer to the processor context when\r | |
219 | the interrupt occurred on the processor.\r | |
220 | **/\r | |
221 | VOID\r | |
222 | EFIAPI\r | |
223 | DebugExceptionHandler (\r | |
224 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
225 | IN EFI_SYSTEM_CONTEXT SystemContext\r | |
226 | )\r | |
227 | {\r | |
228 | UINTN CpuIndex;\r | |
229 | UINTN PFEntry;\r | |
230 | \r | |
09afd9a4 JW |
231 | if (!mSmmProfileStart &&\r |
232 | !HEAP_GUARD_NONSTOP_MODE &&\r | |
233 | !NULL_DETECTION_NONSTOP_MODE) {\r | |
529a5a86 MK |
234 | return;\r |
235 | }\r | |
236 | CpuIndex = GetCpuIndex ();\r | |
237 | \r | |
238 | //\r | |
239 | // Clear last PF entries\r | |
240 | //\r | |
241 | for (PFEntry = 0; PFEntry < mPFEntryCount[CpuIndex]; PFEntry++) {\r | |
242 | *mLastPFEntryPointer[CpuIndex][PFEntry] = mLastPFEntryValue[CpuIndex][PFEntry];\r | |
243 | }\r | |
244 | \r | |
245 | //\r | |
246 | // Reset page fault exception count for next page fault.\r | |
247 | //\r | |
248 | mPFEntryCount[CpuIndex] = 0;\r | |
249 | \r | |
250 | //\r | |
251 | // Flush TLB\r | |
252 | //\r | |
253 | CpuFlushTlb ();\r | |
254 | \r | |
255 | //\r | |
256 | // Clear TF in EFLAGS\r | |
257 | //\r | |
258 | ClearTrapFlag (SystemContext);\r | |
259 | }\r | |
260 | \r | |
97f1061e JF |
261 | /**\r |
262 | Check if the input address is in SMM ranges.\r | |
263 | \r | |
264 | @param[in] Address The input address.\r | |
265 | \r | |
266 | @retval TRUE The input address is in SMM.\r | |
267 | @retval FALSE The input address is not in SMM.\r | |
268 | **/\r | |
269 | BOOLEAN\r | |
270 | IsInSmmRanges (\r | |
271 | IN EFI_PHYSICAL_ADDRESS Address\r | |
272 | )\r | |
273 | {\r | |
274 | UINTN Index;\r | |
275 | \r | |
29dc8aa8 | 276 | if ((Address >= mCpuHotPlugData.SmrrBase) && (Address < mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {\r |
97f1061e JF |
277 | return TRUE;\r |
278 | }\r | |
279 | for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {\r | |
280 | if (Address >= mSmmCpuSmramRanges[Index].CpuStart &&\r | |
281 | Address < mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) {\r | |
282 | return TRUE;\r | |
283 | }\r | |
284 | }\r | |
285 | return FALSE;\r | |
286 | }\r | |
287 | \r | |
529a5a86 MK |
288 | /**\r |
289 | Check if the memory address will be mapped by 4KB-page.\r | |
290 | \r | |
291 | @param Address The address of Memory.\r | |
292 | @param Nx The flag indicates if the memory is execute-disable.\r | |
293 | \r | |
294 | **/\r | |
295 | BOOLEAN\r | |
296 | IsAddressValid (\r | |
297 | IN EFI_PHYSICAL_ADDRESS Address,\r | |
298 | IN BOOLEAN *Nx\r | |
299 | )\r | |
300 | {\r | |
301 | UINTN Index;\r | |
302 | \r | |
529a5a86 MK |
303 | if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r |
304 | //\r | |
305 | // Check configuration\r | |
306 | //\r | |
307 | for (Index = 0; Index < mProtectionMemRangeCount; Index++) {\r | |
308 | if ((Address >= mProtectionMemRange[Index].Range.Base) && (Address < mProtectionMemRange[Index].Range.Top)) {\r | |
309 | *Nx = mProtectionMemRange[Index].Nx;\r | |
310 | return mProtectionMemRange[Index].Present;\r | |
311 | }\r | |
312 | }\r | |
313 | *Nx = TRUE;\r | |
314 | return FALSE;\r | |
315 | \r | |
316 | } else {\r | |
97f1061e JF |
317 | *Nx = TRUE;\r |
318 | if (IsInSmmRanges (Address)) {\r | |
319 | *Nx = FALSE;\r | |
529a5a86 MK |
320 | }\r |
321 | return TRUE;\r | |
322 | }\r | |
323 | }\r | |
324 | \r | |
325 | /**\r | |
326 | Check if the memory address will be mapped by 4KB-page.\r | |
327 | \r | |
328 | @param Address The address of Memory.\r | |
329 | \r | |
330 | **/\r | |
331 | BOOLEAN\r | |
332 | IsAddressSplit (\r | |
333 | IN EFI_PHYSICAL_ADDRESS Address\r | |
334 | )\r | |
335 | {\r | |
336 | UINTN Index;\r | |
337 | \r | |
338 | if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r | |
339 | //\r | |
340 | // Check configuration\r | |
341 | //\r | |
342 | for (Index = 0; Index < mSplitMemRangeCount; Index++) {\r | |
343 | if ((Address >= mSplitMemRange[Index].Base) && (Address < mSplitMemRange[Index].Top)) {\r | |
344 | return TRUE;\r | |
345 | }\r | |
346 | }\r | |
347 | } else {\r | |
348 | if (Address < mCpuHotPlugData.SmrrBase) {\r | |
349 | if ((mCpuHotPlugData.SmrrBase - Address) < BASE_2MB) {\r | |
350 | return TRUE;\r | |
351 | }\r | |
352 | } else if (Address > (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize - BASE_2MB)) {\r | |
353 | if ((Address - (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize - BASE_2MB)) < BASE_2MB) {\r | |
354 | return TRUE;\r | |
355 | }\r | |
356 | }\r | |
357 | }\r | |
358 | //\r | |
359 | // Return default\r | |
360 | //\r | |
361 | return FALSE;\r | |
362 | }\r | |
363 | \r | |
364 | /**\r | |
365 | Initialize the protected memory ranges and the 4KB-page mapped memory ranges.\r | |
366 | \r | |
367 | **/\r | |
368 | VOID\r | |
369 | InitProtectedMemRange (\r | |
370 | VOID\r | |
371 | )\r | |
372 | {\r | |
373 | UINTN Index;\r | |
374 | UINTN NumberOfDescriptors;\r | |
ee584389 | 375 | UINTN NumberOfAddedDescriptors;\r |
529a5a86 MK |
376 | UINTN NumberOfProtectRange;\r |
377 | UINTN NumberOfSpliteRange;\r | |
378 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r | |
379 | UINTN TotalSize;\r | |
529a5a86 MK |
380 | EFI_PHYSICAL_ADDRESS ProtectBaseAddress;\r |
381 | EFI_PHYSICAL_ADDRESS ProtectEndAddress;\r | |
382 | EFI_PHYSICAL_ADDRESS Top2MBAlignedAddress;\r | |
383 | EFI_PHYSICAL_ADDRESS Base2MBAlignedAddress;\r | |
384 | UINT64 High4KBPageSize;\r | |
385 | UINT64 Low4KBPageSize;\r | |
386 | \r | |
387 | NumberOfDescriptors = 0;\r | |
ee584389 | 388 | NumberOfAddedDescriptors = mSmmCpuSmramRangeCount;\r |
529a5a86 MK |
389 | NumberOfSpliteRange = 0;\r |
390 | MemorySpaceMap = NULL;\r | |
391 | \r | |
392 | //\r | |
393 | // Get MMIO ranges from GCD and add them into protected memory ranges.\r | |
394 | //\r | |
dc0a7143 LE |
395 | gDS->GetMemorySpaceMap (\r |
396 | &NumberOfDescriptors,\r | |
397 | &MemorySpaceMap\r | |
398 | );\r | |
529a5a86 MK |
399 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r |
400 | if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) {\r | |
ee584389 | 401 | NumberOfAddedDescriptors++;\r |
529a5a86 MK |
402 | }\r |
403 | }\r | |
404 | \r | |
ee584389 JF |
405 | if (NumberOfAddedDescriptors != 0) {\r |
406 | TotalSize = NumberOfAddedDescriptors * sizeof (MEMORY_PROTECTION_RANGE) + sizeof (mProtectionMemRangeTemplate);\r | |
529a5a86 MK |
407 | mProtectionMemRange = (MEMORY_PROTECTION_RANGE *) AllocateZeroPool (TotalSize);\r |
408 | ASSERT (mProtectionMemRange != NULL);\r | |
409 | mProtectionMemRangeCount = TotalSize / sizeof (MEMORY_PROTECTION_RANGE);\r | |
410 | \r | |
411 | //\r | |
412 | // Copy existing ranges.\r | |
413 | //\r | |
414 | CopyMem (mProtectionMemRange, mProtectionMemRangeTemplate, sizeof (mProtectionMemRangeTemplate));\r | |
415 | \r | |
416 | //\r | |
417 | // Create split ranges which come from protected ranges.\r | |
418 | //\r | |
419 | TotalSize = (TotalSize / sizeof (MEMORY_PROTECTION_RANGE)) * sizeof (MEMORY_RANGE);\r | |
420 | mSplitMemRange = (MEMORY_RANGE *) AllocateZeroPool (TotalSize);\r | |
421 | ASSERT (mSplitMemRange != NULL);\r | |
422 | \r | |
ee584389 JF |
423 | //\r |
424 | // Create SMM ranges which are set to present and execution-enable.\r | |
425 | //\r | |
426 | NumberOfProtectRange = sizeof (mProtectionMemRangeTemplate) / sizeof (MEMORY_PROTECTION_RANGE);\r | |
427 | for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {\r | |
428 | if (mSmmCpuSmramRanges[Index].CpuStart >= mProtectionMemRange[0].Range.Base &&\r | |
429 | mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top) {\r | |
430 | //\r | |
431 | // If the address have been already covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz\r | |
432 | //\r | |
433 | break;\r | |
434 | }\r | |
435 | mProtectionMemRange[NumberOfProtectRange].Range.Base = mSmmCpuSmramRanges[Index].CpuStart;\r | |
436 | mProtectionMemRange[NumberOfProtectRange].Range.Top = mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize;\r | |
437 | mProtectionMemRange[NumberOfProtectRange].Present = TRUE;\r | |
438 | mProtectionMemRange[NumberOfProtectRange].Nx = FALSE;\r | |
439 | NumberOfProtectRange++;\r | |
440 | }\r | |
441 | \r | |
529a5a86 MK |
442 | //\r |
443 | // Create MMIO ranges which are set to present and execution-disable.\r | |
444 | //\r | |
529a5a86 MK |
445 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r |
446 | if (MemorySpaceMap[Index].GcdMemoryType != EfiGcdMemoryTypeMemoryMappedIo) {\r | |
447 | continue;\r | |
448 | }\r | |
449 | mProtectionMemRange[NumberOfProtectRange].Range.Base = MemorySpaceMap[Index].BaseAddress;\r | |
450 | mProtectionMemRange[NumberOfProtectRange].Range.Top = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length;\r | |
451 | mProtectionMemRange[NumberOfProtectRange].Present = TRUE;\r | |
452 | mProtectionMemRange[NumberOfProtectRange].Nx = TRUE;\r | |
453 | NumberOfProtectRange++;\r | |
454 | }\r | |
ee584389 JF |
455 | \r |
456 | //\r | |
457 | // Check and updated actual protected memory ranges count\r | |
458 | //\r | |
459 | ASSERT (NumberOfProtectRange <= mProtectionMemRangeCount);\r | |
460 | mProtectionMemRangeCount = NumberOfProtectRange;\r | |
529a5a86 MK |
461 | }\r |
462 | \r | |
463 | //\r | |
464 | // According to protected ranges, create the ranges which will be mapped by 2KB page.\r | |
465 | //\r | |
466 | NumberOfSpliteRange = 0;\r | |
467 | NumberOfProtectRange = mProtectionMemRangeCount;\r | |
468 | for (Index = 0; Index < NumberOfProtectRange; Index++) {\r | |
469 | //\r | |
470 | // If MMIO base address is not 2MB alignment, make 2MB alignment for create 4KB page in page table.\r | |
471 | //\r | |
472 | ProtectBaseAddress = mProtectionMemRange[Index].Range.Base;\r | |
473 | ProtectEndAddress = mProtectionMemRange[Index].Range.Top;\r | |
474 | if (((ProtectBaseAddress & (SIZE_2MB - 1)) != 0) || ((ProtectEndAddress & (SIZE_2MB - 1)) != 0)) {\r | |
475 | //\r | |
476 | // Check if it is possible to create 4KB-page for not 2MB-aligned range and to create 2MB-page for 2MB-aligned range.\r | |
477 | // A mix of 4KB and 2MB page could save SMRAM space.\r | |
478 | //\r | |
479 | Top2MBAlignedAddress = ProtectEndAddress & ~(SIZE_2MB - 1);\r | |
480 | Base2MBAlignedAddress = (ProtectBaseAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);\r | |
481 | if ((Top2MBAlignedAddress > Base2MBAlignedAddress) &&\r | |
482 | ((Top2MBAlignedAddress - Base2MBAlignedAddress) >= SIZE_2MB)) {\r | |
483 | //\r | |
484 | // There is an range which could be mapped by 2MB-page.\r | |
485 | //\r | |
486 | High4KBPageSize = ((ProtectEndAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1)) - (ProtectEndAddress & ~(SIZE_2MB - 1));\r | |
487 | Low4KBPageSize = ((ProtectBaseAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1)) - (ProtectBaseAddress & ~(SIZE_2MB - 1));\r | |
488 | if (High4KBPageSize != 0) {\r | |
489 | //\r | |
490 | // Add not 2MB-aligned range to be mapped by 4KB-page.\r | |
491 | //\r | |
492 | mSplitMemRange[NumberOfSpliteRange].Base = ProtectEndAddress & ~(SIZE_2MB - 1);\r | |
493 | mSplitMemRange[NumberOfSpliteRange].Top = (ProtectEndAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);\r | |
494 | NumberOfSpliteRange++;\r | |
495 | }\r | |
496 | if (Low4KBPageSize != 0) {\r | |
497 | //\r | |
498 | // Add not 2MB-aligned range to be mapped by 4KB-page.\r | |
499 | //\r | |
500 | mSplitMemRange[NumberOfSpliteRange].Base = ProtectBaseAddress & ~(SIZE_2MB - 1);\r | |
501 | mSplitMemRange[NumberOfSpliteRange].Top = (ProtectBaseAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);\r | |
502 | NumberOfSpliteRange++;\r | |
503 | }\r | |
504 | } else {\r | |
505 | //\r | |
506 | // The range could only be mapped by 4KB-page.\r | |
507 | //\r | |
508 | mSplitMemRange[NumberOfSpliteRange].Base = ProtectBaseAddress & ~(SIZE_2MB - 1);\r | |
509 | mSplitMemRange[NumberOfSpliteRange].Top = (ProtectEndAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);\r | |
510 | NumberOfSpliteRange++;\r | |
511 | }\r | |
512 | }\r | |
513 | }\r | |
514 | \r | |
515 | mSplitMemRangeCount = NumberOfSpliteRange;\r | |
516 | \r | |
517 | DEBUG ((EFI_D_INFO, "SMM Profile Memory Ranges:\n"));\r | |
518 | for (Index = 0; Index < mProtectionMemRangeCount; Index++) {\r | |
519 | DEBUG ((EFI_D_INFO, "mProtectionMemRange[%d].Base = %lx\n", Index, mProtectionMemRange[Index].Range.Base));\r | |
520 | DEBUG ((EFI_D_INFO, "mProtectionMemRange[%d].Top = %lx\n", Index, mProtectionMemRange[Index].Range.Top));\r | |
521 | }\r | |
522 | for (Index = 0; Index < mSplitMemRangeCount; Index++) {\r | |
523 | DEBUG ((EFI_D_INFO, "mSplitMemRange[%d].Base = %lx\n", Index, mSplitMemRange[Index].Base));\r | |
524 | DEBUG ((EFI_D_INFO, "mSplitMemRange[%d].Top = %lx\n", Index, mSplitMemRange[Index].Top));\r | |
525 | }\r | |
526 | }\r | |
527 | \r | |
528 | /**\r | |
529 | Update page table according to protected memory ranges and the 4KB-page mapped memory ranges.\r | |
530 | \r | |
531 | **/\r | |
532 | VOID\r | |
533 | InitPaging (\r | |
534 | VOID\r | |
535 | )\r | |
536 | {\r | |
7365eb2c RN |
537 | UINT64 Pml5Entry;\r |
538 | UINT64 Pml4Entry;\r | |
539 | UINT64 *Pml5;\r | |
529a5a86 | 540 | UINT64 *Pml4;\r |
7e56f892 RN |
541 | UINT64 *Pdpt;\r |
542 | UINT64 *Pd;\r | |
529a5a86 MK |
543 | UINT64 *Pt;\r |
544 | UINTN Address;\r | |
7365eb2c | 545 | UINTN Pml5Index;\r |
7e56f892 RN |
546 | UINTN Pml4Index;\r |
547 | UINTN PdptIndex;\r | |
548 | UINTN PdIndex;\r | |
549 | UINTN PtIndex;\r | |
550 | UINTN NumberOfPdptEntries;\r | |
529a5a86 | 551 | UINTN NumberOfPml4Entries;\r |
7365eb2c | 552 | UINTN NumberOfPml5Entries;\r |
529a5a86 MK |
553 | UINTN SizeOfMemorySpace;\r |
554 | BOOLEAN Nx;\r | |
7365eb2c RN |
555 | IA32_CR4 Cr4;\r |
556 | BOOLEAN Enable5LevelPaging;\r | |
557 | \r | |
558 | Cr4.UintN = AsmReadCr4 ();\r | |
559 | Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);\r | |
529a5a86 MK |
560 | \r |
561 | if (sizeof (UINTN) == sizeof (UINT64)) {\r | |
7365eb2c RN |
562 | if (!Enable5LevelPaging) {\r |
563 | Pml5Entry = (UINTN) mSmmProfileCr3 | IA32_PG_P;\r | |
564 | Pml5 = &Pml5Entry;\r | |
565 | } else {\r | |
566 | Pml5 = (UINT64*) (UINTN) mSmmProfileCr3;\r | |
567 | }\r | |
529a5a86 MK |
568 | SizeOfMemorySpace = HighBitSet64 (gPhyMask) + 1;\r |
569 | //\r | |
570 | // Calculate the table entries of PML4E and PDPTE.\r | |
571 | //\r | |
7365eb2c RN |
572 | NumberOfPml5Entries = 1;\r |
573 | if (SizeOfMemorySpace > 48) {\r | |
574 | NumberOfPml5Entries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 48);\r | |
575 | SizeOfMemorySpace = 48;\r | |
529a5a86 | 576 | }\r |
7365eb2c | 577 | \r |
529a5a86 | 578 | NumberOfPml4Entries = 1;\r |
7365eb2c RN |
579 | if (SizeOfMemorySpace > 39) {\r |
580 | NumberOfPml4Entries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 39);\r | |
581 | SizeOfMemorySpace = 39;\r | |
582 | }\r | |
583 | \r | |
584 | NumberOfPdptEntries = 1;\r | |
585 | ASSERT (SizeOfMemorySpace > 30);\r | |
586 | NumberOfPdptEntries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 30);\r | |
587 | } else {\r | |
588 | Pml4Entry = (UINTN) mSmmProfileCr3 | IA32_PG_P;\r | |
589 | Pml4 = &Pml4Entry;\r | |
590 | Pml5Entry = (UINTN) Pml4 | IA32_PG_P;\r | |
591 | Pml5 = &Pml5Entry;\r | |
592 | NumberOfPml5Entries = 1;\r | |
593 | NumberOfPml4Entries = 1;\r | |
7e56f892 | 594 | NumberOfPdptEntries = 4;\r |
529a5a86 MK |
595 | }\r |
596 | \r | |
597 | //\r | |
598 | // Go through page table and change 2MB-page into 4KB-page.\r | |
599 | //\r | |
7365eb2c RN |
600 | for (Pml5Index = 0; Pml5Index < NumberOfPml5Entries; Pml5Index++) {\r |
601 | if ((Pml5[Pml5Index] & IA32_PG_P) == 0) {\r | |
602 | //\r | |
603 | // If PML5 entry does not exist, skip it\r | |
604 | //\r | |
605 | continue;\r | |
606 | }\r | |
607 | Pml4 = (UINT64 *) (UINTN) (Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);\r | |
608 | for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {\r | |
7e56f892 | 609 | if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {\r |
529a5a86 | 610 | //\r |
7e56f892 | 611 | // If PML4 entry does not exist, skip it\r |
529a5a86 MK |
612 | //\r |
613 | continue;\r | |
614 | }\r | |
7e56f892 | 615 | Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r |
7365eb2c RN |
616 | for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {\r |
617 | if ((*Pdpt & IA32_PG_P) == 0) {\r | |
618 | //\r | |
619 | // If PDPT entry does not exist, skip it\r | |
620 | //\r | |
621 | continue;\r | |
622 | }\r | |
623 | if ((*Pdpt & IA32_PG_PS) != 0) {\r | |
529a5a86 | 624 | //\r |
7365eb2c | 625 | // This is 1G entry, skip it\r |
529a5a86 MK |
626 | //\r |
627 | continue;\r | |
628 | }\r | |
7365eb2c RN |
629 | Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r |
630 | if (Pd == 0) {\r | |
631 | continue;\r | |
632 | }\r | |
633 | for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {\r | |
634 | if ((*Pd & IA32_PG_P) == 0) {\r | |
635 | //\r | |
636 | // If PD entry does not exist, skip it\r | |
637 | //\r | |
638 | continue;\r | |
639 | }\r | |
640 | Address = (UINTN) LShiftU64 (\r | |
641 | LShiftU64 (\r | |
642 | LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,\r | |
643 | 9\r | |
644 | ) + PdIndex,\r | |
645 | 21\r | |
646 | );\r | |
529a5a86 | 647 | \r |
529a5a86 | 648 | //\r |
7365eb2c | 649 | // If it is 2M page, check IsAddressSplit()\r |
529a5a86 | 650 | //\r |
7365eb2c RN |
651 | if (((*Pd & IA32_PG_PS) != 0) && IsAddressSplit (Address)) {\r |
652 | //\r | |
653 | // Based on current page table, create 4KB page table for split area.\r | |
654 | //\r | |
655 | ASSERT (Address == (*Pd & PHYSICAL_ADDRESS_MASK));\r | |
656 | \r | |
657 | Pt = AllocatePageTableMemory (1);\r | |
658 | ASSERT (Pt != NULL);\r | |
529a5a86 | 659 | \r |
7365eb2c | 660 | *Pd = (UINTN) Pt | IA32_PG_RW | IA32_PG_P;\r |
529a5a86 | 661 | \r |
7365eb2c RN |
662 | // Split it\r |
663 | for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++, Pt++) {\r | |
664 | *Pt = Address + ((PtIndex << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS);\r | |
665 | } // end for PT\r | |
666 | *Pd = (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r | |
667 | } // end if IsAddressSplit\r | |
668 | } // end for PD\r | |
669 | } // end for PDPT\r | |
670 | } // end for PML4\r | |
671 | } // end for PML5\r | |
529a5a86 MK |
672 | \r |
673 | //\r | |
674 | // Go through page table and set several page table entries to absent or execute-disable.\r | |
675 | //\r | |
676 | DEBUG ((EFI_D_INFO, "Patch page table start ...\n"));\r | |
7365eb2c RN |
677 | for (Pml5Index = 0; Pml5Index < NumberOfPml5Entries; Pml5Index++) {\r |
678 | if ((Pml5[Pml5Index] & IA32_PG_P) == 0) {\r | |
679 | //\r | |
680 | // If PML5 entry does not exist, skip it\r | |
681 | //\r | |
682 | continue;\r | |
683 | }\r | |
684 | Pml4 = (UINT64 *) (UINTN) (Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);\r | |
685 | for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {\r | |
7e56f892 | 686 | if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {\r |
529a5a86 | 687 | //\r |
7e56f892 | 688 | // If PML4 entry does not exist, skip it\r |
529a5a86 MK |
689 | //\r |
690 | continue;\r | |
691 | }\r | |
7e56f892 | 692 | Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r |
7365eb2c RN |
693 | for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {\r |
694 | if ((*Pdpt & IA32_PG_P) == 0) {\r | |
695 | //\r | |
696 | // If PDPT entry does not exist, skip it\r | |
697 | //\r | |
698 | continue;\r | |
717fb604 | 699 | }\r |
7365eb2c | 700 | if ((*Pdpt & IA32_PG_PS) != 0) {\r |
529a5a86 | 701 | //\r |
7365eb2c | 702 | // This is 1G entry, set NX bit and skip it\r |
529a5a86 | 703 | //\r |
7365eb2c RN |
704 | if (mXdSupported) {\r |
705 | *Pdpt = *Pdpt | IA32_PG_NX;\r | |
706 | }\r | |
529a5a86 MK |
707 | continue;\r |
708 | }\r | |
7365eb2c RN |
709 | Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r |
710 | if (Pd == 0) {\r | |
711 | continue;\r | |
712 | }\r | |
713 | for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {\r | |
714 | if ((*Pd & IA32_PG_P) == 0) {\r | |
529a5a86 | 715 | //\r |
7365eb2c | 716 | // If PD entry does not exist, skip it\r |
529a5a86 | 717 | //\r |
529a5a86 MK |
718 | continue;\r |
719 | }\r | |
7365eb2c RN |
720 | Address = (UINTN) LShiftU64 (\r |
721 | LShiftU64 (\r | |
722 | LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,\r | |
723 | 9\r | |
724 | ) + PdIndex,\r | |
725 | 21\r | |
726 | );\r | |
727 | \r | |
728 | if ((*Pd & IA32_PG_PS) != 0) {\r | |
729 | // 2MB page\r | |
730 | \r | |
529a5a86 | 731 | if (!IsAddressValid (Address, &Nx)) {\r |
7365eb2c RN |
732 | //\r |
733 | // Patch to remove Present flag and RW flag\r | |
734 | //\r | |
735 | *Pd = *Pd & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r | |
529a5a86 MK |
736 | }\r |
737 | if (Nx && mXdSupported) {\r | |
7365eb2c RN |
738 | *Pd = *Pd | IA32_PG_NX;\r |
739 | }\r | |
740 | } else {\r | |
741 | // 4KB page\r | |
742 | Pt = (UINT64 *)(UINTN)(*Pd & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r | |
743 | if (Pt == 0) {\r | |
744 | continue;\r | |
529a5a86 | 745 | }\r |
7365eb2c RN |
746 | for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++, Pt++) {\r |
747 | if (!IsAddressValid (Address, &Nx)) {\r | |
748 | *Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r | |
749 | }\r | |
750 | if (Nx && mXdSupported) {\r | |
751 | *Pt = *Pt | IA32_PG_NX;\r | |
752 | }\r | |
753 | Address += SIZE_4KB;\r | |
754 | } // end for PT\r | |
755 | } // end if PS\r | |
756 | } // end for PD\r | |
757 | } // end for PDPT\r | |
758 | } // end for PML4\r | |
759 | } // end for PML5\r | |
529a5a86 MK |
760 | \r |
761 | //\r | |
762 | // Flush TLB\r | |
763 | //\r | |
764 | CpuFlushTlb ();\r | |
765 | DEBUG ((EFI_D_INFO, "Patch page table done!\n"));\r | |
766 | //\r | |
767 | // Set execute-disable flag\r | |
768 | //\r | |
769 | mXdEnabled = TRUE;\r | |
770 | \r | |
771 | return ;\r | |
772 | }\r | |
773 | \r | |
529a5a86 MK |
774 | /**\r |
775 | To get system port address of the SMI Command Port in FADT table.\r | |
776 | \r | |
777 | **/\r | |
778 | VOID\r | |
779 | GetSmiCommandPort (\r | |
780 | VOID\r | |
781 | )\r | |
782 | {\r | |
783 | EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;\r | |
784 | \r | |
4c214f82 SZ |
785 | Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) EfiLocateFirstAcpiTable (\r |
786 | EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE\r | |
787 | );\r | |
529a5a86 MK |
788 | ASSERT (Fadt != NULL);\r |
789 | \r | |
790 | mSmiCommandPort = Fadt->SmiCmd;\r | |
791 | DEBUG ((EFI_D_INFO, "mSmiCommandPort = %x\n", mSmiCommandPort));\r | |
792 | }\r | |
793 | \r | |
794 | /**\r | |
795 | Updates page table to make some memory ranges (like system memory) absent\r | |
796 | and make some memory ranges (like MMIO) present and execute disable. It also\r | |
797 | update 2MB-page to 4KB-page for some memory ranges.\r | |
798 | \r | |
799 | **/\r | |
800 | VOID\r | |
801 | SmmProfileStart (\r | |
802 | VOID\r | |
803 | )\r | |
804 | {\r | |
805 | //\r | |
806 | // The flag indicates SMM profile starts to work.\r | |
807 | //\r | |
808 | mSmmProfileStart = TRUE;\r | |
809 | }\r | |
810 | \r | |
811 | /**\r | |
812 | Initialize SMM profile in SmmReadyToLock protocol callback function.\r | |
813 | \r | |
814 | @param Protocol Points to the protocol's unique identifier.\r | |
815 | @param Interface Points to the interface instance.\r | |
816 | @param Handle The handle on which the interface was installed.\r | |
817 | \r | |
818 | @retval EFI_SUCCESS SmmReadyToLock protocol callback runs successfully.\r | |
819 | **/\r | |
820 | EFI_STATUS\r | |
821 | EFIAPI\r | |
822 | InitSmmProfileCallBack (\r | |
823 | IN CONST EFI_GUID *Protocol,\r | |
824 | IN VOID *Interface,\r | |
825 | IN EFI_HANDLE Handle\r | |
826 | )\r | |
827 | {\r | |
529a5a86 MK |
828 | //\r |
829 | // Save to variable so that SMM profile data can be found.\r | |
830 | //\r | |
dc0a7143 LE |
831 | gRT->SetVariable (\r |
832 | SMM_PROFILE_NAME,\r | |
833 | &gEfiCallerIdGuid,\r | |
834 | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r | |
835 | sizeof(mSmmProfileBase),\r | |
836 | &mSmmProfileBase\r | |
837 | );\r | |
529a5a86 MK |
838 | \r |
839 | //\r | |
840 | // Get Software SMI from FADT\r | |
841 | //\r | |
842 | GetSmiCommandPort ();\r | |
843 | \r | |
844 | //\r | |
845 | // Initialize protected memory range for patching page table later.\r | |
846 | //\r | |
847 | InitProtectedMemRange ();\r | |
848 | \r | |
849 | return EFI_SUCCESS;\r | |
850 | }\r | |
851 | \r | |
852 | /**\r | |
853 | Initialize SMM profile data structures.\r | |
854 | \r | |
855 | **/\r | |
856 | VOID\r | |
857 | InitSmmProfileInternal (\r | |
858 | VOID\r | |
859 | )\r | |
860 | {\r | |
861 | EFI_STATUS Status;\r | |
862 | EFI_PHYSICAL_ADDRESS Base;\r | |
863 | VOID *Registration;\r | |
864 | UINTN Index;\r | |
865 | UINTN MsrDsAreaSizePerCpu;\r | |
866 | UINTN TotalSize;\r | |
867 | \r | |
bb767506 | 868 | mPFEntryCount = (UINTN *)AllocateZeroPool (sizeof (UINTN) * mMaxNumberOfCpus);\r |
529a5a86 MK |
869 | ASSERT (mPFEntryCount != NULL);\r |
870 | mLastPFEntryValue = (UINT64 (*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (\r | |
bb767506 | 871 | sizeof (mLastPFEntryValue[0]) * mMaxNumberOfCpus);\r |
529a5a86 MK |
872 | ASSERT (mLastPFEntryValue != NULL);\r |
873 | mLastPFEntryPointer = (UINT64 *(*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (\r | |
bb767506 | 874 | sizeof (mLastPFEntryPointer[0]) * mMaxNumberOfCpus);\r |
529a5a86 MK |
875 | ASSERT (mLastPFEntryPointer != NULL);\r |
876 | \r | |
877 | //\r | |
878 | // Allocate memory for SmmProfile below 4GB.\r | |
879 | // The base address\r | |
880 | //\r | |
881 | mSmmProfileSize = PcdGet32 (PcdCpuSmmProfileSize);\r | |
882 | ASSERT ((mSmmProfileSize & 0xFFF) == 0);\r | |
883 | \r | |
884 | if (mBtsSupported) {\r | |
885 | TotalSize = mSmmProfileSize + mMsrDsAreaSize;\r | |
886 | } else {\r | |
887 | TotalSize = mSmmProfileSize;\r | |
888 | }\r | |
889 | \r | |
890 | Base = 0xFFFFFFFF;\r | |
891 | Status = gBS->AllocatePages (\r | |
892 | AllocateMaxAddress,\r | |
893 | EfiReservedMemoryType,\r | |
894 | EFI_SIZE_TO_PAGES (TotalSize),\r | |
895 | &Base\r | |
896 | );\r | |
897 | ASSERT_EFI_ERROR (Status);\r | |
898 | ZeroMem ((VOID *)(UINTN)Base, TotalSize);\r | |
899 | mSmmProfileBase = (SMM_PROFILE_HEADER *)(UINTN)Base;\r | |
900 | \r | |
901 | //\r | |
902 | // Initialize SMM profile data header.\r | |
903 | //\r | |
904 | mSmmProfileBase->HeaderSize = sizeof (SMM_PROFILE_HEADER);\r | |
905 | mSmmProfileBase->MaxDataEntries = (UINT64)((mSmmProfileSize - sizeof(SMM_PROFILE_HEADER)) / sizeof (SMM_PROFILE_ENTRY));\r | |
906 | mSmmProfileBase->MaxDataSize = MultU64x64 (mSmmProfileBase->MaxDataEntries, sizeof(SMM_PROFILE_ENTRY));\r | |
907 | mSmmProfileBase->CurDataEntries = 0;\r | |
908 | mSmmProfileBase->CurDataSize = 0;\r | |
909 | mSmmProfileBase->TsegStart = mCpuHotPlugData.SmrrBase;\r | |
910 | mSmmProfileBase->TsegSize = mCpuHotPlugData.SmrrSize;\r | |
911 | mSmmProfileBase->NumSmis = 0;\r | |
912 | mSmmProfileBase->NumCpus = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r | |
913 | \r | |
914 | if (mBtsSupported) {\r | |
bb767506 | 915 | mMsrDsArea = (MSR_DS_AREA_STRUCT **)AllocateZeroPool (sizeof (MSR_DS_AREA_STRUCT *) * mMaxNumberOfCpus);\r |
529a5a86 | 916 | ASSERT (mMsrDsArea != NULL);\r |
bb767506 | 917 | mMsrBTSRecord = (BRANCH_TRACE_RECORD **)AllocateZeroPool (sizeof (BRANCH_TRACE_RECORD *) * mMaxNumberOfCpus);\r |
529a5a86 | 918 | ASSERT (mMsrBTSRecord != NULL);\r |
bb767506 | 919 | mMsrPEBSRecord = (PEBS_RECORD **)AllocateZeroPool (sizeof (PEBS_RECORD *) * mMaxNumberOfCpus);\r |
529a5a86 MK |
920 | ASSERT (mMsrPEBSRecord != NULL);\r |
921 | \r | |
922 | mMsrDsAreaBase = (MSR_DS_AREA_STRUCT *)((UINTN)Base + mSmmProfileSize);\r | |
bb767506 | 923 | MsrDsAreaSizePerCpu = mMsrDsAreaSize / mMaxNumberOfCpus;\r |
529a5a86 | 924 | mBTSRecordNumber = (MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER - sizeof(MSR_DS_AREA_STRUCT)) / sizeof(BRANCH_TRACE_RECORD);\r |
bb767506 | 925 | for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r |
529a5a86 MK |
926 | mMsrDsArea[Index] = (MSR_DS_AREA_STRUCT *)((UINTN)mMsrDsAreaBase + MsrDsAreaSizePerCpu * Index);\r |
927 | mMsrBTSRecord[Index] = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[Index] + sizeof(MSR_DS_AREA_STRUCT));\r | |
928 | mMsrPEBSRecord[Index] = (PEBS_RECORD *)((UINTN)mMsrDsArea[Index] + MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER);\r | |
929 | \r | |
930 | mMsrDsArea[Index]->BTSBufferBase = (UINTN)mMsrBTSRecord[Index];\r | |
931 | mMsrDsArea[Index]->BTSIndex = mMsrDsArea[Index]->BTSBufferBase;\r | |
932 | mMsrDsArea[Index]->BTSAbsoluteMaximum = mMsrDsArea[Index]->BTSBufferBase + mBTSRecordNumber * sizeof(BRANCH_TRACE_RECORD) + 1;\r | |
933 | mMsrDsArea[Index]->BTSInterruptThreshold = mMsrDsArea[Index]->BTSAbsoluteMaximum + 1;\r | |
934 | \r | |
935 | mMsrDsArea[Index]->PEBSBufferBase = (UINTN)mMsrPEBSRecord[Index];\r | |
936 | mMsrDsArea[Index]->PEBSIndex = mMsrDsArea[Index]->PEBSBufferBase;\r | |
937 | mMsrDsArea[Index]->PEBSAbsoluteMaximum = mMsrDsArea[Index]->PEBSBufferBase + PEBS_RECORD_NUMBER * sizeof(PEBS_RECORD) + 1;\r | |
938 | mMsrDsArea[Index]->PEBSInterruptThreshold = mMsrDsArea[Index]->PEBSAbsoluteMaximum + 1;\r | |
939 | }\r | |
940 | }\r | |
941 | \r | |
942 | mProtectionMemRange = mProtectionMemRangeTemplate;\r | |
943 | mProtectionMemRangeCount = sizeof (mProtectionMemRangeTemplate) / sizeof (MEMORY_PROTECTION_RANGE);\r | |
944 | \r | |
945 | //\r | |
946 | // Update TSeg entry.\r | |
947 | //\r | |
948 | mProtectionMemRange[0].Range.Base = mCpuHotPlugData.SmrrBase;\r | |
949 | mProtectionMemRange[0].Range.Top = mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize;\r | |
950 | \r | |
951 | //\r | |
952 | // Update SMM profile entry.\r | |
953 | //\r | |
954 | mProtectionMemRange[1].Range.Base = (EFI_PHYSICAL_ADDRESS)(UINTN)mSmmProfileBase;\r | |
955 | mProtectionMemRange[1].Range.Top = (EFI_PHYSICAL_ADDRESS)(UINTN)mSmmProfileBase + TotalSize;\r | |
956 | \r | |
957 | //\r | |
958 | // Allocate memory reserved for creating 4KB pages.\r | |
959 | //\r | |
960 | InitPagesForPFHandler ();\r | |
961 | \r | |
962 | //\r | |
963 | // Start SMM profile when SmmReadyToLock protocol is installed.\r | |
964 | //\r | |
965 | Status = gSmst->SmmRegisterProtocolNotify (\r | |
966 | &gEfiSmmReadyToLockProtocolGuid,\r | |
967 | InitSmmProfileCallBack,\r | |
968 | &Registration\r | |
969 | );\r | |
970 | ASSERT_EFI_ERROR (Status);\r | |
971 | \r | |
972 | return ;\r | |
973 | }\r | |
974 | \r | |
975 | /**\r | |
3eb69b08 | 976 | Check if feature is supported by a processor.\r |
529a5a86 MK |
977 | \r |
978 | **/\r | |
979 | VOID\r | |
980 | CheckFeatureSupported (\r | |
51773d49 | 981 | VOID\r |
529a5a86 MK |
982 | )\r |
983 | {\r | |
f85d3ce2 | 984 | UINT32 RegEax;\r |
3eb69b08 | 985 | UINT32 RegEcx;\r |
f85d3ce2 JF |
986 | UINT32 RegEdx;\r |
987 | MSR_IA32_MISC_ENABLE_REGISTER MiscEnableMsr;\r | |
529a5a86 | 988 | \r |
3eb69b08 JY |
989 | if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {\r |
990 | AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r | |
991 | if (RegEax <= CPUID_EXTENDED_FUNCTION) {\r | |
992 | mCetSupported = FALSE;\r | |
993 | PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);\r | |
994 | }\r | |
995 | AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL, NULL, &RegEcx, NULL);\r | |
996 | if ((RegEcx & CPUID_CET_SS) == 0) {\r | |
997 | mCetSupported = FALSE;\r | |
998 | PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);\r | |
999 | }\r | |
1000 | }\r | |
1001 | \r | |
529a5a86 MK |
1002 | if (mXdSupported) {\r |
1003 | AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r | |
1004 | if (RegEax <= CPUID_EXTENDED_FUNCTION) {\r | |
1005 | //\r | |
1006 | // Extended CPUID functions are not supported on this processor.\r | |
1007 | //\r | |
1008 | mXdSupported = FALSE;\r | |
3c5ce64f | 1009 | PatchInstructionX86 (gPatchXdSupported, mXdSupported, 1);\r |
529a5a86 MK |
1010 | }\r |
1011 | \r | |
1012 | AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);\r | |
1013 | if ((RegEdx & CPUID1_EDX_XD_SUPPORT) == 0) {\r | |
1014 | //\r | |
1015 | // Execute Disable Bit feature is not supported on this processor.\r | |
1016 | //\r | |
1017 | mXdSupported = FALSE;\r | |
3c5ce64f | 1018 | PatchInstructionX86 (gPatchXdSupported, mXdSupported, 1);\r |
529a5a86 MK |
1019 | }\r |
1020 | }\r | |
1021 | \r | |
1022 | if (mBtsSupported) {\r | |
1023 | AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);\r | |
1024 | if ((RegEdx & CPUID1_EDX_BTS_AVAILABLE) != 0) {\r | |
1025 | //\r | |
1026 | // Per IA32 manuals:\r | |
1027 | // When CPUID.1:EDX[21] is set, the following BTS facilities are available:\r | |
1028 | // 1. The BTS_UNAVAILABLE flag in the IA32_MISC_ENABLE MSR indicates the\r | |
1029 | // availability of the BTS facilities, including the ability to set the BTS and\r | |
1030 | // BTINT bits in the MSR_DEBUGCTLA MSR.\r | |
1031 | // 2. The IA32_DS_AREA MSR can be programmed to point to the DS save area.\r | |
1032 | //\r | |
f85d3ce2 JF |
1033 | MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);\r |
1034 | if (MiscEnableMsr.Bits.BTS == 1) {\r | |
529a5a86 | 1035 | //\r |
f85d3ce2 | 1036 | // BTS facilities is not supported if MSR_IA32_MISC_ENABLE.BTS bit is set.\r |
529a5a86 MK |
1037 | //\r |
1038 | mBtsSupported = FALSE;\r | |
1039 | }\r | |
1040 | }\r | |
1041 | }\r | |
1042 | }\r | |
1043 | \r | |
529a5a86 MK |
1044 | /**\r |
1045 | Enable single step.\r | |
1046 | \r | |
1047 | **/\r | |
1048 | VOID\r | |
1049 | ActivateSingleStepDB (\r | |
1050 | VOID\r | |
1051 | )\r | |
1052 | {\r | |
1053 | UINTN Dr6;\r | |
1054 | \r | |
1055 | Dr6 = AsmReadDr6 ();\r | |
1056 | if ((Dr6 & DR6_SINGLE_STEP) != 0) {\r | |
1057 | return;\r | |
1058 | }\r | |
1059 | Dr6 |= DR6_SINGLE_STEP;\r | |
1060 | AsmWriteDr6 (Dr6);\r | |
1061 | }\r | |
1062 | \r | |
1063 | /**\r | |
1064 | Enable last branch.\r | |
1065 | \r | |
1066 | **/\r | |
1067 | VOID\r | |
1068 | ActivateLBR (\r | |
1069 | VOID\r | |
1070 | )\r | |
1071 | {\r | |
1072 | UINT64 DebugCtl;\r | |
1073 | \r | |
1074 | DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL);\r | |
1075 | if ((DebugCtl & MSR_DEBUG_CTL_LBR) != 0) {\r | |
1076 | return ;\r | |
1077 | }\r | |
529a5a86 MK |
1078 | DebugCtl |= MSR_DEBUG_CTL_LBR;\r |
1079 | AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl);\r | |
1080 | }\r | |
1081 | \r | |
1082 | /**\r | |
1083 | Enable branch trace store.\r | |
1084 | \r | |
1085 | @param CpuIndex The index of the processor.\r | |
1086 | \r | |
1087 | **/\r | |
1088 | VOID\r | |
1089 | ActivateBTS (\r | |
1090 | IN UINTN CpuIndex\r | |
1091 | )\r | |
1092 | {\r | |
1093 | UINT64 DebugCtl;\r | |
1094 | \r | |
1095 | DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL);\r | |
1096 | if ((DebugCtl & MSR_DEBUG_CTL_BTS) != 0) {\r | |
1097 | return ;\r | |
1098 | }\r | |
1099 | \r | |
1100 | AsmWriteMsr64 (MSR_DS_AREA, (UINT64)(UINTN)mMsrDsArea[CpuIndex]);\r | |
1101 | DebugCtl |= (UINT64)(MSR_DEBUG_CTL_BTS | MSR_DEBUG_CTL_TR);\r | |
1102 | DebugCtl &= ~((UINT64)MSR_DEBUG_CTL_BTINT);\r | |
1103 | AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl);\r | |
1104 | }\r | |
1105 | \r | |
1106 | /**\r | |
1107 | Increase SMI number in each SMI entry.\r | |
1108 | \r | |
1109 | **/\r | |
1110 | VOID\r | |
1111 | SmmProfileRecordSmiNum (\r | |
1112 | VOID\r | |
1113 | )\r | |
1114 | {\r | |
1115 | if (mSmmProfileStart) {\r | |
1116 | mSmmProfileBase->NumSmis++;\r | |
1117 | }\r | |
1118 | }\r | |
1119 | \r | |
1120 | /**\r | |
1121 | Initialize processor environment for SMM profile.\r | |
1122 | \r | |
1123 | @param CpuIndex The index of the processor.\r | |
1124 | \r | |
1125 | **/\r | |
1126 | VOID\r | |
1127 | ActivateSmmProfile (\r | |
1128 | IN UINTN CpuIndex\r | |
1129 | )\r | |
1130 | {\r | |
1131 | //\r | |
1132 | // Enable Single Step DB#\r | |
1133 | //\r | |
1134 | ActivateSingleStepDB ();\r | |
1135 | \r | |
1136 | if (mBtsSupported) {\r | |
1137 | //\r | |
1138 | // We can not get useful information from LER, so we have to use BTS.\r | |
1139 | //\r | |
1140 | ActivateLBR ();\r | |
1141 | \r | |
1142 | //\r | |
1143 | // Enable BTS\r | |
1144 | //\r | |
1145 | ActivateBTS (CpuIndex);\r | |
1146 | }\r | |
1147 | }\r | |
1148 | \r | |
1149 | /**\r | |
1150 | Initialize SMM profile in SMM CPU entry point.\r | |
1151 | \r | |
1152 | @param[in] Cr3 The base address of the page tables to use in SMM.\r | |
1153 | \r | |
1154 | **/\r | |
1155 | VOID\r | |
1156 | InitSmmProfile (\r | |
1157 | UINT32 Cr3\r | |
1158 | )\r | |
1159 | {\r | |
1160 | //\r | |
1161 | // Save Cr3\r | |
1162 | //\r | |
1163 | mSmmProfileCr3 = Cr3;\r | |
1164 | \r | |
1165 | //\r | |
1166 | // Skip SMM profile initialization if feature is disabled\r | |
1167 | //\r | |
09afd9a4 JW |
1168 | if (!FeaturePcdGet (PcdCpuSmmProfileEnable) &&\r |
1169 | !HEAP_GUARD_NONSTOP_MODE &&\r | |
1170 | !NULL_DETECTION_NONSTOP_MODE) {\r | |
529a5a86 MK |
1171 | return;\r |
1172 | }\r | |
1173 | \r | |
1174 | //\r | |
1175 | // Initialize SmmProfile here\r | |
1176 | //\r | |
1177 | InitSmmProfileInternal ();\r | |
1178 | \r | |
1179 | //\r | |
1180 | // Initialize profile IDT.\r | |
1181 | //\r | |
1182 | InitIdtr ();\r | |
09afd9a4 JW |
1183 | \r |
1184 | //\r | |
1185 | // Tell #PF handler to prepare a #DB subsequently.\r | |
1186 | //\r | |
1187 | mSetupDebugTrap = TRUE;\r | |
529a5a86 MK |
1188 | }\r |
1189 | \r | |
1190 | /**\r | |
1191 | Update page table to map the memory correctly in order to make the instruction\r | |
1192 | which caused page fault execute successfully. And it also save the original page\r | |
1193 | table to be restored in single-step exception.\r | |
1194 | \r | |
1195 | @param PageTable PageTable Address.\r | |
1196 | @param PFAddress The memory address which caused page fault exception.\r | |
1197 | @param CpuIndex The index of the processor.\r | |
1198 | @param ErrorCode The Error code of exception.\r | |
1199 | \r | |
1200 | **/\r | |
1201 | VOID\r | |
1202 | RestorePageTableBelow4G (\r | |
1203 | UINT64 *PageTable,\r | |
1204 | UINT64 PFAddress,\r | |
1205 | UINTN CpuIndex,\r | |
1206 | UINTN ErrorCode\r | |
1207 | )\r | |
1208 | {\r | |
1209 | UINTN PTIndex;\r | |
1210 | UINTN PFIndex;\r | |
7365eb2c RN |
1211 | IA32_CR4 Cr4;\r |
1212 | BOOLEAN Enable5LevelPaging;\r | |
1213 | \r | |
1214 | Cr4.UintN = AsmReadCr4 ();\r | |
1215 | Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);\r | |
1216 | \r | |
1217 | //\r | |
1218 | // PML5\r | |
1219 | //\r | |
1220 | if (Enable5LevelPaging) {\r | |
1221 | PTIndex = (UINTN)BitFieldRead64 (PFAddress, 48, 56);\r | |
1222 | ASSERT (PageTable[PTIndex] != 0);\r | |
1223 | PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r | |
1224 | }\r | |
529a5a86 MK |
1225 | \r |
1226 | //\r | |
1227 | // PML4\r | |
1228 | //\r | |
1229 | if (sizeof(UINT64) == sizeof(UINTN)) {\r | |
1230 | PTIndex = (UINTN)BitFieldRead64 (PFAddress, 39, 47);\r | |
1231 | ASSERT (PageTable[PTIndex] != 0);\r | |
1232 | PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r | |
1233 | }\r | |
1234 | \r | |
1235 | //\r | |
1236 | // PDPTE\r | |
1237 | //\r | |
1238 | PTIndex = (UINTN)BitFieldRead64 (PFAddress, 30, 38);\r | |
1239 | ASSERT (PageTable[PTIndex] != 0);\r | |
1240 | PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r | |
1241 | \r | |
1242 | //\r | |
1243 | // PD\r | |
1244 | //\r | |
1245 | PTIndex = (UINTN)BitFieldRead64 (PFAddress, 21, 29);\r | |
1246 | if ((PageTable[PTIndex] & IA32_PG_PS) != 0) {\r | |
1247 | //\r | |
1248 | // Large page\r | |
1249 | //\r | |
1250 | \r | |
1251 | //\r | |
1252 | // Record old entries with non-present status\r | |
1253 | // Old entries include the memory which instruction is at and the memory which instruction access.\r | |
1254 | //\r | |
1255 | //\r | |
1256 | ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT);\r | |
1257 | if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) {\r | |
1258 | PFIndex = mPFEntryCount[CpuIndex];\r | |
1259 | mLastPFEntryValue[CpuIndex][PFIndex] = PageTable[PTIndex];\r | |
1260 | mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex];\r | |
1261 | mPFEntryCount[CpuIndex]++;\r | |
1262 | }\r | |
1263 | \r | |
1264 | //\r | |
1265 | // Set new entry\r | |
1266 | //\r | |
1267 | PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1));\r | |
1268 | PageTable[PTIndex] |= (UINT64)IA32_PG_PS;\r | |
881520ea | 1269 | PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;\r |
529a5a86 MK |
1270 | if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r |
1271 | PageTable[PTIndex] &= ~IA32_PG_NX;\r | |
1272 | }\r | |
1273 | } else {\r | |
1274 | //\r | |
1275 | // Small page\r | |
1276 | //\r | |
1277 | ASSERT (PageTable[PTIndex] != 0);\r | |
1278 | PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r | |
1279 | \r | |
1280 | //\r | |
1281 | // 4K PTE\r | |
1282 | //\r | |
1283 | PTIndex = (UINTN)BitFieldRead64 (PFAddress, 12, 20);\r | |
1284 | \r | |
1285 | //\r | |
1286 | // Record old entries with non-present status\r | |
1287 | // Old entries include the memory which instruction is at and the memory which instruction access.\r | |
1288 | //\r | |
1289 | //\r | |
1290 | ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT);\r | |
1291 | if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) {\r | |
1292 | PFIndex = mPFEntryCount[CpuIndex];\r | |
1293 | mLastPFEntryValue[CpuIndex][PFIndex] = PageTable[PTIndex];\r | |
1294 | mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex];\r | |
1295 | mPFEntryCount[CpuIndex]++;\r | |
1296 | }\r | |
1297 | \r | |
1298 | //\r | |
1299 | // Set new entry\r | |
1300 | //\r | |
1301 | PageTable[PTIndex] = (PFAddress & ~((1ull << 12) - 1));\r | |
881520ea | 1302 | PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;\r |
529a5a86 MK |
1303 | if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r |
1304 | PageTable[PTIndex] &= ~IA32_PG_NX;\r | |
1305 | }\r | |
1306 | }\r | |
1307 | }\r | |
1308 | \r | |
09afd9a4 JW |
1309 | /**\r |
1310 | Handler for Page Fault triggered by Guard page.\r | |
1311 | \r | |
1312 | @param ErrorCode The Error code of exception.\r | |
1313 | \r | |
1314 | **/\r | |
1315 | VOID\r | |
1316 | GuardPagePFHandler (\r | |
1317 | UINTN ErrorCode\r | |
1318 | )\r | |
1319 | {\r | |
1320 | UINT64 *PageTable;\r | |
1321 | UINT64 PFAddress;\r | |
1322 | UINT64 RestoreAddress;\r | |
1323 | UINTN RestorePageNumber;\r | |
1324 | UINTN CpuIndex;\r | |
1325 | \r | |
1326 | PageTable = (UINT64 *)AsmReadCr3 ();\r | |
1327 | PFAddress = AsmReadCr2 ();\r | |
1328 | CpuIndex = GetCpuIndex ();\r | |
1329 | \r | |
1330 | //\r | |
1331 | // Memory operation cross pages, like "rep mov" instruction, will cause\r | |
1332 | // infinite loop between this and Debug Trap handler. We have to make sure\r | |
1333 | // that current page and the page followed are both in PRESENT state.\r | |
1334 | //\r | |
1335 | RestorePageNumber = 2;\r | |
1336 | RestoreAddress = PFAddress;\r | |
1337 | while (RestorePageNumber > 0) {\r | |
1338 | RestorePageTableBelow4G (PageTable, RestoreAddress, CpuIndex, ErrorCode);\r | |
1339 | RestoreAddress += EFI_PAGE_SIZE;\r | |
1340 | RestorePageNumber--;\r | |
1341 | }\r | |
1342 | \r | |
1343 | //\r | |
1344 | // Flush TLB\r | |
1345 | //\r | |
1346 | CpuFlushTlb ();\r | |
1347 | }\r | |
1348 | \r | |
529a5a86 MK |
1349 | /**\r |
1350 | The Page fault handler to save SMM profile data.\r | |
1351 | \r | |
1352 | @param Rip The RIP when exception happens.\r | |
1353 | @param ErrorCode The Error code of exception.\r | |
1354 | \r | |
1355 | **/\r | |
1356 | VOID\r | |
1357 | SmmProfilePFHandler (\r | |
1358 | UINTN Rip,\r | |
1359 | UINTN ErrorCode\r | |
1360 | )\r | |
1361 | {\r | |
1362 | UINT64 *PageTable;\r | |
1363 | UINT64 PFAddress;\r | |
890d9ee5 JW |
1364 | UINT64 RestoreAddress;\r |
1365 | UINTN RestorePageNumber;\r | |
529a5a86 MK |
1366 | UINTN CpuIndex;\r |
1367 | UINTN Index;\r | |
1368 | UINT64 InstructionAddress;\r | |
1369 | UINTN MaxEntryNumber;\r | |
1370 | UINTN CurrentEntryNumber;\r | |
1371 | BOOLEAN IsValidPFAddress;\r | |
1372 | SMM_PROFILE_ENTRY *SmmProfileEntry;\r | |
1373 | UINT64 SmiCommand;\r | |
1374 | EFI_STATUS Status;\r | |
529a5a86 MK |
1375 | UINT8 SoftSmiValue;\r |
1376 | EFI_SMM_SAVE_STATE_IO_INFO IoInfo;\r | |
1377 | \r | |
1378 | if (!mSmmProfileStart) {\r | |
1379 | //\r | |
1380 | // If SMM profile does not start, call original page fault handler.\r | |
1381 | //\r | |
1382 | SmiDefaultPFHandler ();\r | |
1383 | return;\r | |
1384 | }\r | |
1385 | \r | |
1386 | if (mBtsSupported) {\r | |
1387 | DisableBTS ();\r | |
1388 | }\r | |
1389 | \r | |
1390 | IsValidPFAddress = FALSE;\r | |
1391 | PageTable = (UINT64 *)AsmReadCr3 ();\r | |
1392 | PFAddress = AsmReadCr2 ();\r | |
1393 | CpuIndex = GetCpuIndex ();\r | |
1394 | \r | |
890d9ee5 JW |
1395 | //\r |
1396 | // Memory operation cross pages, like "rep mov" instruction, will cause\r | |
1397 | // infinite loop between this and Debug Trap handler. We have to make sure\r | |
1398 | // that current page and the page followed are both in PRESENT state.\r | |
1399 | //\r | |
1400 | RestorePageNumber = 2;\r | |
1401 | RestoreAddress = PFAddress;\r | |
1402 | while (RestorePageNumber > 0) {\r | |
1403 | if (RestoreAddress <= 0xFFFFFFFF) {\r | |
1404 | RestorePageTableBelow4G (PageTable, RestoreAddress, CpuIndex, ErrorCode);\r | |
1405 | } else {\r | |
1406 | RestorePageTableAbove4G (PageTable, RestoreAddress, CpuIndex, ErrorCode, &IsValidPFAddress);\r | |
1407 | }\r | |
1408 | RestoreAddress += EFI_PAGE_SIZE;\r | |
1409 | RestorePageNumber--;\r | |
529a5a86 MK |
1410 | }\r |
1411 | \r | |
1412 | if (!IsValidPFAddress) {\r | |
1413 | InstructionAddress = Rip;\r | |
1414 | if ((ErrorCode & IA32_PF_EC_ID) != 0 && (mBtsSupported)) {\r | |
1415 | //\r | |
1416 | // If it is instruction fetch failure, get the correct IP from BTS.\r | |
1417 | //\r | |
1418 | InstructionAddress = GetSourceFromDestinationOnBts (CpuIndex, Rip);\r | |
1419 | if (InstructionAddress == 0) {\r | |
1420 | //\r | |
1421 | // It indicates the instruction which caused page fault is not a jump instruction,\r | |
1422 | // set instruction address same as the page fault address.\r | |
1423 | //\r | |
1424 | InstructionAddress = PFAddress;\r | |
1425 | }\r | |
1426 | }\r | |
1427 | \r | |
529a5a86 MK |
1428 | //\r |
1429 | // Indicate it is not software SMI\r | |
1430 | //\r | |
1431 | SmiCommand = 0xFFFFFFFFFFFFFFFFULL;\r | |
1432 | for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {\r | |
1433 | Status = SmmReadSaveState(&mSmmCpu, sizeof(IoInfo), EFI_SMM_SAVE_STATE_REGISTER_IO, Index, &IoInfo);\r | |
1434 | if (EFI_ERROR (Status)) {\r | |
1435 | continue;\r | |
1436 | }\r | |
1437 | if (IoInfo.IoPort == mSmiCommandPort) {\r | |
529a5a86 MK |
1438 | //\r |
1439 | // A software SMI triggered by SMI command port has been found, get SmiCommand from SMI command port.\r | |
1440 | //\r | |
1441 | SoftSmiValue = IoRead8 (mSmiCommandPort);\r | |
1442 | SmiCommand = (UINT64)SoftSmiValue;\r | |
1443 | break;\r | |
1444 | }\r | |
1445 | }\r | |
1446 | \r | |
1447 | SmmProfileEntry = (SMM_PROFILE_ENTRY *)(UINTN)(mSmmProfileBase + 1);\r | |
1448 | //\r | |
1449 | // Check if there is already a same entry in profile data.\r | |
1450 | //\r | |
1451 | for (Index = 0; Index < (UINTN) mSmmProfileBase->CurDataEntries; Index++) {\r | |
1452 | if ((SmmProfileEntry[Index].ErrorCode == (UINT64)ErrorCode) &&\r | |
1453 | (SmmProfileEntry[Index].Address == PFAddress) &&\r | |
1454 | (SmmProfileEntry[Index].CpuNum == (UINT64)CpuIndex) &&\r | |
1455 | (SmmProfileEntry[Index].Instruction == InstructionAddress) &&\r | |
1456 | (SmmProfileEntry[Index].SmiCmd == SmiCommand)) {\r | |
1457 | //\r | |
1458 | // Same record exist, need not save again.\r | |
1459 | //\r | |
1460 | break;\r | |
1461 | }\r | |
1462 | }\r | |
1463 | if (Index == mSmmProfileBase->CurDataEntries) {\r | |
1464 | CurrentEntryNumber = (UINTN) mSmmProfileBase->CurDataEntries;\r | |
1465 | MaxEntryNumber = (UINTN) mSmmProfileBase->MaxDataEntries;\r | |
1466 | if (FeaturePcdGet (PcdCpuSmmProfileRingBuffer)) {\r | |
1467 | CurrentEntryNumber = CurrentEntryNumber % MaxEntryNumber;\r | |
1468 | }\r | |
1469 | if (CurrentEntryNumber < MaxEntryNumber) {\r | |
1470 | //\r | |
1471 | // Log the new entry\r | |
1472 | //\r | |
1473 | SmmProfileEntry[CurrentEntryNumber].SmiNum = mSmmProfileBase->NumSmis;\r | |
1474 | SmmProfileEntry[CurrentEntryNumber].ErrorCode = (UINT64)ErrorCode;\r | |
1475 | SmmProfileEntry[CurrentEntryNumber].ApicId = (UINT64)GetApicId ();\r | |
1476 | SmmProfileEntry[CurrentEntryNumber].CpuNum = (UINT64)CpuIndex;\r | |
1477 | SmmProfileEntry[CurrentEntryNumber].Address = PFAddress;\r | |
1478 | SmmProfileEntry[CurrentEntryNumber].Instruction = InstructionAddress;\r | |
1479 | SmmProfileEntry[CurrentEntryNumber].SmiCmd = SmiCommand;\r | |
1480 | //\r | |
1481 | // Update current entry index and data size in the header.\r | |
1482 | //\r | |
1483 | mSmmProfileBase->CurDataEntries++;\r | |
1484 | mSmmProfileBase->CurDataSize = MultU64x64 (mSmmProfileBase->CurDataEntries, sizeof (SMM_PROFILE_ENTRY));\r | |
1485 | }\r | |
1486 | }\r | |
1487 | }\r | |
1488 | //\r | |
1489 | // Flush TLB\r | |
1490 | //\r | |
1491 | CpuFlushTlb ();\r | |
1492 | \r | |
1493 | if (mBtsSupported) {\r | |
1494 | EnableBTS ();\r | |
1495 | }\r | |
1496 | }\r | |
1497 | \r | |
1498 | /**\r | |
1499 | Replace INT1 exception handler to restore page table to absent/execute-disable state\r | |
1500 | in order to trigger page fault again to save SMM profile data..\r | |
1501 | \r | |
1502 | **/\r | |
1503 | VOID\r | |
1504 | InitIdtr (\r | |
1505 | VOID\r | |
1506 | )\r | |
1507 | {\r | |
5c88af79 JF |
1508 | EFI_STATUS Status;\r |
1509 | \r | |
1510 | Status = SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_DEBUG, DebugExceptionHandler);\r | |
1511 | ASSERT_EFI_ERROR (Status);\r | |
529a5a86 | 1512 | }\r |