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529a5a86 MK |
1 | /** @file\r |
2 | SMM profile internal header file.\r | |
3 | \r | |
4c214f82 | 4 | Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>\r |
529a5a86 MK |
5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef _SMM_PROFILE_INTERNAL_H_\r | |
16 | #define _SMM_PROFILE_INTERNAL_H_\r | |
17 | \r | |
529a5a86 MK |
18 | #include <Protocol/SmmReadyToLock.h>\r |
19 | #include <Library/UefiRuntimeServicesTableLib.h>\r | |
20 | #include <Library/DxeServicesTableLib.h>\r | |
21 | #include <Library/CpuLib.h>\r | |
22 | #include <IndustryStandard/Acpi.h>\r | |
23 | \r | |
24 | #include "SmmProfileArch.h"\r | |
25 | \r | |
26 | //\r | |
27 | // Configure the SMM_PROFILE DTS region size\r | |
28 | //\r | |
29 | #define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M\r | |
30 | \r | |
31 | #define MAX_PF_PAGE_COUNT 0x2\r | |
32 | \r | |
33 | #define PEBS_RECORD_NUMBER 0x2\r | |
34 | \r | |
35 | #define MAX_PF_ENTRY_COUNT 10\r | |
36 | \r | |
37 | //\r | |
38 | // This MACRO just enable unit test for the profile\r | |
39 | // Please disable it.\r | |
40 | //\r | |
41 | \r | |
529a5a86 MK |
42 | #define IA32_PF_EC_ID (1u << 4)\r |
43 | \r | |
44 | #define SMM_PROFILE_NAME L"SmmProfileData"\r | |
45 | \r | |
46 | //\r | |
47 | // CPU generic definition\r | |
48 | //\r | |
49 | #define CPUID1_EDX_XD_SUPPORT 0x100000\r | |
50 | #define MSR_EFER 0xc0000080\r | |
51 | #define MSR_EFER_XD 0x800\r | |
52 | \r | |
53 | #define CPUID1_EDX_BTS_AVAILABLE 0x200000\r | |
54 | \r | |
55 | #define DR6_SINGLE_STEP 0x4000\r | |
56 | #define RFLAG_TF 0x100\r | |
57 | \r | |
58 | #define MSR_DEBUG_CTL 0x1D9\r | |
59 | #define MSR_DEBUG_CTL_LBR 0x1\r | |
60 | #define MSR_DEBUG_CTL_TR 0x40\r | |
61 | #define MSR_DEBUG_CTL_BTS 0x80\r | |
62 | #define MSR_DEBUG_CTL_BTINT 0x100\r | |
529a5a86 MK |
63 | #define MSR_DS_AREA 0x600\r |
64 | \r | |
09afd9a4 JW |
65 | #define HEAP_GUARD_NONSTOP_MODE \\r |
66 | ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6)\r | |
67 | \r | |
68 | #define NULL_DETECTION_NONSTOP_MODE \\r | |
69 | ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT1)) > BIT6)\r | |
70 | \r | |
529a5a86 MK |
71 | typedef struct {\r |
72 | EFI_PHYSICAL_ADDRESS Base;\r | |
73 | EFI_PHYSICAL_ADDRESS Top;\r | |
74 | } MEMORY_RANGE;\r | |
75 | \r | |
76 | typedef struct {\r | |
77 | MEMORY_RANGE Range;\r | |
78 | BOOLEAN Present;\r | |
79 | BOOLEAN Nx;\r | |
80 | } MEMORY_PROTECTION_RANGE;\r | |
81 | \r | |
82 | typedef struct {\r | |
83 | UINT64 HeaderSize;\r | |
84 | UINT64 MaxDataEntries;\r | |
85 | UINT64 MaxDataSize;\r | |
86 | UINT64 CurDataEntries;\r | |
87 | UINT64 CurDataSize;\r | |
88 | UINT64 TsegStart;\r | |
89 | UINT64 TsegSize;\r | |
90 | UINT64 NumSmis;\r | |
91 | UINT64 NumCpus;\r | |
92 | } SMM_PROFILE_HEADER;\r | |
93 | \r | |
94 | typedef struct {\r | |
95 | UINT64 SmiNum;\r | |
96 | UINT64 CpuNum;\r | |
97 | UINT64 ApicId;\r | |
98 | UINT64 ErrorCode;\r | |
99 | UINT64 Instruction;\r | |
100 | UINT64 Address;\r | |
101 | UINT64 SmiCmd;\r | |
102 | } SMM_PROFILE_ENTRY;\r | |
103 | \r | |
104 | extern SMM_S3_RESUME_STATE *mSmmS3ResumeState;\r | |
105 | extern UINTN gSmiExceptionHandlers[];\r | |
106 | extern BOOLEAN mXdSupported;\r | |
3c5ce64f | 107 | X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported;\r |
529a5a86 MK |
108 | extern UINTN *mPFEntryCount;\r |
109 | extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];\r | |
110 | extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];\r | |
111 | \r | |
112 | //\r | |
113 | // Internal functions\r | |
114 | //\r | |
115 | \r | |
116 | /**\r | |
117 | Update IDT table to replace page fault handler and INT 1 handler.\r | |
118 | \r | |
119 | **/\r | |
120 | VOID\r | |
121 | InitIdtr (\r | |
122 | VOID\r | |
123 | );\r | |
124 | \r | |
125 | /**\r | |
126 | Check if the memory address will be mapped by 4KB-page.\r | |
127 | \r | |
128 | @param Address The address of Memory.\r | |
129 | \r | |
130 | **/\r | |
131 | BOOLEAN\r | |
132 | IsAddressSplit (\r | |
133 | IN EFI_PHYSICAL_ADDRESS Address\r | |
134 | );\r | |
135 | \r | |
136 | /**\r | |
137 | Check if the memory address will be mapped by 4KB-page.\r | |
138 | \r | |
139 | @param Address The address of Memory.\r | |
140 | @param Nx The flag indicates if the memory is execute-disable.\r | |
141 | \r | |
142 | **/\r | |
143 | BOOLEAN\r | |
144 | IsAddressValid (\r | |
145 | IN EFI_PHYSICAL_ADDRESS Address,\r | |
146 | IN BOOLEAN *Nx\r | |
147 | );\r | |
148 | \r | |
149 | /**\r | |
150 | Page Fault handler for SMM use.\r | |
151 | \r | |
152 | **/\r | |
153 | VOID\r | |
154 | SmiDefaultPFHandler (\r | |
155 | VOID\r | |
156 | );\r | |
157 | \r | |
158 | /**\r | |
159 | Clear TF in FLAGS.\r | |
160 | \r | |
161 | @param SystemContext A pointer to the processor context when\r | |
162 | the interrupt occurred on the processor.\r | |
163 | \r | |
164 | **/\r | |
165 | VOID\r | |
166 | ClearTrapFlag (\r | |
167 | IN OUT EFI_SYSTEM_CONTEXT SystemContext\r | |
168 | );\r | |
169 | \r | |
170 | #endif // _SMM_PROFILE_H_\r |