]>
Commit | Line | Data |
---|---|---|
9a36d4dc LG |
1 | ;------------------------------------------------------------------------------ ;\r |
2 | ; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
3 | ; This program and the accompanying materials\r | |
4 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
5 | ; which accompanies this distribution. The full text of the license may be found at\r | |
6 | ; http://opensource.org/licenses/bsd-license.php.\r | |
7 | ;\r | |
8 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
9 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
10 | ;\r | |
11 | ; Module Name:\r | |
12 | ;\r | |
13 | ; SmiEntry.nasm\r | |
14 | ;\r | |
15 | ; Abstract:\r | |
16 | ;\r | |
17 | ; Code template of the SMI handler for a particular processor\r | |
18 | ;\r | |
19 | ;-------------------------------------------------------------------------------\r | |
20 | \r | |
21 | ;\r | |
22 | ; Variables referrenced by C code\r | |
23 | ;\r | |
24 | \r | |
25 | ;\r | |
26 | ; Constants relating to PROCESSOR_SMM_DESCRIPTOR\r | |
27 | ;\r | |
28 | %define DSC_OFFSET 0xfb00\r | |
29 | %define DSC_GDTPTR 0x30\r | |
30 | %define DSC_GDTSIZ 0x38\r | |
31 | %define DSC_CS 14\r | |
32 | %define DSC_DS 16\r | |
33 | %define DSC_SS 18\r | |
34 | %define DSC_OTHERSEG 20\r | |
35 | ;\r | |
36 | ; Constants relating to CPU State Save Area\r | |
37 | ;\r | |
38 | %define SSM_DR6 0xffd0\r | |
39 | %define SSM_DR7 0xffc8\r | |
40 | \r | |
41 | %define PROTECT_MODE_CS 0x8\r | |
42 | %define PROTECT_MODE_DS 0x20\r | |
43 | %define LONG_MODE_CS 0x38\r | |
44 | %define TSS_SEGMENT 0x40\r | |
45 | %define GDT_SIZE 0x50\r | |
46 | \r | |
47 | extern ASM_PFX(SmiRendezvous)\r | |
48 | extern ASM_PFX(gSmiHandlerIdtr)\r | |
49 | extern ASM_PFX(CpuSmmDebugEntry)\r | |
50 | extern ASM_PFX(CpuSmmDebugExit)\r | |
51 | \r | |
52 | global ASM_PFX(gSmbase)\r | |
53 | global ASM_PFX(gSmiStack)\r | |
54 | global ASM_PFX(gSmiCr3)\r | |
55 | global ASM_PFX(gcSmiHandlerTemplate)\r | |
56 | global ASM_PFX(gcSmiHandlerSize)\r | |
57 | \r | |
58 | DEFAULT REL\r | |
59 | SECTION .text\r | |
60 | \r | |
61 | BITS 16\r | |
62 | ASM_PFX(gcSmiHandlerTemplate):\r | |
63 | _SmiEntryPoint:\r | |
64 | mov bx, _GdtDesc - _SmiEntryPoint + 0x8000\r | |
65 | mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]\r | |
66 | dec ax\r | |
67 | mov [cs:bx], ax\r | |
68 | mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]\r | |
69 | mov [cs:bx + 2], eax\r | |
70 | o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]\r | |
71 | mov ax, PROTECT_MODE_CS\r | |
72 | mov [cs:bx-0x2],ax \r | |
73 | DB 0x66, 0xbf ; mov edi, SMBASE\r | |
74 | ASM_PFX(gSmbase): DD 0\r | |
75 | lea eax, [edi + (@ProtectedMode - _SmiEntryPoint) + 0x8000]\r | |
76 | mov [cs:bx-0x6],eax\r | |
77 | mov ebx, cr0\r | |
78 | and ebx, 0x9ffafff3\r | |
79 | or ebx, 0x23\r | |
80 | mov cr0, ebx\r | |
81 | jmp dword 0x0:0x0\r | |
82 | _GdtDesc: \r | |
83 | DW 0\r | |
84 | DD 0\r | |
85 | \r | |
86 | BITS 32\r | |
87 | @ProtectedMode:\r | |
88 | mov ax, PROTECT_MODE_DS\r | |
89 | o16 mov ds, ax\r | |
90 | o16 mov es, ax\r | |
91 | o16 mov fs, ax\r | |
92 | o16 mov gs, ax\r | |
93 | o16 mov ss, ax\r | |
94 | DB 0xbc ; mov esp, imm32\r | |
95 | ASM_PFX(gSmiStack): DD 0\r | |
96 | jmp ProtFlatMode\r | |
97 | \r | |
98 | BITS 64\r | |
99 | ProtFlatMode:\r | |
100 | DB 0xb8 ; mov eax, offset gSmiCr3\r | |
101 | ASM_PFX(gSmiCr3): DD 0\r | |
102 | mov cr3, rax\r | |
103 | mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3\r | |
104 | mov cr4, rax ; in PreModifyMtrrs() to flush TLB.\r | |
105 | ; Load TSS\r | |
106 | sub esp, 8 ; reserve room in stack\r | |
107 | sgdt [rsp]\r | |
108 | mov eax, [rsp + 2] ; eax = GDT base\r | |
109 | add esp, 8\r | |
110 | mov dl, 0x89\r | |
111 | mov [rax + TSS_SEGMENT + 5], dl ; clear busy flag\r | |
112 | mov eax, TSS_SEGMENT\r | |
113 | ltr ax\r | |
114 | \r | |
115 | ; Switch into @LongMode\r | |
116 | push LONG_MODE_CS ; push cs hardcore here\r | |
117 | call Base ; push reture address for retf later\r | |
118 | Base:\r | |
119 | add dword [rsp], @LongMode - Base; offset for far retf, seg is the 1st arg\r | |
120 | mov ecx, 0xc0000080\r | |
121 | rdmsr\r | |
122 | or ah, 1\r | |
123 | wrmsr\r | |
124 | mov rbx, cr0\r | |
125 | or ebx, 080010000h ; enable paging + WP\r | |
126 | mov cr0, rbx\r | |
127 | retf\r | |
128 | @LongMode: ; long mode (64-bit code) starts here\r | |
129 | mov rax, ASM_PFX(gSmiHandlerIdtr)\r | |
130 | lidt [rax]\r | |
131 | lea ebx, [rdi + DSC_OFFSET]\r | |
132 | mov ax, [rbx + DSC_DS]\r | |
133 | mov ds, eax\r | |
134 | mov ax, [rbx + DSC_OTHERSEG]\r | |
135 | mov es, eax\r | |
136 | mov fs, eax\r | |
137 | mov gs, eax\r | |
138 | mov ax, [rbx + DSC_SS]\r | |
139 | mov ss, eax\r | |
140 | ; jmp _SmiHandler ; instruction is not needed\r | |
141 | \r | |
142 | _SmiHandler:\r | |
143 | mov rbx, [rsp] ; rbx <- CpuIndex\r | |
144 | \r | |
145 | ;\r | |
146 | ; Save FP registers\r | |
147 | ;\r | |
148 | sub rsp, 0x208\r | |
149 | DB 0x48 ; FXSAVE64\r | |
150 | fxsave [rsp]\r | |
151 | \r | |
152 | add rsp, -0x20\r | |
153 | \r | |
154 | mov rcx, rbx\r | |
155 | mov rax, CpuSmmDebugEntry\r | |
156 | call rax\r | |
157 | \r | |
158 | mov rcx, rbx\r | |
159 | mov rax, SmiRendezvous ; rax <- absolute addr of SmiRedezvous\r | |
160 | call rax\r | |
161 | \r | |
162 | mov rcx, rbx\r | |
163 | mov rax, CpuSmmDebugExit\r | |
164 | call rax\r | |
165 | \r | |
166 | add rsp, 0x20\r | |
167 | \r | |
168 | ;\r | |
169 | ; Restore FP registers\r | |
170 | ;\r | |
171 | DB 0x48 ; FXRSTOR64\r | |
172 | fxrstor [rsp]\r | |
173 | \r | |
174 | rsm\r | |
175 | \r | |
176 | gcSmiHandlerSize DW $ - _SmiEntryPoint\r | |
177 | \r |