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1 | ;------------------------------------------------------------------------------\r |
2 | ; @file\r | |
3 | ; Serial port debug support macros\r | |
4 | ;\r | |
7367cc6c | 5 | ; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 6 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
bc252e8e EB |
7 | ;\r |
8 | ;------------------------------------------------------------------------------\r | |
9 | \r | |
10 | ;//---------------------------------------------\r | |
11 | ;// UART Register Offsets\r | |
12 | ;//---------------------------------------------\r | |
13 | %define BAUD_LOW_OFFSET 0x00\r | |
14 | %define BAUD_HIGH_OFFSET 0x01\r | |
15 | %define IER_OFFSET 0x01\r | |
16 | %define LCR_SHADOW_OFFSET 0x01\r | |
17 | %define FCR_SHADOW_OFFSET 0x02\r | |
18 | %define IR_CONTROL_OFFSET 0x02\r | |
19 | %define FCR_OFFSET 0x02\r | |
20 | %define EIR_OFFSET 0x02\r | |
21 | %define BSR_OFFSET 0x03\r | |
22 | %define LCR_OFFSET 0x03\r | |
23 | %define MCR_OFFSET 0x04\r | |
24 | %define LSR_OFFSET 0x05\r | |
25 | %define MSR_OFFSET 0x06\r | |
26 | \r | |
27 | ;//---------------------------------------------\r | |
28 | ;// UART Register Bit Defines\r | |
29 | ;//---------------------------------------------\r | |
30 | %define LSR_TXRDY 0x20\r | |
31 | %define LSR_RXDA 0x01\r | |
32 | %define DLAB 0x01\r | |
33 | \r | |
34 | ; UINT16 gComBase = 0x3f8;\r | |
35 | ; UINTN gBps = 115200;\r | |
36 | ; UINT8 gData = 8;\r | |
37 | ; UINT8 gStop = 1;\r | |
38 | ; UINT8 gParity = 0;\r | |
39 | ; UINT8 gBreakSet = 0;\r | |
40 | \r | |
41 | %define DEFAULT_COM_BASE 0x3f8\r | |
42 | %define DEFAULT_BPS 115200\r | |
43 | %define DEFAULT_DATA 8\r | |
44 | %define DEFAULT_STOP 1\r | |
45 | %define DEFAULT_PARITY 0\r | |
46 | %define DEFAULT_BREAK_SET 0\r | |
47 | \r | |
48 | %define SERIAL_DEFAULT_LCR ( \\r | |
49 | (DEFAULT_BREAK_SET << 6) | \\r | |
50 | (DEFAULT_PARITY << 3) | \\r | |
51 | (DEFAULT_STOP << 2) | \\r | |
52 | (DEFAULT_DATA - 5) \\r | |
53 | )\r | |
54 | \r | |
55 | %define SERIAL_PORT_IO_BASE_ADDRESS DEFAULT_COM_BASE\r | |
56 | \r | |
57 | %macro inFromSerialPort 1\r | |
58 | mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)\r | |
59 | in al, dx\r | |
60 | %endmacro\r | |
61 | \r | |
62 | %macro waitForSerialTxReady 0\r | |
63 | \r | |
64 | %%waitingForTx:\r | |
65 | inFromSerialPort LSR_OFFSET\r | |
66 | test al, LSR_TXRDY\r | |
67 | jz %%waitingForTx\r | |
68 | \r | |
69 | %endmacro\r | |
70 | \r | |
71 | %macro outToSerialPort 2\r | |
72 | mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)\r | |
73 | mov al, %2\r | |
74 | out dx, al\r | |
75 | %endmacro\r | |
76 | \r | |
77 | %macro debugShowCharacter 1\r | |
78 | waitForSerialTxReady\r | |
79 | outToSerialPort 0, %1\r | |
80 | %endmacro\r | |
81 | \r | |
82 | %macro debugShowHexDigit 1\r | |
83 | %if (%1 < 0xa)\r | |
84 | debugShowCharacter BYTE ('0' + (%1))\r | |
85 | %else\r | |
86 | debugShowCharacter BYTE ('a' + ((%1) - 0xa))\r | |
87 | %endif\r | |
88 | %endmacro\r | |
89 | \r | |
90 | %macro debugNewline 0\r | |
91 | debugShowCharacter `\r`\r | |
92 | debugShowCharacter `\n`\r | |
93 | %endmacro\r | |
94 | \r | |
95 | %macro debugShowPostCode 1\r | |
96 | debugShowHexDigit (((%1) >> 4) & 0xf)\r | |
97 | debugShowHexDigit ((%1) & 0xf)\r | |
98 | debugNewline\r | |
99 | %endmacro\r | |
100 | \r | |
101 | BITS 16\r | |
102 | \r | |
103 | %macro debugInitialize 0\r | |
7367cc6c | 104 | jmp real16InitDebug\r |
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105 | real16InitDebugReturn:\r |
106 | %endmacro\r | |
107 | \r | |
108 | real16InitDebug:\r | |
109 | ;\r | |
110 | ; Set communications format\r | |
111 | ;\r | |
112 | outToSerialPort LCR_OFFSET, ((DLAB << 7) | SERIAL_DEFAULT_LCR)\r | |
113 | \r | |
114 | ;\r | |
115 | ; Configure baud rate\r | |
116 | ;\r | |
117 | outToSerialPort BAUD_HIGH_OFFSET, ((115200 / DEFAULT_BPS) >> 8)\r | |
118 | outToSerialPort BAUD_LOW_OFFSET, ((115200 / DEFAULT_BPS) & 0xff)\r | |
119 | \r | |
120 | ;\r | |
121 | ; Switch back to bank 0\r | |
122 | ;\r | |
123 | outToSerialPort LCR_OFFSET, SERIAL_DEFAULT_LCR\r | |
124 | \r | |
125 | jmp real16InitDebugReturn\r | |
126 | \r |