UefiPayloadPkg: Add SpiFlashLib

[mirror_edk2.git] / UefiPayloadPkg / Library / SpiFlashLib / PchSpi.c

/** @file\r
\r
  Copyright (c) 2017-2021, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
#include "SpiCommon.h"\r
\r
/**\r
  Acquire SPI MMIO BAR.\r
\r
  @param[in] PchSpiBase           PCH SPI PCI Base Address\r
\r
  @retval                         Return SPI BAR Address\r
\r
**/\r
UINT32\r
AcquireSpiBar0 (\r
  IN  UINTN         PchSpiBase\r
  )\r
{\r
  return MmioRead32 (PchSpiBase + R_SPI_BASE) & ~(B_SPI_BAR0_MASK);\r
}\r
\r
/**\r
  Release SPI MMIO BAR. Do nothing.\r
\r
  @param[in] PchSpiBase           PCH SPI PCI Base Address\r
\r
**/\r
VOID\r
ReleaseSpiBar0 (\r
  IN  UINTN         PchSpiBase\r
  )\r
{\r
}\r
\r
\r
\r
/**\r
  This function is to enable/disable BIOS Write Protect in SMM phase.\r
\r
  @param[in] EnableSmmSts        Flag to Enable/disable Bios write protect\r
\r
**/\r
VOID\r
CpuSmmDisableBiosWriteProtect (\r
   IN  BOOLEAN   EnableSmmSts\r
  )\r
{\r
  UINT32      Data32;\r
\r
  if(EnableSmmSts){\r
    //\r
    // Disable BIOS Write Protect in SMM phase.\r
    //\r
    Data32 = MmioRead32 ((UINTN) (0xFED30880)) | (UINT32) (BIT0);\r
    AsmWriteMsr32 (0x000001FE, Data32);\r
  } else {\r
    //\r
    // Enable BIOS Write Protect in SMM phase\r
    //\r
    Data32 = MmioRead32 ((UINTN) (0xFED30880)) & (UINT32) (~BIT0);\r
    AsmWriteMsr32 (0x000001FE, Data32);\r
  }\r
\r
  //\r
  // Read FED30880h back to ensure the setting went through.\r
  //\r
  Data32 = MmioRead32 (0xFED30880);\r
}\r
\r
\r
/**\r
  This function is a hook for Spi to disable BIOS Write Protect.\r
\r
  @param[in] PchSpiBase           PCH SPI PCI Base Address\r
  @param[in] CpuSmmBwp            Need to disable CPU SMM Bios write protection or not\r
\r
  @retval EFI_SUCCESS             The protocol instance was properly initialized\r
  @retval EFI_ACCESS_DENIED       The BIOS Region can only be updated in SMM phase\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
DisableBiosWriteProtect (\r
  IN  UINTN         PchSpiBase,\r
  IN  UINT8         CpuSmmBwp\r
  )\r
{\r
\r
  //\r
  // Write clear BC_SYNC_SS prior to change WPD from 0 to 1.\r
  //\r
  MmioOr8 (PchSpiBase + R_SPI_BCR + 1, (B_SPI_BCR_SYNC_SS >> 8));\r
\r
  //\r
  // Enable the access to the BIOS space for both read and write cycles\r
  //\r
  MmioOr8 (PchSpiBase + R_SPI_BCR, B_SPI_BCR_BIOSWE);\r
\r
  if (CpuSmmBwp != 0) {\r
    CpuSmmDisableBiosWriteProtect (TRUE);\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  This function is a hook for Spi to enable BIOS Write Protect.\r
\r
  @param[in] PchSpiBase           PCH SPI PCI Base Address\r
  @param[in] CpuSmmBwp            Need to disable CPU SMM Bios write protection or not\r
\r
**/\r
VOID\r
EFIAPI\r
EnableBiosWriteProtect (\r
  IN  UINTN         PchSpiBase,\r
  IN  UINT8         CpuSmmBwp\r
  )\r
{\r
\r
  //\r
  // Disable the access to the BIOS space for write cycles\r
  //\r
  MmioAnd8 (PchSpiBase + R_SPI_BCR, (UINT8) (~B_SPI_BCR_BIOSWE));\r
\r
  if (CpuSmmBwp != 0) {\r
    CpuSmmDisableBiosWriteProtect (FALSE);\r
  }\r
}\r
\r
/**\r
  This function disables SPI Prefetching and caching,\r
  and returns previous BIOS Control Register value before disabling.\r
\r
  @param[in] PchSpiBase           PCH SPI PCI Base Address\r
\r
  @retval                         Previous BIOS Control Register value\r
\r
**/\r
UINT8\r
SaveAndDisableSpiPrefetchCache (\r
  IN  UINTN         PchSpiBase\r
  )\r
{\r
  UINT8           BiosCtlSave;\r
\r
  BiosCtlSave = MmioRead8 (PchSpiBase + R_SPI_BCR) & B_SPI_BCR_SRC;\r
\r
  MmioAndThenOr32 (PchSpiBase + R_SPI_BCR, \\r
    (UINT32) (~B_SPI_BCR_SRC), \\r
    (UINT32) (V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS <<  B_SPI_BCR_SRC));\r
\r
  return BiosCtlSave;\r
}\r
\r
/**\r
  This function updates BIOS Control Register with the given value.\r
\r
  @param[in] PchSpiBase           PCH SPI PCI Base Address\r
  @param[in] BiosCtlValue         BIOS Control Register Value to be updated\r
\r
**/\r
VOID\r
SetSpiBiosControlRegister (\r
  IN  UINTN         PchSpiBase,\r
  IN  UINT8         BiosCtlValue\r
  )\r
{\r
  MmioAndThenOr8 (PchSpiBase + R_SPI_BCR, (UINT8) ~B_SPI_BCR_SRC, BiosCtlValue);\r
}\r