projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /**************************************************************************;\r |
| 2 | ;* *;\r | |
| 3 | ;* *;\r | |
| 4 | ;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r | |
| 5 | ;* Family of Customer Reference Boards. *;\r | |
| 6 | ;* *;\r | |
| 7 | ;* *;\r | |
| 8 | ;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r | |
| 9 | ;\r | |
| 7ede8060 | 10 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
11 | ;\r |
| 12 | ;* *;\r | |
| 13 | ;* *;\r | |
| 14 | ;**************************************************************************/\r | |
| 15 | \r | |
| 16 | \r | |
| 17 | // General Purpose Events. This Scope handles the Run-time and\r | |
| 18 | // Wake-time SCIs. The specific method called will be determined by\r | |
| 19 | // the _Lxx value, where xx equals the bit location in the General\r | |
| 20 | // Purpose Event register(s).\r | |
| 21 | \r | |
| 22 | Scope(\_GPE)\r | |
| 23 | {\r | |
| 24 | //\r | |
| 25 | // Software GPE caused the event.\r | |
| 26 | //\r | |
| 27 | Method(_L02)\r | |
| 28 | {\r | |
| 29 | // Clear GPE status bit.\r | |
| 30 | Store(0,GPEC)\r | |
| 31 | //\r | |
| 32 | // Handle DTS Thermal Events.\r | |
| 33 | //\r | |
| 34 | External(DTSE, IntObj)\r | |
| 35 | If(CondRefOf(DTSE))\r | |
| 36 | {\r | |
| 37 | If(LGreaterEqual(DTSE, 0x01))\r | |
| 38 | {\r | |
| 39 | Notify(\_TZ.TZ01,0x80)\r | |
| 40 | }\r | |
| 41 | }\r | |
| 42 | }\r | |
| 43 | \r | |
| 44 | //\r | |
| 45 | // PUNIT SCI event.\r | |
| 46 | //\r | |
| 47 | Method(_L04)\r | |
| 48 | {\r | |
| 49 | // Clear the PUNIT Status Bit.\r | |
| 50 | Store(1, PSCI)\r | |
| 51 | }\r | |
| 52 | \r | |
| 53 | \r | |
| 54 | //\r | |
| 55 | // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC).\r | |
| 56 | //\r | |
| 57 | Method(_L05)\r | |
| 58 | {\r | |
| 59 | If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI event?\r | |
| 60 | {\r | |
| 61 | \_SB.PCI0.GFX0.GSCI() // Handle the SWSCI\r | |
| 62 | }\r | |
| 63 | }\r | |
| 64 | \r | |
| 65 | //\r | |
| 66 | // This PME event (PCH's GPE #13) is received when any PCH internal device with PCI Power Management capabilities\r | |
| 67 | // on bus 0 asserts the equivalent of the PME# signal.\r | |
| 68 | //\r | |
| 69 | Method(_L0D, 0)\r | |
| 70 | {\r | |
| 71 | If(LAnd(\_SB.PCI0.EHC1.PMEE, \_SB.PCI0.EHC1.PMES))\r | |
| 72 | {\r | |
| 73 | If(LNotEqual(OSEL, 1))\r | |
| 74 | {\r | |
| 75 | Store(1, \_SB.PCI0.EHC1.PMES) //Clear PME status\r | |
| 76 | Store(0, \_SB.PCI0.EHC1.PMEE) //Disable PME\r | |
| 77 | }\r | |
| 78 | Notify(\_SB.PCI0.EHC1, 0x02)\r | |
| 79 | }\r | |
| 80 | If(LAnd(\_SB.PCI0.XHC1.PMEE, \_SB.PCI0.XHC1.PMES))\r | |
| 81 | {\r | |
| 82 | If(LNotEqual(OSEL, 1))\r | |
| 83 | {\r | |
| 84 | Store(1, \_SB.PCI0.XHC1.PMES) //Clear PME status\r | |
| 85 | Store(0, \_SB.PCI0.XHC1.PMEE) //Disable PME\r | |
| 86 | }\r | |
| 87 | Notify(\_SB.PCI0.XHC1, 0x02)\r | |
| 88 | }\r | |
| 89 | If(LAnd(\_SB.PCI0.HDEF.PMEE, \_SB.PCI0.HDEF.PMES))\r | |
| 90 | {\r | |
| 91 | If(LNotEqual(OSEL, 1))\r | |
| 92 | {\r | |
| 93 | Store(1, \_SB.PCI0.HDEF.PMES) //Clear PME status\r | |
| 94 | Store(0, \_SB.PCI0.HDEF.PMEE) //Disable PME\r | |
| 95 | }\r | |
| 96 | Notify(\_SB.PCI0.HDEF, 0x02)\r | |
| 97 | }\r | |
| 98 | }\r | |
| 99 | }\r |