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3cbfba02 DW |
1 | /**************************************************************************;\r |
2 | ;* *;\r | |
3 | ;* *;\r | |
4 | ;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r | |
5 | ;* Family of Customer Reference Boards. *;\r | |
6 | ;* *;\r | |
7 | ;* *;\r | |
8 | ;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r | |
9 | ;\r | |
7ede8060 | 10 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
3cbfba02 DW |
11 | ;\r |
12 | ;* *;\r | |
13 | ;* *;\r | |
14 | ;**************************************************************************/\r | |
15 | \r | |
16 | \r | |
17 | // LPC Bridge - Device 31, Function 0\r | |
18 | // Define the needed LPC registers used by ASL.\r | |
19 | \r | |
20 | scope(\_SB)\r | |
21 | {\r | |
22 | OperationRegion(ILBR, SystemMemory, \IBAS, 0x8C)\r | |
23 | Field(ILBR, AnyAcc, NoLock, Preserve)\r | |
24 | {\r | |
25 | Offset(0x08), // 0x08\r | |
26 | PARC, 8,\r | |
27 | PBRC, 8,\r | |
28 | PCRC, 8,\r | |
29 | PDRC, 8,\r | |
30 | PERC, 8,\r | |
31 | PFRC, 8,\r | |
32 | PGRC, 8,\r | |
33 | PHRC, 8,\r | |
34 | Offset(0x88), // 0x88\r | |
35 | , 3,\r | |
36 | UI3E, 1,\r | |
37 | UI4E, 1\r | |
38 | }\r | |
39 | \r | |
40 | Include ("98_LINK.ASL")\r | |
41 | }\r | |
42 | \r | |
43 | OperationRegion(LPC0, PCI_Config, 0x00, 0xC0)\r | |
44 | Field(LPC0, AnyAcc, NoLock, Preserve)\r | |
45 | {\r | |
46 | Offset(0x08), // 0x08\r | |
47 | SRID, 8, // Revision ID\r | |
48 | Offset(0x080), // 0x80\r | |
49 | C1EN, 1, // COM1 Enable\r | |
50 | , 31\r | |
51 | }\r | |
52 | \r | |
53 | \r | |
54 | Include ("LPC_DEV.ASL")\r | |
55 | \r | |
56 | \r | |
57 | \r | |
58 | \r | |
59 | \r |