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1 | /**************************************************************************;\r |
2 | ;* *;\r | |
3 | ;* *;\r | |
4 | ;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r | |
5 | ;* Family of Customer Reference Boards. *;\r | |
6 | ;* *;\r | |
7 | ;* *;\r | |
8 | ;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r | |
9 | ;\r | |
10 | ; This program and the accompanying materials are licensed and made available under\r | |
11 | ; the terms and conditions of the BSD License that accompanies this distribution.\r | |
12 | ; The full text of the license may be found at\r | |
13 | ; http://opensource.org/licenses/bsd-license.php.\r | |
14 | ;\r | |
15 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | ;\r | |
18 | ;* *;\r | |
19 | ;* *;\r | |
20 | ;**************************************************************************/\r | |
21 | \r | |
22 | \r | |
23 | Scope(\)\r | |
24 | {\r | |
25 | //\r | |
26 | // Define VLV ABASE I/O as an ACPI operating region. The base address\r | |
27 | // can be found in Device 31, Registers 40-43h.\r | |
28 | //\r | |
29 | OperationRegion(PMIO, SystemIo, \PMBS, 0x46)\r | |
30 | Field(PMIO, ByteAcc, NoLock, Preserve)\r | |
31 | {\r | |
32 | , 8,\r | |
33 | PWBS, 1, // Power Button Status\r | |
34 | Offset(0x20),\r | |
35 | , 13,\r | |
36 | PMEB, 1, // PME_B0_STS\r | |
37 | Offset(0x42), // General Purpose Control\r | |
38 | , 1,\r | |
39 | GPEC, 1\r | |
40 | }\r | |
41 | Field(PMIO, ByteAcc, NoLock, WriteAsZeros)\r | |
42 | {\r | |
43 | Offset(0x20), // GPE0 Status\r | |
44 | , 4,\r | |
45 | PSCI, 1, // PUNIT SCI Status\r | |
46 | SCIS, 1 // GUNIT SCI Status\r | |
47 | }\r | |
48 | \r | |
49 | \r | |
50 | \r | |
51 | //\r | |
52 | // Define a Memory Region that will allow access to the PMC\r | |
53 | // Register Block. Note that in the Intel Reference Solution, the PMC\r | |
54 | // will get fixed up dynamically during POST.\r | |
55 | //\r | |
56 | OperationRegion(PMCR, SystemMemory, \PFDR, 0x04)// PMC Function Disable Register\r | |
57 | Field(PMCR,DWordAcc,Lock,Preserve)\r | |
58 | {\r | |
59 | Offset(0x00), // Function Disable Register\r | |
60 | L10D, 1, // (0) LPIO1 DMA Disable\r | |
61 | L11D, 1, // (1) LPIO1 PWM #1 Disable\r | |
62 | L12D, 1, // (2) LPIO1 PWM #2 Disable\r | |
63 | L13D, 1, // (3) LPIO1 HS-UART #1 Disable\r | |
64 | L14D, 1, // (4) LPIO1 HS-UART #2 Disable\r | |
65 | L15D, 1, // (5) LPIO1 SPI Disable\r | |
66 | , 2, // (6:7) Reserved\r | |
67 | SD1D, 1, // (8) SCC SDIO #1 Disable\r | |
68 | SD2D, 1, // (9) SCC SDIO #2 Disable\r | |
69 | SD3D, 1, // (10) SCC SDIO #3 Disable\r | |
70 | HSID, 1, // (11)\r | |
71 | HDAD, 1, // (12) Azalia Disable\r | |
72 | LPED, 1, // (13) LPE Disable\r | |
73 | OTGD, 1, // (14) USB OTG Disable\r | |
74 | , 1, // (15) USH Disable\r | |
75 | , 1, // (16)\r | |
76 | , 1, // (17)\r | |
77 | , 1, // (18) USB Disable\r | |
78 | , 1, // (19) SEC Disable\r | |
79 | RP1D, 1, // (20) Root Port 0 Disable\r | |
80 | RP2D, 1, // (21) Root Port 1 Disable\r | |
81 | RP3D, 1, // (22) Root Port 2 Disable\r | |
82 | RP4D, 1, // (23) Root Port 3 Disable\r | |
83 | L20D, 1, // (24) LPIO2 DMA Disable\r | |
84 | L21D, 1, // (25) LPIO2 I2C #1 Disable\r | |
85 | L22D, 1, // (26) LPIO2 I2C #2 Disable\r | |
86 | L23D, 1, // (27) LPIO2 I2C #3 Disable\r | |
87 | L24D, 1, // (28) LPIO2 I2C #4 Disable\r | |
88 | L25D, 1, // (29) LPIO2 I2C #5 Disable\r | |
89 | L26D, 1, // (30) LPIO2 I2C #6 Disable\r | |
90 | L27D, 1 // (31) LPIO2 I2C #7 Disable\r | |
91 | }\r | |
92 | \r | |
93 | \r | |
94 | OperationRegion(CLKC, SystemMemory, \PCLK, 0x18)// PMC CLK CTL Registers\r | |
95 | Field(CLKC,DWordAcc,Lock,Preserve)\r | |
96 | {\r | |
97 | Offset(0x00), // PLT_CLK_CTL_0\r | |
98 | CKC0, 2,\r | |
99 | CKF0, 1,\r | |
100 | , 29,\r | |
101 | Offset(0x04), // PLT_CLK_CTL_1\r | |
102 | CKC1, 2,\r | |
103 | CKF1, 1,\r | |
104 | , 29,\r | |
105 | Offset(0x08), // PLT_CLK_CTL_2\r | |
106 | CKC2, 2,\r | |
107 | CKF2, 1,\r | |
108 | , 29,\r | |
109 | Offset(0x0C), // PLT_CLK_CTL_3\r | |
110 | CKC3, 2,\r | |
111 | CKF3, 1,\r | |
112 | , 29,\r | |
113 | Offset(0x10), // PLT_CLK_CTL_4\r | |
114 | CKC4, 2,\r | |
115 | CKF4, 1,\r | |
116 | , 29,\r | |
117 | Offset(0x14), // PLT_CLK_CTL_5\r | |
118 | CKC5, 2,\r | |
119 | CKF5, 1,\r | |
120 | , 29,\r | |
121 | }\r | |
122 | } //end Scope(\)\r | |
123 | \r | |
124 | scope (\_SB)\r | |
125 | {\r | |
126 | Device(LPEA)\r | |
127 | {\r | |
128 | Name (_ADR, 0)\r | |
129 | Name (_HID, "80860F28")\r | |
130 | Name (_CID, "80860F28")\r | |
131 | //Name (_CLS, Package (3) {0x04, 0x01, 0x00})\r | |
132 | Name (_DDN, "Intel(R) Low Power Audio Controller - 80860F28")\r | |
133 | Name (_SUB, "80867270")\r | |
134 | Name (_UID, 1)\r | |
135 | Name (_DEP, Package() {\_SB.I2C2.RTEK})\r | |
136 | Name(_PR0,Package() {PLPE})\r | |
137 | \r | |
138 | Method (_STA, 0x0, NotSerialized)\r | |
139 | {\r | |
140 | If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 0)))\r | |
141 | {\r | |
142 | Return (0xF)\r | |
143 | }\r | |
144 | Return (0x0)\r | |
145 | }\r | |
146 | \r | |
147 | Method (_DIS, 0x0, NotSerialized)\r | |
148 | {\r | |
149 | //Add a dummy disable function\r | |
150 | }\r | |
151 | \r | |
152 | Name (RBUF, ResourceTemplate ()\r | |
153 | {\r | |
154 | Memory32Fixed (ReadWrite, 0xFE400000, 0x00200000, BAR0) // MMIO 1 - LPE MMIO\r | |
155 | Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space\r | |
156 | Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post\r | |
157 | Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}\r | |
158 | Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {25}\r | |
159 | Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {26}\r | |
160 | Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {27}\r | |
161 | Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {28}\r | |
162 | Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}\r | |
163 | GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO2") {28} // Audio jack interrupt\r | |
164 | }\r | |
165 | )\r | |
166 | \r | |
167 | Method (_CRS, 0x0, NotSerialized)\r | |
168 | {\r | |
169 | CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r | |
170 | Store(LPE0, B0BA)\r | |
171 | CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)\r | |
172 | Store(LPE1, B1BA)\r | |
173 | CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)\r | |
174 | Store(LPE2, B2BA)\r | |
175 | Return (RBUF)\r | |
176 | }\r | |
177 | \r | |
178 | OperationRegion (KEYS, SystemMemory, LPE1, 0x100)\r | |
179 | Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r | |
180 | {\r | |
181 | Offset (0x84),\r | |
182 | PSAT, 32\r | |
183 | }\r | |
184 | \r | |
185 | PowerResource(PLPE, 0, 0) // Power Resource for LPEA\r | |
186 | {\r | |
187 | Method (_STA)\r | |
188 | {\r | |
189 | Return (1) // Power Resource is always available.\r | |
190 | }\r | |
191 | \r | |
192 | Method (_ON)\r | |
193 | {\r | |
194 | And(PSAT, 0xfffffffC, PSAT)\r | |
195 | OR(PSAT, 0X00000000, PSAT)\r | |
196 | }\r | |
197 | \r | |
198 | Method (_OFF)\r | |
199 | {\r | |
200 | OR(PSAT, 0x00000003, PSAT)\r | |
201 | OR(PSAT, 0X00000000, PSAT)\r | |
202 | }\r | |
203 | } // End PLPE\r | |
204 | } // End "Low Power Engine Audio"\r | |
205 | \r | |
206 | Device(LPA2)\r | |
207 | {\r | |
208 | Name (_ADR, 0)\r | |
209 | Name (_HID, "LPE0F28") // _HID: Hardware ID\r | |
210 | Name (_CID, "LPE0F28") // _CID: Compatible ID\r | |
211 | Name (_DDN, "Intel(R) SST Audio - LPE0F28") // _DDN: DOS Device Name\r | |
212 | Name (_SUB, "80867270")\r | |
213 | Name (_UID, 1)\r | |
214 | Name (_DEP, Package() {\_SB.I2C2.RTEK})\r | |
215 | Name(_PR0,Package() {PLPE})\r | |
216 | \r | |
217 | Method (_STA, 0x0, NotSerialized)\r | |
218 | {\r | |
219 | If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 1)))\r | |
220 | {\r | |
221 | Return (0xF)\r | |
222 | }\r | |
223 | Return (0x0)\r | |
224 | }\r | |
225 | \r | |
226 | Method (_DIS, 0x0, NotSerialized)\r | |
227 | {\r | |
228 | //Add a dummy disable function\r | |
229 | }\r | |
230 | \r | |
231 | Name (RBUF, ResourceTemplate ()\r | |
232 | {\r | |
233 | Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post\r | |
234 | Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00000100, SHIM)\r | |
235 | Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, MBOX)\r | |
236 | Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00014000, IRAM)\r | |
237 | Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00028000, DRAM)\r | |
238 | Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}\r | |
239 | Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space\r | |
240 | }\r | |
241 | )\r | |
242 | \r | |
243 | Method (_CRS, 0x0, NotSerialized)\r | |
244 | {\r | |
245 | CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)\r | |
246 | Add(LPE0, 0x140000, SHBA)\r | |
247 | CreateDwordField(^RBUF, ^MBOX._BAS, MBBA)\r | |
248 | Add(LPE0, 0x144000, MBBA)\r | |
249 | CreateDwordField(^RBUF, ^IRAM._BAS, IRBA)\r | |
250 | Add(LPE0, 0xC0000, IRBA)\r | |
251 | CreateDwordField(^RBUF, ^DRAM._BAS, DRBA)\r | |
252 | Add(LPE0, 0x100000, DRBA)\r | |
253 | CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)\r | |
254 | Store(LPE1, B1BA)\r | |
255 | CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)\r | |
256 | Store(LPE2, B2BA)\r | |
257 | Return (RBUF)\r | |
258 | }\r | |
259 | \r | |
260 | OperationRegion (KEYS, SystemMemory, LPE1, 0x100)\r | |
261 | Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r | |
262 | {\r | |
263 | Offset (0x84),\r | |
264 | PSAT, 32\r | |
265 | }\r | |
266 | \r | |
267 | PowerResource(PLPE, 0, 0) // Power Resource for LPEA\r | |
268 | {\r | |
269 | Method (_STA)\r | |
270 | {\r | |
271 | Return (1) // Power Resource is always available.\r | |
272 | }\r | |
273 | \r | |
274 | Method (_ON)\r | |
275 | {\r | |
276 | And(PSAT, 0xfffffffC, PSAT)\r | |
277 | OR(PSAT, 0X00000000, PSAT)\r | |
278 | }\r | |
279 | \r | |
280 | Method (_OFF)\r | |
281 | {\r | |
282 | OR(PSAT, 0x00000003, PSAT)\r | |
283 | OR(PSAT, 0X00000000, PSAT)\r | |
284 | }\r | |
285 | } // End PLPE\r | |
286 | \r | |
287 | Device (ADMA)\r | |
288 | {\r | |
289 | Name (_ADR, Zero) // _ADR: Address\r | |
290 | Name (_HID, "DMA0F28") // _HID: Hardware ID\r | |
291 | Name (_CID, "DMA0F28") // _CID: Compatible ID\r | |
292 | Name (_DDN, "Intel(R) Audio DMA0 - DMA0F28") // _DDN: DOS Device Name\r | |
293 | Name (_UID, One) // _UID: Unique ID\r | |
294 | Name (RBUF, ResourceTemplate ()\r | |
295 | {\r | |
296 | Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, DMA0) // LPE BASE + LPE DMA0 offset\r | |
297 | Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, SHIM) // LPE BASE + LPE SHIM offset\r | |
298 | Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}\r | |
299 | })\r | |
300 | \r | |
301 | Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings\r | |
302 | {\r | |
303 | CreateDwordField(^RBUF, ^DMA0._BAS, D0BA)\r | |
304 | Add(LPE0, 0x98000, D0BA)\r | |
305 | CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)\r | |
306 | Add(LPE0, 0x140000, SHBA)\r | |
307 | Return (RBUF)\r | |
308 | }\r | |
309 | }\r | |
310 | } // End "Low Power Engine Audio" for Android\r | |
311 | }\r | |
312 | \r | |
313 | scope (\_SB.PCI0)\r | |
314 | {\r | |
315 | \r | |
316 | //\r | |
317 | // Serial ATA Host Controller - Device 19, Function 0\r | |
318 | //\r | |
319 | \r | |
320 | Device(SATA)\r | |
321 | {\r | |
322 | Name(_ADR,0x00130000)\r | |
323 | //\r | |
324 | // SATA Methods pulled in via SSDT.\r | |
325 | //\r | |
326 | \r | |
327 | OperationRegion(SATR, PCI_Config, 0x74,0x4)\r | |
328 | Field(SATR,WordAcc,NoLock,Preserve)\r | |
329 | {\r | |
330 | Offset(0x00), // 0x74, PMCR\r | |
331 | , 8,\r | |
332 | PMEE, 1, //PME_EN\r | |
333 | , 6,\r | |
334 | PMES, 1 //PME_STS\r | |
335 | }\r | |
336 | \r | |
337 | Method (_STA, 0x0, NotSerialized)\r | |
338 | {\r | |
339 | Return(0xf)\r | |
340 | }\r | |
341 | \r | |
342 | Method(_DSW, 3)\r | |
343 | {\r | |
344 | } // End _DSW\r | |
345 | }\r | |
346 | \r | |
347 | //\r | |
348 | // For eMMC 4.41 PCI mode in order to present non-removable device under Windows environment\r | |
349 | //\r | |
350 | Device(EM41)\r | |
351 | {\r | |
352 | Name(_ADR,0x00100000)\r | |
353 | OperationRegion(SDIO, PCI_Config, 0x84,0x4)\r | |
354 | Field(SDIO,WordAcc,NoLock,Preserve)\r | |
355 | {\r | |
356 | Offset(0x00), // 0x84, PMCR\r | |
357 | , 8,\r | |
358 | PMEE, 1, //PME_EN\r | |
359 | , 6,\r | |
360 | PMES, 1 //PME_STS\r | |
361 | }\r | |
362 | \r | |
363 | Method (_STA, 0x0, NotSerialized)\r | |
364 | {\r | |
365 | If (LAnd(LEqual(PCIM, 1), LEqual(SD1D, 0)))\r | |
366 | {\r | |
367 | Return(0xF)\r | |
368 | }\r | |
369 | Else\r | |
370 | {\r | |
371 | Return(0x0)\r | |
372 | }\r | |
373 | }\r | |
374 | \r | |
375 | Method(_DSW, 3)\r | |
376 | {\r | |
377 | } // End _DSW\r | |
378 | \r | |
379 | Device (CARD)\r | |
380 | {\r | |
381 | Name (_ADR, 0x00000008)\r | |
382 | Method(_RMV, 0x0, NotSerialized)\r | |
383 | {\r | |
384 | Return (0)\r | |
385 | } // End _DSW\r | |
386 | }\r | |
387 | }\r | |
388 | \r | |
389 | //\r | |
390 | // For eMMC 4.5 PCI mode in order to present non-removable device under Windows environment\r | |
391 | //\r | |
392 | Device(EM45)\r | |
393 | {\r | |
394 | Name(_ADR,0x00170000)\r | |
395 | OperationRegion(SDIO, PCI_Config, 0x84,0x4)\r | |
396 | Field(SDIO,WordAcc,NoLock,Preserve)\r | |
397 | {\r | |
398 | Offset(0x00), // 0x84, PMCR\r | |
399 | , 8,\r | |
400 | PMEE, 1, //PME_EN\r | |
401 | , 6,\r | |
402 | PMES, 1 //PME_STS\r | |
403 | }\r | |
404 | \r | |
405 | Method (_STA, 0x0, NotSerialized)\r | |
406 | {\r | |
407 | If (LAnd(LEqual(PCIM, 1), LEqual(HSID, 0)))\r | |
408 | {\r | |
409 | Return(0xF)\r | |
410 | }\r | |
411 | Else\r | |
412 | {\r | |
413 | Return(0x0)\r | |
414 | }\r | |
415 | }\r | |
416 | \r | |
417 | Method(_DSW, 3)\r | |
418 | {\r | |
419 | } // End _DSW\r | |
420 | \r | |
421 | Device (CARD)\r | |
422 | {\r | |
423 | Name (_ADR, 0x00000008)\r | |
424 | Method(_RMV, 0x0, NotSerialized)\r | |
425 | {\r | |
426 | Return (0)\r | |
427 | } // End _DSW\r | |
428 | }\r | |
429 | }\r | |
430 | //\r | |
431 | // For SD Host Controller (Bus 0x00 : Dev 0x12 : Func 0x00) PCI mode in order to present non-removable device under Windows environment\r | |
432 | //\r | |
433 | Device(SD12)\r | |
434 | {\r | |
435 | Name(_ADR,0x00120000)\r | |
436 | \r | |
437 | Method (_STA, 0x0, NotSerialized)\r | |
438 | {\r | |
439 | //\r | |
440 | // PCIM>> 0:ACPI mode 1:PCI mode\r | |
441 | //\r | |
442 | If (LEqual(PCIM, 0)) {\r | |
443 | Return (0x0)\r | |
444 | }\r | |
445 | \r | |
446 | //\r | |
447 | // If device is disabled.\r | |
448 | //\r | |
449 | If (LEqual(SD3D, 1))\r | |
450 | {\r | |
451 | Return (0x0)\r | |
452 | }\r | |
453 | \r | |
454 | Return (0xF)\r | |
455 | }\r | |
456 | \r | |
457 | Device (CARD)\r | |
458 | {\r | |
459 | Name (_ADR, 0x00000008)\r | |
460 | Method(_RMV, 0x0, NotSerialized)\r | |
461 | {\r | |
462 | // SDRM = 0 non-removable;\r | |
463 | If (LEqual(SDRM, 0))\r | |
464 | {\r | |
465 | Return (0)\r | |
466 | }\r | |
467 | \r | |
468 | Return (1)\r | |
469 | }\r | |
470 | }\r | |
471 | }\r | |
472 | \r | |
473 | // xHCI Controller - Device 20, Function 0\r | |
474 | include("PchXhci.asl")\r | |
475 | \r | |
476 | //\r | |
477 | // High Definition Audio Controller - Device 27, Function 0\r | |
478 | //\r | |
479 | Device(HDEF)\r | |
480 | {\r | |
481 | Name(_ADR, 0x001B0000)\r | |
482 | include("PchAudio.asl")\r | |
483 | \r | |
484 | Method (_STA, 0x0, NotSerialized)\r | |
485 | {\r | |
486 | If (LEqual(HDAD, 0))\r | |
487 | {\r | |
488 | Return(0xf)\r | |
489 | }\r | |
490 | Return(0x0)\r | |
491 | }\r | |
492 | \r | |
493 | Method(_DSW, 3)\r | |
494 | {\r | |
495 | } // End _DSW\r | |
496 | } // end "High Definition Audio Controller"\r | |
497 | \r | |
498 | \r | |
499 | \r | |
500 | //\r | |
501 | // PCIE Root Port #1\r | |
502 | //\r | |
503 | Device(RP01)\r | |
504 | {\r | |
505 | Name(_ADR, 0x001C0000)\r | |
506 | include("PchPcie.asl")\r | |
507 | Name(_PRW, Package() {9, 4})\r | |
508 | \r | |
509 | Method(_PRT,0)\r | |
510 | {\r | |
511 | If(PICM) { Return(AR04) }// APIC mode\r | |
512 | Return (PR04) // PIC Mode\r | |
513 | } // end _PRT\r | |
514 | } // end "PCIE Root Port #1"\r | |
515 | \r | |
516 | //\r | |
517 | // PCIE Root Port #2\r | |
518 | //\r | |
519 | Device(RP02)\r | |
520 | {\r | |
521 | Name(_ADR, 0x001C0001)\r | |
522 | include("PchPcie.asl")\r | |
523 | Name(_PRW, Package() {9, 4})\r | |
524 | \r | |
525 | Method(_PRT,0)\r | |
526 | {\r | |
527 | If(PICM) { Return(AR05) }// APIC mode\r | |
528 | Return (PR05) // PIC Mode\r | |
529 | } // end _PRT\r | |
530 | \r | |
531 | } // end "PCIE Root Port #2"\r | |
532 | \r | |
533 | //\r | |
534 | // PCIE Root Port #3\r | |
535 | //\r | |
536 | Device(RP03)\r | |
537 | {\r | |
538 | Name(_ADR, 0x001C0002)\r | |
539 | include("PchPcie.asl")\r | |
540 | Name(_PRW, Package() {9, 4})\r | |
541 | Method(_PRT,0)\r | |
542 | {\r | |
543 | If(PICM) { Return(AR06) }// APIC mode\r | |
544 | Return (PR06) // PIC Mode\r | |
545 | } // end _PRT\r | |
546 | \r | |
547 | } // end "PCIE Root Port #3"\r | |
548 | \r | |
549 | //\r | |
550 | // PCIE Root Port #4\r | |
551 | //\r | |
552 | Device(RP04)\r | |
553 | {\r | |
554 | Name(_ADR, 0x001C0003)\r | |
555 | include("PchPcie.asl")\r | |
556 | Name(_PRW, Package() {9, 4})\r | |
557 | Method(_PRT,0)\r | |
558 | {\r | |
559 | If(PICM) { Return(AR07) }// APIC mode\r | |
560 | Return (PR07) // PIC Mode\r | |
561 | } // end _PRT\r | |
562 | \r | |
563 | } // end "PCIE Root Port #4"\r | |
564 | \r | |
565 | \r | |
566 | Scope(\_SB)\r | |
567 | {\r | |
568 | //\r | |
569 | // Dummy power resource for USB D3 cold support\r | |
570 | //\r | |
571 | PowerResource(USBC, 0, 0)\r | |
572 | {\r | |
573 | Method(_STA) { Return (0xF) }\r | |
574 | Method(_ON) {}\r | |
575 | Method(_OFF) {}\r | |
576 | }\r | |
577 | }\r | |
578 | //\r | |
579 | // EHCI Controller - Device 29, Function 0\r | |
580 | //\r | |
581 | Device(EHC1)\r | |
582 | {\r | |
583 | Name(_ADR, 0x001D0000)\r | |
584 | Name(_DEP, Package(0x1)\r | |
585 | {\r | |
586 | PEPD\r | |
587 | })\r | |
588 | include("PchEhci.asl")\r | |
589 | Name(_PRW, Package() {0x0D, 4})\r | |
590 | \r | |
591 | OperationRegion(USBR, PCI_Config, 0x54,0x4)\r | |
592 | Field(USBR,WordAcc,NoLock,Preserve)\r | |
593 | {\r | |
594 | Offset(0x00), // 0x54, PMCR\r | |
595 | , 8,\r | |
596 | PMEE, 1, //PME_EN\r | |
597 | , 6,\r | |
598 | PMES, 1 //PME_STS\r | |
599 | }\r | |
600 | \r | |
601 | Method (_STA, 0x0, NotSerialized)\r | |
602 | {\r | |
603 | If(LEqual(XHCI, 0)) //XHCI is not present. It means EHCI is there\r | |
604 | {\r | |
605 | Return (0xF)\r | |
606 | } Else\r | |
607 | {\r | |
608 | Return (0x0)\r | |
609 | }\r | |
610 | }\r | |
611 | \r | |
612 | Method (_RMV, 0, NotSerialized)\r | |
613 | {\r | |
614 | Return (0x0)\r | |
615 | }\r | |
616 | //\r | |
617 | // Create a dummy PR3 method to indicate to the PCI driver\r | |
618 | // that the device is capable of D3 cold\r | |
619 | //\r | |
620 | Method(_PR3, 0x0, NotSerialized)\r | |
621 | {\r | |
622 | return (Package() {\_SB.USBC})\r | |
623 | }\r | |
624 | \r | |
625 | } // end "EHCI Controller"\r | |
626 | \r | |
627 | //\r | |
628 | // SMBus Controller - Device 31, Function 3\r | |
629 | //\r | |
630 | Device(SBUS)\r | |
631 | {\r | |
632 | Name(_ADR,0x001F0003)\r | |
633 | Include("PchSmb.asl")\r | |
634 | }\r | |
635 | \r | |
636 | Device(SEC0)\r | |
637 | {\r | |
638 | Name (_ADR, 0x001a0000) // Device 0x1a, Function 0\r | |
639 | Name(_DEP, Package(0x1)\r | |
640 | {\r | |
641 | PEPD\r | |
642 | })\r | |
643 | \r | |
644 | \r | |
645 | OperationRegion (PMEB, PCI_Config, 0x84, 0x04) //PMECTRLSTATUS\r | |
646 | Field (PMEB, WordAcc, NoLock, Preserve)\r | |
647 | {\r | |
648 | , 8,\r | |
649 | PMEE, 1, //bit8 PMEENABLE\r | |
650 | , 6,\r | |
651 | PMES, 1 //bit15 PMESTATUS\r | |
652 | }\r | |
653 | \r | |
654 | // Arg0 -- integer that contains the device wake capability control (0-disable 1- enable)\r | |
655 | // Arg1 -- integer that contains target system state (0-4)\r | |
656 | // Arg2 -- integer that contains the target device state\r | |
657 | Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake\r | |
658 | {\r | |
659 | }\r | |
660 | \r | |
661 | Method (_CRS, 0, NotSerialized)\r | |
662 | {\r | |
663 | Name (RBUF, ResourceTemplate ()\r | |
664 | {\r | |
665 | Memory32Fixed (ReadWrite, 0x1e000000, 0x2000000)\r | |
666 | })\r | |
667 | \r | |
668 | If (LEqual(PAVP, 2))\r | |
669 | {\r | |
670 | Return (RBUF)\r | |
671 | }\r | |
672 | Return (ResourceTemplate() {})\r | |
673 | }\r | |
674 | \r | |
675 | Method (_STA)\r | |
676 | {\r | |
677 | If (LNotEqual(PAVP, 0))\r | |
678 | {\r | |
679 | Return (0xF)\r | |
680 | }\r | |
681 | Return (0x0)\r | |
682 | }\r | |
683 | } // Device(SEC0)\r | |
684 | \r | |
685 | } // End scope (\_SB.PCI0)\r |