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1 | /**************************************************************************;\r |
2 | ;* *;\r | |
3 | ;* *;\r | |
4 | ;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *;\r | |
5 | ;* Family of Customer Reference Boards. *;\r | |
6 | ;* *;\r | |
7 | ;* *;\r | |
8 | ;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r | |
9 | ;\r | |
10 | ; This program and the accompanying materials are licensed and made available under\r | |
11 | ; the terms and conditions of the BSD License that accompanies this distribution.\r | |
12 | ; The full text of the license may be found at\r | |
13 | ; http://opensource.org/licenses/bsd-license.php.\r | |
14 | ;\r | |
15 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | ;\r | |
18 | ;* *;\r | |
19 | ;* *;\r | |
20 | ;**************************************************************************/\r | |
21 | \r | |
22 | Scope(\_SB)\r | |
23 | {\r | |
24 | \r | |
25 | //RTC\r | |
26 | Device(RTC) // RTC\r | |
27 | {\r | |
28 | Name(_HID,EISAID("PNP0B00"))\r | |
29 | \r | |
30 | Name(_CRS,ResourceTemplate()\r | |
31 | {\r | |
32 | IO(Decode16,0x70,0x70,0x01,0x08)\r | |
33 | })\r | |
34 | }\r | |
35 | //RTC\r | |
36 | \r | |
37 | Device(HPET) // High Performance Event Timer\r | |
38 | {\r | |
39 | Name (_HID, EisaId ("PNP0103"))\r | |
40 | Name (_UID, 0x00)\r | |
41 | Method (_STA, 0, NotSerialized)\r | |
42 | {\r | |
43 | Return (0x0F)\r | |
44 | }\r | |
45 | \r | |
46 | Method (_CRS, 0, Serialized)\r | |
47 | {\r | |
48 | Name (RBUF, ResourceTemplate ()\r | |
49 | {\r | |
50 | Memory32Fixed (ReadWrite,\r | |
51 | 0xFED00000, // Address Base\r | |
52 | 0x00000400, // Address Length\r | |
53 | )\r | |
54 | Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )\r | |
55 | {\r | |
56 | 0x00000008, //0xB HPET-2\r | |
57 | }\r | |
58 | })\r | |
59 | Return (RBUF)\r | |
60 | }\r | |
61 | }\r | |
62 | //HPET\r | |
63 | \r | |
64 | Name(PR00, Package()\r | |
65 | {\r | |
66 | // SD Host #0 - eMMC\r | |
67 | Package() {0x0010FFFF, 0, LNKA, 0 },\r | |
68 | // SD Host #1 - SDIO\r | |
69 | Package() {0x0011FFFF, 0, LNKB, 0 },\r | |
70 | // SD Host #2 - SD Card\r | |
71 | Package() {0x0012FFFF, 0, LNKC, 0 },\r | |
72 | // SATA Controller\r | |
73 | Package() {0x0013FFFF, 0, LNKD, 0 },\r | |
74 | // xHCI Host\r | |
75 | Package() {0x0014FFFF, 0, LNKE, 0 },\r | |
76 | // Low Power Audio Engine\r | |
77 | Package() {0x0015FFFF, 0, LNKF, 0 },\r | |
78 | // USB OTG\r | |
79 | Package() {0x0016FFFF, 0, LNKG, 0 },\r | |
80 | // MIPI-HSI/eMMC4.5\r | |
81 | Package() {0x0017FFFF, 0, LNKH, 0 },\r | |
82 | // LPSS2 DMA\r | |
83 | // LPSS2 I2C #4\r | |
84 | Package() {0x0018FFFF, 0, LNKB, 0 },\r | |
85 | // LPSS2 I2C #1\r | |
86 | // LPSS2 I2C #5\r | |
87 | Package() {0x0018FFFF, 2, LNKD, 0 },\r | |
88 | // LPSS2 I2C #2\r | |
89 | // LPSS2 I2C #6\r | |
90 | Package() {0x0018FFFF, 3, LNKC, 0 },\r | |
91 | // LPSS2 I2C #3\r | |
92 | // LPSS2 I2C #7\r | |
93 | Package() {0x0018FFFF, 1, LNKA, 0 },\r | |
94 | // SeC\r | |
95 | Package() {0x001AFFFF, 0, LNKF, 0 },\r | |
96 | //\r | |
97 | // High Definition Audio Controller\r | |
98 | Package() {0x001BFFFF, 0, LNKG, 0 },\r | |
99 | //\r | |
100 | // EHCI Controller\r | |
101 | Package() {0x001DFFFF, 0, LNKH, 0 },\r | |
102 | // LPSS DMA\r | |
103 | Package() {0x001EFFFF, 0, LNKD, 0 },\r | |
104 | // LPSS I2C #0\r | |
105 | Package() {0x001EFFFF, 3, LNKA, 0 },\r | |
106 | // LPSS I2C #1\r | |
107 | Package() {0x001EFFFF, 1, LNKB, 0 },\r | |
108 | // LPSS PCM\r | |
109 | Package() {0x001EFFFF, 2, LNKC, 0 },\r | |
110 | // LPSS I2S\r | |
111 | // LPSS HS-UART #0\r | |
112 | // LPSS HS-UART #1\r | |
113 | // LPSS SPI\r | |
114 | // LPC Bridge\r | |
115 | //\r | |
116 | // SMBus Controller\r | |
117 | Package() {0x001FFFFF, 1, LNKC, 0 },\r | |
118 | //\r | |
119 | // PCIE Root Port #1\r | |
120 | Package() {0x001CFFFF, 0, LNKA, 0 },\r | |
121 | // PCIE Root Port #2\r | |
122 | Package() {0x001CFFFF, 1, LNKB, 0 },\r | |
123 | // PCIE Root Port #3\r | |
124 | Package() {0x001CFFFF, 2, LNKC, 0 },\r | |
125 | // PCIE Root Port #4\r | |
126 | Package() {0x001CFFFF, 3, LNKD, 0 },\r | |
127 | \r | |
128 | // Host Bridge\r | |
129 | // Mobile IGFX\r | |
130 | Package() {0x0002FFFF, 0, LNKA, 0 },\r | |
131 | })\r | |
132 | \r | |
133 | Name(AR00, Package()\r | |
134 | {\r | |
135 | // SD Host #0 - eMMC\r | |
136 | Package() {0x0010FFFF, 0, 0, 16 },\r | |
137 | // SD Host #1 - SDIO\r | |
138 | Package() {0x0011FFFF, 0, 0, 17 },\r | |
139 | // SD Host #2 - SD Card\r | |
140 | Package() {0x0012FFFF, 0, 0, 18 },\r | |
141 | // SATA Controller\r | |
142 | Package() {0x0013FFFF, 0, 0, 19 },\r | |
143 | // xHCI Host\r | |
144 | Package() {0x0014FFFF, 0, 0, 20 },\r | |
145 | // Low Power Audio Engine\r | |
146 | Package() {0x0015FFFF, 0, 0, 21 },\r | |
147 | // USB OTG\r | |
148 | Package() {0x0016FFFF, 0, 0, 22 },\r | |
149 | //\r | |
150 | // MIPI-HSI\r | |
151 | Package() {0x0017FFFF, 0, 0, 23 },\r | |
152 | //\r | |
153 | // LPSS2 DMA\r | |
154 | // LPSS2 I2C #4\r | |
155 | Package() {0x0018FFFF, 0, 0, 17 },\r | |
156 | // LPSS2 I2C #1\r | |
157 | // LPSS2 I2C #5\r | |
158 | Package() {0x0018FFFF, 2, 0, 19 },\r | |
159 | // LPSS2 I2C #2\r | |
160 | // LPSS2 I2C #6\r | |
161 | Package() {0x0018FFFF, 3, 0, 18 },\r | |
162 | // LPSS2 I2C #3\r | |
163 | // LPSS2 I2C #7\r | |
164 | Package() {0x0018FFFF, 1, 0, 16 },\r | |
165 | \r | |
166 | // SeC\r | |
167 | Package() {0x001AFFFF, 0, 0, 21 },\r | |
168 | //\r | |
169 | // High Definition Audio Controller\r | |
170 | Package() {0x001BFFFF, 0, 0, 22 },\r | |
171 | //\r | |
172 | // EHCI Controller\r | |
173 | Package() {0x001DFFFF, 0, 0, 23 },\r | |
174 | // LPSS DMA\r | |
175 | Package() {0x001EFFFF, 0, 0, 19 },\r | |
176 | // LPSS I2C #0\r | |
177 | Package() {0x001EFFFF, 3, 0, 16 },\r | |
178 | // LPSS I2C #1\r | |
179 | Package() {0x001EFFFF, 1, 0, 17 },\r | |
180 | // LPSS PCM\r | |
181 | Package() {0x001EFFFF, 2, 0, 18 },\r | |
182 | // LPSS I2S\r | |
183 | // LPSS HS-UART #0\r | |
184 | // LPSS HS-UART #1\r | |
185 | // LPSS SPI\r | |
186 | // LPC Bridge\r | |
187 | //\r | |
188 | // SMBus Controller\r | |
189 | Package() {0x001FFFFF, 1, 0, 18 },\r | |
190 | //\r | |
191 | // PCIE Root Port #1\r | |
192 | Package() {0x001CFFFF, 0, 0, 16 },\r | |
193 | // PCIE Root Port #2\r | |
194 | Package() {0x001CFFFF, 1, 0, 17 },\r | |
195 | // PCIE Root Port #3\r | |
196 | Package() {0x001CFFFF, 2, 0, 18 },\r | |
197 | // PCIE Root Port #4\r | |
198 | Package() {0x001CFFFF, 3, 0, 19 },\r | |
199 | // Host Bridge\r | |
200 | // Mobile IGFX\r | |
201 | Package() {0x0002FFFF, 0, 0, 16 },\r | |
202 | })\r | |
203 | \r | |
204 | Name(PR04, Package()\r | |
205 | {\r | |
206 | // PCIE Port #1 Slot\r | |
207 | Package() {0x0000FFFF, 0, LNKA, 0 },\r | |
208 | Package() {0x0000FFFF, 1, LNKB, 0 },\r | |
209 | Package() {0x0000FFFF, 2, LNKC, 0 },\r | |
210 | Package() {0x0000FFFF, 3, LNKD, 0 },\r | |
211 | })\r | |
212 | \r | |
213 | Name(AR04, Package()\r | |
214 | {\r | |
215 | // PCIE Port #1 Slot\r | |
216 | Package() {0x0000FFFF, 0, 0, 16 },\r | |
217 | Package() {0x0000FFFF, 1, 0, 17 },\r | |
218 | Package() {0x0000FFFF, 2, 0, 18 },\r | |
219 | Package() {0x0000FFFF, 3, 0, 19 },\r | |
220 | })\r | |
221 | \r | |
222 | Name(PR05, Package()\r | |
223 | {\r | |
224 | // PCIE Port #2 Slot\r | |
225 | Package() {0x0000FFFF, 0, LNKB, 0 },\r | |
226 | Package() {0x0000FFFF, 1, LNKC, 0 },\r | |
227 | Package() {0x0000FFFF, 2, LNKD, 0 },\r | |
228 | Package() {0x0000FFFF, 3, LNKA, 0 },\r | |
229 | })\r | |
230 | \r | |
231 | Name(AR05, Package()\r | |
232 | {\r | |
233 | // PCIE Port #2 Slot\r | |
234 | Package() {0x0000FFFF, 0, 0, 17 },\r | |
235 | Package() {0x0000FFFF, 1, 0, 18 },\r | |
236 | Package() {0x0000FFFF, 2, 0, 19 },\r | |
237 | Package() {0x0000FFFF, 3, 0, 16 },\r | |
238 | })\r | |
239 | \r | |
240 | Name(PR06, Package()\r | |
241 | {\r | |
242 | // PCIE Port #3 Slot\r | |
243 | Package() {0x0000FFFF, 0, LNKC, 0 },\r | |
244 | Package() {0x0000FFFF, 1, LNKD, 0 },\r | |
245 | Package() {0x0000FFFF, 2, LNKA, 0 },\r | |
246 | Package() {0x0000FFFF, 3, LNKB, 0 },\r | |
247 | })\r | |
248 | \r | |
249 | Name(AR06, Package()\r | |
250 | {\r | |
251 | // PCIE Port #3 Slot\r | |
252 | Package() {0x0000FFFF, 0, 0, 18 },\r | |
253 | Package() {0x0000FFFF, 1, 0, 19 },\r | |
254 | Package() {0x0000FFFF, 2, 0, 16 },\r | |
255 | Package() {0x0000FFFF, 3, 0, 17 },\r | |
256 | })\r | |
257 | \r | |
258 | Name(PR07, Package()\r | |
259 | {\r | |
260 | // PCIE Port #4 Slot\r | |
261 | Package() {0x0000FFFF, 0, LNKD, 0 },\r | |
262 | Package() {0x0000FFFF, 1, LNKA, 0 },\r | |
263 | Package() {0x0000FFFF, 2, LNKB, 0 },\r | |
264 | Package() {0x0000FFFF, 3, LNKC, 0 },\r | |
265 | })\r | |
266 | \r | |
267 | Name(AR07, Package()\r | |
268 | {\r | |
269 | // PCIE Port #4 Slot\r | |
270 | Package() {0x0000FFFF, 0, 0, 19 },\r | |
271 | Package() {0x0000FFFF, 1, 0, 16 },\r | |
272 | Package() {0x0000FFFF, 2, 0, 17 },\r | |
273 | Package() {0x0000FFFF, 3, 0, 18 },\r | |
274 | })\r | |
275 | \r | |
276 | Name(PR01, Package()\r | |
277 | {\r | |
278 | // PCI slot 1\r | |
279 | Package() {0x0000FFFF, 0, LNKF, 0 },\r | |
280 | Package() {0x0000FFFF, 1, LNKG, 0 },\r | |
281 | Package() {0x0000FFFF, 2, LNKH, 0 },\r | |
282 | Package() {0x0000FFFF, 3, LNKE, 0 },\r | |
283 | // PCI slot 2\r | |
284 | Package() {0x0001FFFF, 0, LNKG, 0 },\r | |
285 | Package() {0x0001FFFF, 1, LNKF, 0 },\r | |
286 | Package() {0x0001FFFF, 2, LNKE, 0 },\r | |
287 | Package() {0x0001FFFF, 3, LNKH, 0 },\r | |
288 | // PCI slot 3\r | |
289 | Package() {0x0002FFFF, 0, LNKC, 0 },\r | |
290 | Package() {0x0002FFFF, 1, LNKD, 0 },\r | |
291 | Package() {0x0002FFFF, 2, LNKB, 0 },\r | |
292 | Package() {0x0002FFFF, 3, LNKA, 0 },\r | |
293 | // PCI slot 4\r | |
294 | Package() {0x0003FFFF, 0, LNKD, 0 },\r | |
295 | Package() {0x0003FFFF, 1, LNKC, 0 },\r | |
296 | Package() {0x0003FFFF, 2, LNKF, 0 },\r | |
297 | Package() {0x0003FFFF, 3, LNKG, 0 },\r | |
298 | })\r | |
299 | \r | |
300 | Name(AR01, Package()\r | |
301 | {\r | |
302 | // PCI slot 1\r | |
303 | Package() {0x0000FFFF, 0, 0, 21 },\r | |
304 | Package() {0x0000FFFF, 1, 0, 22 },\r | |
305 | Package() {0x0000FFFF, 2, 0, 23 },\r | |
306 | Package() {0x0000FFFF, 3, 0, 20 },\r | |
307 | // PCI slot 2\r | |
308 | Package() {0x0001FFFF, 0, 0, 22 },\r | |
309 | Package() {0x0001FFFF, 1, 0, 21 },\r | |
310 | Package() {0x0001FFFF, 2, 0, 20 },\r | |
311 | Package() {0x0001FFFF, 3, 0, 23 },\r | |
312 | // PCI slot 3\r | |
313 | Package() {0x0002FFFF, 0, 0, 18 },\r | |
314 | Package() {0x0002FFFF, 1, 0, 19 },\r | |
315 | Package() {0x0002FFFF, 2, 0, 17 },\r | |
316 | Package() {0x0002FFFF, 3, 0, 16 },\r | |
317 | // PCI slot 4\r | |
318 | Package() {0x0003FFFF, 0, 0, 19 },\r | |
319 | Package() {0x0003FFFF, 1, 0, 18 },\r | |
320 | Package() {0x0003FFFF, 2, 0, 21 },\r | |
321 | Package() {0x0003FFFF, 3, 0, 22 },\r | |
322 | })\r | |
323 | //---------------------------------------------------------------------------\r | |
324 | // List of IRQ resource buffers compatible with _PRS return format.\r | |
325 | //---------------------------------------------------------------------------\r | |
326 | // Naming legend:\r | |
327 | // RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.\r | |
328 | // Note. PRSy name is generated if IRQ Link name starts from "LNK".\r | |
329 | // HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.\r | |
330 | //---------------------------------------------------------------------------\r | |
331 | Name(PRSA, ResourceTemplate() // Link name: LNKA\r | |
332 | {\r | |
333 | IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}\r | |
334 | })\r | |
335 | Alias(PRSA,PRSB) // Link name: LNKB\r | |
336 | Alias(PRSA,PRSC) // Link name: LNKC\r | |
337 | Alias(PRSA,PRSD) // Link name: LNKD\r | |
338 | Alias(PRSA,PRSE) // Link name: LNKE\r | |
339 | Alias(PRSA,PRSF) // Link name: LNKF\r | |
340 | Alias(PRSA,PRSG) // Link name: LNKG\r | |
341 | Alias(PRSA,PRSH) // Link name: LNKH\r | |
342 | //---------------------------------------------------------------------------\r | |
343 | // Begin PCI tree object scope\r | |
344 | //---------------------------------------------------------------------------\r | |
345 | \r | |
346 | Device(PCI0) // PCI Bridge "Host Bridge"\r | |
347 | {\r | |
348 | Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy\r | |
349 | Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID\r | |
350 | Name(_ADR, 0x00000000)\r | |
351 | Method(^BN00, 0) { return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope\r | |
352 | Method(_BBN, 0) { return(BN00()) } // Bus number, optional for the Root PCI Bus\r | |
353 | Name(_UID, 0x0000) // Unique Bus ID, optional\r | |
354 | Name(_DEP, Package(0x1)\r | |
355 | {\r | |
356 | PEPD\r | |
357 | })\r | |
358 | \r | |
359 | Method(_PRT,0)\r | |
360 | {\r | |
361 | If(PICM) {Return(AR00)} // APIC mode\r | |
362 | Return (PR00) // PIC Mode\r | |
363 | } // end _PRT\r | |
364 | \r | |
365 | include("HOST_BUS.ASL")\r | |
366 | Device(LPCB) // LPC Bridge\r | |
367 | {\r | |
368 | Name(_ADR, 0x001F0000)\r | |
369 | include("LpcB.asl")\r | |
370 | } // end "LPC Bridge"\r | |
371 | \r | |
372 | } // end PCI0 Bridge "Host Bridge"\r | |
373 | } // end _SB scope\r |