projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /**************************************************************************;\r |
| 2 | ;* *;\r | |
| 3 | ;* *;\r | |
| 4 | ;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *;\r | |
| 5 | ;* Family of Customer Reference Boards. *;\r | |
| 6 | ;* *;\r | |
| 7 | ;* *;\r | |
| 52a99493 | 8 | ;* Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved *;\r |
| 3cbfba02 | 9 | ;\r |
| 7ede8060 | 10 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
11 | ;\r |
| 12 | ;* *;\r | |
| 13 | ;* *;\r | |
| 14 | ;**************************************************************************/\r | |
| 15 | \r | |
| 16 | Scope(\_SB)\r | |
| 17 | {\r | |
| 3cbfba02 DW |
18 | //RTC\r |
| 19 | Device(RTC) // RTC\r | |
| 20 | {\r | |
| 21 | Name(_HID,EISAID("PNP0B00"))\r | |
| 22 | \r | |
| 23 | Name(_CRS,ResourceTemplate()\r | |
| 24 | {\r | |
| 25 | IO(Decode16,0x70,0x70,0x01,0x08)\r | |
| 26 | })\r | |
| 52a99493 LS |
27 | \r |
| 28 | Method(_STA,0,Serialized) {\r | |
| 29 | \r | |
| 30 | //\r | |
| 31 | // Report RTC Battery is Prensent or Not Present.\r | |
| 32 | //\r | |
| 33 | If (LEqual(BATT, 1)) {\r | |
| 34 | Return (0xF)\r | |
| 35 | }\r | |
| 36 | Return (0x0)\r | |
| 37 | }\r | |
| 3cbfba02 DW |
38 | }\r |
| 39 | //RTC\r | |
| 40 | \r | |
| 41 | Device(HPET) // High Performance Event Timer\r | |
| 42 | {\r | |
| 43 | Name (_HID, EisaId ("PNP0103"))\r | |
| 44 | Name (_UID, 0x00)\r | |
| 45 | Method (_STA, 0, NotSerialized)\r | |
| 46 | {\r | |
| 47 | Return (0x0F)\r | |
| 48 | }\r | |
| 49 | \r | |
| 50 | Method (_CRS, 0, Serialized)\r | |
| 51 | {\r | |
| 52 | Name (RBUF, ResourceTemplate ()\r | |
| 53 | {\r | |
| 54 | Memory32Fixed (ReadWrite,\r | |
| 55 | 0xFED00000, // Address Base\r | |
| 56 | 0x00000400, // Address Length\r | |
| 57 | )\r | |
| 58 | Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )\r | |
| 59 | {\r | |
| 60 | 0x00000008, //0xB HPET-2\r | |
| 61 | }\r | |
| 62 | })\r | |
| 63 | Return (RBUF)\r | |
| 64 | }\r | |
| 65 | }\r | |
| 66 | //HPET\r | |
| 67 | \r | |
| 68 | Name(PR00, Package()\r | |
| 69 | {\r | |
| 70 | // SD Host #0 - eMMC\r | |
| 71 | Package() {0x0010FFFF, 0, LNKA, 0 },\r | |
| 72 | // SD Host #1 - SDIO\r | |
| 73 | Package() {0x0011FFFF, 0, LNKB, 0 },\r | |
| 74 | // SD Host #2 - SD Card\r | |
| 75 | Package() {0x0012FFFF, 0, LNKC, 0 },\r | |
| 76 | // SATA Controller\r | |
| 77 | Package() {0x0013FFFF, 0, LNKD, 0 },\r | |
| 78 | // xHCI Host\r | |
| 79 | Package() {0x0014FFFF, 0, LNKE, 0 },\r | |
| 80 | // Low Power Audio Engine\r | |
| 81 | Package() {0x0015FFFF, 0, LNKF, 0 },\r | |
| 82 | // USB OTG\r | |
| 83 | Package() {0x0016FFFF, 0, LNKG, 0 },\r | |
| 84 | // MIPI-HSI/eMMC4.5\r | |
| 85 | Package() {0x0017FFFF, 0, LNKH, 0 },\r | |
| 86 | // LPSS2 DMA\r | |
| 87 | // LPSS2 I2C #4\r | |
| 88 | Package() {0x0018FFFF, 0, LNKB, 0 },\r | |
| 89 | // LPSS2 I2C #1\r | |
| 90 | // LPSS2 I2C #5\r | |
| 91 | Package() {0x0018FFFF, 2, LNKD, 0 },\r | |
| 92 | // LPSS2 I2C #2\r | |
| 93 | // LPSS2 I2C #6\r | |
| 94 | Package() {0x0018FFFF, 3, LNKC, 0 },\r | |
| 95 | // LPSS2 I2C #3\r | |
| 96 | // LPSS2 I2C #7\r | |
| 97 | Package() {0x0018FFFF, 1, LNKA, 0 },\r | |
| 98 | // SeC\r | |
| 99 | Package() {0x001AFFFF, 0, LNKF, 0 },\r | |
| 100 | //\r | |
| 101 | // High Definition Audio Controller\r | |
| 102 | Package() {0x001BFFFF, 0, LNKG, 0 },\r | |
| 103 | //\r | |
| 104 | // EHCI Controller\r | |
| 105 | Package() {0x001DFFFF, 0, LNKH, 0 },\r | |
| 106 | // LPSS DMA\r | |
| 107 | Package() {0x001EFFFF, 0, LNKD, 0 },\r | |
| 108 | // LPSS I2C #0\r | |
| 109 | Package() {0x001EFFFF, 3, LNKA, 0 },\r | |
| 110 | // LPSS I2C #1\r | |
| 111 | Package() {0x001EFFFF, 1, LNKB, 0 },\r | |
| 112 | // LPSS PCM\r | |
| 113 | Package() {0x001EFFFF, 2, LNKC, 0 },\r | |
| 114 | // LPSS I2S\r | |
| 115 | // LPSS HS-UART #0\r | |
| 116 | // LPSS HS-UART #1\r | |
| 117 | // LPSS SPI\r | |
| 118 | // LPC Bridge\r | |
| 119 | //\r | |
| 120 | // SMBus Controller\r | |
| 121 | Package() {0x001FFFFF, 1, LNKC, 0 },\r | |
| 122 | //\r | |
| 123 | // PCIE Root Port #1\r | |
| 124 | Package() {0x001CFFFF, 0, LNKA, 0 },\r | |
| 125 | // PCIE Root Port #2\r | |
| 126 | Package() {0x001CFFFF, 1, LNKB, 0 },\r | |
| 127 | // PCIE Root Port #3\r | |
| 128 | Package() {0x001CFFFF, 2, LNKC, 0 },\r | |
| 129 | // PCIE Root Port #4\r | |
| 130 | Package() {0x001CFFFF, 3, LNKD, 0 },\r | |
| 131 | \r | |
| 132 | // Host Bridge\r | |
| 133 | // Mobile IGFX\r | |
| 134 | Package() {0x0002FFFF, 0, LNKA, 0 },\r | |
| 135 | })\r | |
| 136 | \r | |
| 137 | Name(AR00, Package()\r | |
| 138 | {\r | |
| 139 | // SD Host #0 - eMMC\r | |
| 140 | Package() {0x0010FFFF, 0, 0, 16 },\r | |
| 141 | // SD Host #1 - SDIO\r | |
| 142 | Package() {0x0011FFFF, 0, 0, 17 },\r | |
| 143 | // SD Host #2 - SD Card\r | |
| 144 | Package() {0x0012FFFF, 0, 0, 18 },\r | |
| 145 | // SATA Controller\r | |
| 146 | Package() {0x0013FFFF, 0, 0, 19 },\r | |
| 147 | // xHCI Host\r | |
| 148 | Package() {0x0014FFFF, 0, 0, 20 },\r | |
| 149 | // Low Power Audio Engine\r | |
| 150 | Package() {0x0015FFFF, 0, 0, 21 },\r | |
| 151 | // USB OTG\r | |
| 152 | Package() {0x0016FFFF, 0, 0, 22 },\r | |
| 153 | //\r | |
| 154 | // MIPI-HSI\r | |
| 155 | Package() {0x0017FFFF, 0, 0, 23 },\r | |
| 156 | //\r | |
| 157 | // LPSS2 DMA\r | |
| 158 | // LPSS2 I2C #4\r | |
| 159 | Package() {0x0018FFFF, 0, 0, 17 },\r | |
| 160 | // LPSS2 I2C #1\r | |
| 161 | // LPSS2 I2C #5\r | |
| 162 | Package() {0x0018FFFF, 2, 0, 19 },\r | |
| 163 | // LPSS2 I2C #2\r | |
| 164 | // LPSS2 I2C #6\r | |
| 165 | Package() {0x0018FFFF, 3, 0, 18 },\r | |
| 166 | // LPSS2 I2C #3\r | |
| 167 | // LPSS2 I2C #7\r | |
| 168 | Package() {0x0018FFFF, 1, 0, 16 },\r | |
| 169 | \r | |
| 170 | // SeC\r | |
| 171 | Package() {0x001AFFFF, 0, 0, 21 },\r | |
| 172 | //\r | |
| 173 | // High Definition Audio Controller\r | |
| 174 | Package() {0x001BFFFF, 0, 0, 22 },\r | |
| 175 | //\r | |
| 176 | // EHCI Controller\r | |
| 177 | Package() {0x001DFFFF, 0, 0, 23 },\r | |
| 178 | // LPSS DMA\r | |
| 179 | Package() {0x001EFFFF, 0, 0, 19 },\r | |
| 180 | // LPSS I2C #0\r | |
| 181 | Package() {0x001EFFFF, 3, 0, 16 },\r | |
| 182 | // LPSS I2C #1\r | |
| 183 | Package() {0x001EFFFF, 1, 0, 17 },\r | |
| 184 | // LPSS PCM\r | |
| 185 | Package() {0x001EFFFF, 2, 0, 18 },\r | |
| 186 | // LPSS I2S\r | |
| 187 | // LPSS HS-UART #0\r | |
| 188 | // LPSS HS-UART #1\r | |
| 189 | // LPSS SPI\r | |
| 190 | // LPC Bridge\r | |
| 191 | //\r | |
| 192 | // SMBus Controller\r | |
| 193 | Package() {0x001FFFFF, 1, 0, 18 },\r | |
| 194 | //\r | |
| 195 | // PCIE Root Port #1\r | |
| 196 | Package() {0x001CFFFF, 0, 0, 16 },\r | |
| 197 | // PCIE Root Port #2\r | |
| 198 | Package() {0x001CFFFF, 1, 0, 17 },\r | |
| 199 | // PCIE Root Port #3\r | |
| 200 | Package() {0x001CFFFF, 2, 0, 18 },\r | |
| 201 | // PCIE Root Port #4\r | |
| 202 | Package() {0x001CFFFF, 3, 0, 19 },\r | |
| 203 | // Host Bridge\r | |
| 204 | // Mobile IGFX\r | |
| 205 | Package() {0x0002FFFF, 0, 0, 16 },\r | |
| 206 | })\r | |
| 207 | \r | |
| 208 | Name(PR04, Package()\r | |
| 209 | {\r | |
| 210 | // PCIE Port #1 Slot\r | |
| 211 | Package() {0x0000FFFF, 0, LNKA, 0 },\r | |
| 212 | Package() {0x0000FFFF, 1, LNKB, 0 },\r | |
| 213 | Package() {0x0000FFFF, 2, LNKC, 0 },\r | |
| 214 | Package() {0x0000FFFF, 3, LNKD, 0 },\r | |
| 215 | })\r | |
| 216 | \r | |
| 217 | Name(AR04, Package()\r | |
| 218 | {\r | |
| 219 | // PCIE Port #1 Slot\r | |
| 220 | Package() {0x0000FFFF, 0, 0, 16 },\r | |
| 221 | Package() {0x0000FFFF, 1, 0, 17 },\r | |
| 222 | Package() {0x0000FFFF, 2, 0, 18 },\r | |
| 223 | Package() {0x0000FFFF, 3, 0, 19 },\r | |
| 224 | })\r | |
| 225 | \r | |
| 226 | Name(PR05, Package()\r | |
| 227 | {\r | |
| 228 | // PCIE Port #2 Slot\r | |
| 229 | Package() {0x0000FFFF, 0, LNKB, 0 },\r | |
| 230 | Package() {0x0000FFFF, 1, LNKC, 0 },\r | |
| 231 | Package() {0x0000FFFF, 2, LNKD, 0 },\r | |
| 232 | Package() {0x0000FFFF, 3, LNKA, 0 },\r | |
| 233 | })\r | |
| 234 | \r | |
| 235 | Name(AR05, Package()\r | |
| 236 | {\r | |
| 237 | // PCIE Port #2 Slot\r | |
| 238 | Package() {0x0000FFFF, 0, 0, 17 },\r | |
| 239 | Package() {0x0000FFFF, 1, 0, 18 },\r | |
| 240 | Package() {0x0000FFFF, 2, 0, 19 },\r | |
| 241 | Package() {0x0000FFFF, 3, 0, 16 },\r | |
| 242 | })\r | |
| 243 | \r | |
| 244 | Name(PR06, Package()\r | |
| 245 | {\r | |
| 246 | // PCIE Port #3 Slot\r | |
| 247 | Package() {0x0000FFFF, 0, LNKC, 0 },\r | |
| 248 | Package() {0x0000FFFF, 1, LNKD, 0 },\r | |
| 249 | Package() {0x0000FFFF, 2, LNKA, 0 },\r | |
| 250 | Package() {0x0000FFFF, 3, LNKB, 0 },\r | |
| 251 | })\r | |
| 252 | \r | |
| 253 | Name(AR06, Package()\r | |
| 254 | {\r | |
| 255 | // PCIE Port #3 Slot\r | |
| 256 | Package() {0x0000FFFF, 0, 0, 18 },\r | |
| 257 | Package() {0x0000FFFF, 1, 0, 19 },\r | |
| 258 | Package() {0x0000FFFF, 2, 0, 16 },\r | |
| 259 | Package() {0x0000FFFF, 3, 0, 17 },\r | |
| 260 | })\r | |
| 261 | \r | |
| 262 | Name(PR07, Package()\r | |
| 263 | {\r | |
| 264 | // PCIE Port #4 Slot\r | |
| 265 | Package() {0x0000FFFF, 0, LNKD, 0 },\r | |
| 266 | Package() {0x0000FFFF, 1, LNKA, 0 },\r | |
| 267 | Package() {0x0000FFFF, 2, LNKB, 0 },\r | |
| 268 | Package() {0x0000FFFF, 3, LNKC, 0 },\r | |
| 269 | })\r | |
| 270 | \r | |
| 271 | Name(AR07, Package()\r | |
| 272 | {\r | |
| 273 | // PCIE Port #4 Slot\r | |
| 274 | Package() {0x0000FFFF, 0, 0, 19 },\r | |
| 275 | Package() {0x0000FFFF, 1, 0, 16 },\r | |
| 276 | Package() {0x0000FFFF, 2, 0, 17 },\r | |
| 277 | Package() {0x0000FFFF, 3, 0, 18 },\r | |
| 278 | })\r | |
| 279 | \r | |
| 280 | Name(PR01, Package()\r | |
| 281 | {\r | |
| 282 | // PCI slot 1\r | |
| 283 | Package() {0x0000FFFF, 0, LNKF, 0 },\r | |
| 284 | Package() {0x0000FFFF, 1, LNKG, 0 },\r | |
| 285 | Package() {0x0000FFFF, 2, LNKH, 0 },\r | |
| 286 | Package() {0x0000FFFF, 3, LNKE, 0 },\r | |
| 287 | // PCI slot 2\r | |
| 288 | Package() {0x0001FFFF, 0, LNKG, 0 },\r | |
| 289 | Package() {0x0001FFFF, 1, LNKF, 0 },\r | |
| 290 | Package() {0x0001FFFF, 2, LNKE, 0 },\r | |
| 291 | Package() {0x0001FFFF, 3, LNKH, 0 },\r | |
| 292 | // PCI slot 3\r | |
| 293 | Package() {0x0002FFFF, 0, LNKC, 0 },\r | |
| 294 | Package() {0x0002FFFF, 1, LNKD, 0 },\r | |
| 295 | Package() {0x0002FFFF, 2, LNKB, 0 },\r | |
| 296 | Package() {0x0002FFFF, 3, LNKA, 0 },\r | |
| 297 | // PCI slot 4\r | |
| 298 | Package() {0x0003FFFF, 0, LNKD, 0 },\r | |
| 299 | Package() {0x0003FFFF, 1, LNKC, 0 },\r | |
| 300 | Package() {0x0003FFFF, 2, LNKF, 0 },\r | |
| 301 | Package() {0x0003FFFF, 3, LNKG, 0 },\r | |
| 302 | })\r | |
| 303 | \r | |
| 304 | Name(AR01, Package()\r | |
| 305 | {\r | |
| 306 | // PCI slot 1\r | |
| 307 | Package() {0x0000FFFF, 0, 0, 21 },\r | |
| 308 | Package() {0x0000FFFF, 1, 0, 22 },\r | |
| 309 | Package() {0x0000FFFF, 2, 0, 23 },\r | |
| 310 | Package() {0x0000FFFF, 3, 0, 20 },\r | |
| 311 | // PCI slot 2\r | |
| 312 | Package() {0x0001FFFF, 0, 0, 22 },\r | |
| 313 | Package() {0x0001FFFF, 1, 0, 21 },\r | |
| 314 | Package() {0x0001FFFF, 2, 0, 20 },\r | |
| 315 | Package() {0x0001FFFF, 3, 0, 23 },\r | |
| 316 | // PCI slot 3\r | |
| 317 | Package() {0x0002FFFF, 0, 0, 18 },\r | |
| 318 | Package() {0x0002FFFF, 1, 0, 19 },\r | |
| 319 | Package() {0x0002FFFF, 2, 0, 17 },\r | |
| 320 | Package() {0x0002FFFF, 3, 0, 16 },\r | |
| 321 | // PCI slot 4\r | |
| 322 | Package() {0x0003FFFF, 0, 0, 19 },\r | |
| 323 | Package() {0x0003FFFF, 1, 0, 18 },\r | |
| 324 | Package() {0x0003FFFF, 2, 0, 21 },\r | |
| 325 | Package() {0x0003FFFF, 3, 0, 22 },\r | |
| 326 | })\r | |
| 327 | //---------------------------------------------------------------------------\r | |
| 328 | // List of IRQ resource buffers compatible with _PRS return format.\r | |
| 329 | //---------------------------------------------------------------------------\r | |
| 330 | // Naming legend:\r | |
| 331 | // RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.\r | |
| 332 | // Note. PRSy name is generated if IRQ Link name starts from "LNK".\r | |
| 333 | // HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.\r | |
| 334 | //---------------------------------------------------------------------------\r | |
| 335 | Name(PRSA, ResourceTemplate() // Link name: LNKA\r | |
| 336 | {\r | |
| 337 | IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}\r | |
| 338 | })\r | |
| 339 | Alias(PRSA,PRSB) // Link name: LNKB\r | |
| 340 | Alias(PRSA,PRSC) // Link name: LNKC\r | |
| 341 | Alias(PRSA,PRSD) // Link name: LNKD\r | |
| 342 | Alias(PRSA,PRSE) // Link name: LNKE\r | |
| 343 | Alias(PRSA,PRSF) // Link name: LNKF\r | |
| 344 | Alias(PRSA,PRSG) // Link name: LNKG\r | |
| 345 | Alias(PRSA,PRSH) // Link name: LNKH\r | |
| 346 | //---------------------------------------------------------------------------\r | |
| 347 | // Begin PCI tree object scope\r | |
| 348 | //---------------------------------------------------------------------------\r | |
| 349 | \r | |
| 350 | Device(PCI0) // PCI Bridge "Host Bridge"\r | |
| 351 | {\r | |
| 352 | Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy\r | |
| 353 | Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID\r | |
| 354 | Name(_ADR, 0x00000000)\r | |
| 355 | Method(^BN00, 0) { return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope\r | |
| 356 | Method(_BBN, 0) { return(BN00()) } // Bus number, optional for the Root PCI Bus\r | |
| 357 | Name(_UID, 0x0000) // Unique Bus ID, optional\r | |
| 358 | Name(_DEP, Package(0x1)\r | |
| 359 | {\r | |
| 360 | PEPD\r | |
| 361 | })\r | |
| 362 | \r | |
| 363 | Method(_PRT,0)\r | |
| 364 | {\r | |
| 365 | If(PICM) {Return(AR00)} // APIC mode\r | |
| 366 | Return (PR00) // PIC Mode\r | |
| 367 | } // end _PRT\r | |
| 368 | \r | |
| 369 | include("HOST_BUS.ASL")\r | |
| 370 | Device(LPCB) // LPC Bridge\r | |
| 371 | {\r | |
| 372 | Name(_ADR, 0x001F0000)\r | |
| 373 | include("LpcB.asl")\r | |
| 374 | } // end "LPC Bridge"\r | |
| 375 | \r | |
| 376 | } // end PCI0 Bridge "Host Bridge"\r | |
| 377 | } // end _SB scope\r |