]>
Commit | Line | Data |
---|---|---|
3cbfba02 DW |
1 | /**************************************************************************;\r |
2 | ;* *;\r | |
3 | ;* *;\r | |
4 | ;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r | |
5 | ;* Family of Customer Reference Boards. *;\r | |
6 | ;* *;\r | |
7 | ;* *;\r | |
8 | ;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r | |
9 | ;\r | |
10 | ; This program and the accompanying materials are licensed and made available under\r | |
11 | ; the terms and conditions of the BSD License that accompanies this distribution.\r | |
12 | ; The full text of the license may be found at\r | |
13 | ; http://opensource.org/licenses/bsd-license.php.\r | |
14 | ;\r | |
15 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | ;\r | |
18 | ;* *;\r | |
19 | ;* *;\r | |
20 | ;**************************************************************************/\r | |
21 | \r | |
22 | \r | |
23 | // Define the following External variables to prevent a WARNING when\r | |
24 | // using ASL.EXE and an ERROR when using IASL.EXE.\r | |
25 | \r | |
26 | External(PDC0)\r | |
27 | External(PDC1)\r | |
28 | External(PDC2)\r | |
29 | External(PDC3)\r | |
30 | External(CFGD)\r | |
31 | External(\_PR.CPU0._PPC, IntObj)\r | |
32 | External(\_SB.PCI0.LPCB.TPM.PTS, MethodObj)\r | |
33 | External(\_SB.STR3, DeviceObj)\r | |
34 | External(\_SB.I2C1.BATC, DeviceObj)\r | |
35 | External(\_SB.DPTF, DeviceObj)\r | |
36 | External(\_SB.TCHG, DeviceObj)\r | |
37 | External(\_SB.IAOE.PTSL)\r | |
38 | External(\_SB.IAOE.WKRS)\r | |
39 | \r | |
40 | //\r | |
41 | // Create a Global MUTEX.\r | |
42 | //\r | |
43 | Mutex(MUTX,0)\r | |
44 | \r | |
45 | \r | |
46 | \r | |
47 | // Port 80h Update:\r | |
48 | // Update 8 bits of the 32-bit Port 80h.\r | |
49 | //\r | |
50 | // Arguments:\r | |
51 | // Arg0: 0 = Write Port 80h, Bits 7:0 Only.\r | |
52 | // 1 = Write Port 80h, Bits 15:8 Only.\r | |
53 | // 2 = Write Port 80h, Bits 23:16 Only.\r | |
54 | // 3 = Write Port 80h, Bits 31:24 Only.\r | |
55 | // Arg1: 8-bit Value to write\r | |
56 | //\r | |
57 | // Return Value:\r | |
58 | // None\r | |
59 | \r | |
60 | Method(P8XH,2,Serialized)\r | |
61 | {\r | |
62 | If(LEqual(Arg0,0)) // Write Port 80h, Bits 7:0.\r | |
63 | {\r | |
64 | Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D)\r | |
65 | }\r | |
66 | \r | |
67 | If(LEqual(Arg0,1)) // Write Port 80h, Bits 15:8.\r | |
68 | {\r | |
69 | Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D)\r | |
70 | }\r | |
71 | \r | |
72 | If(LEqual(Arg0,2)) // Write Port 80h, Bits 23:16.\r | |
73 | {\r | |
74 | Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D)\r | |
75 | }\r | |
76 | \r | |
77 | If(LEqual(Arg0,3)) // Write Port 80h, Bits 31:24.\r | |
78 | {\r | |
79 | Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D)\r | |
80 | }\r | |
81 | \r | |
82 | }\r | |
83 | \r | |
84 | //\r | |
85 | // Define SW SMI port as an ACPI Operating Region to use for generate SW SMI.\r | |
86 | //\r | |
87 | OperationRegion (SPRT, SystemIO, 0xB2, 2)\r | |
88 | Field (SPRT, ByteAcc, Lock, Preserve)\r | |
89 | {\r | |
90 | SSMP, 8\r | |
91 | }\r | |
92 | \r | |
93 | // The _PIC Control Method is optional for ACPI design. It allows the\r | |
94 | // OS to inform the ASL code which interrupt controller is being used,\r | |
95 | // the 8259 or APIC. The reference code in this document will address\r | |
96 | // PCI IRQ Routing and resource allocation for both cases.\r | |
97 | //\r | |
98 | // The values passed into _PIC are:\r | |
99 | // 0 = 8259\r | |
100 | // 1 = IOAPIC\r | |
101 | \r | |
102 | Method(\_PIC,1)\r | |
103 | {\r | |
104 | Store(Arg0,GPIC)\r | |
105 | Store(Arg0,PICM)\r | |
106 | }\r | |
107 | \r | |
108 | OperationRegion(SWC0, SystemIO, 0x610, 0x0F)\r | |
109 | Field(SWC0, ByteAcc, NoLock, Preserve)\r | |
110 | {\r | |
111 | G1S, 8, //SWC GPE1_STS\r | |
112 | Offset(0x4),\r | |
113 | G1E, 8,\r | |
114 | Offset(0xA),\r | |
115 | G1S2, 8, //SWC GPE1_STS_2\r | |
116 | G1S3, 8 //SWC GPE1_STS_3\r | |
117 | }\r | |
118 | \r | |
119 | OperationRegion (SWC1, SystemIO, \PMBS, 0x2C)\r | |
120 | Field(SWC1, DWordAcc, NoLock, Preserve)\r | |
121 | {\r | |
122 | Offset(0x20),\r | |
123 | G0S, 32, //GPE0_STS\r | |
124 | Offset(0x28),\r | |
125 | G0EN, 32 //GPE0_EN\r | |
126 | }\r | |
127 | \r | |
128 | // Prepare to Sleep. The hook is called when the OS is about to\r | |
129 | // enter a sleep state. The argument passed is the numeric value of\r | |
130 | // the Sx state.\r | |
131 | \r | |
132 | Method(_PTS,1)\r | |
133 | {\r | |
134 | Store(0,P80D) // Zero out the entire Port 80h DWord.\r | |
135 | P8XH(0,Arg0) // Output Sleep State to Port 80h, Byte 0.\r | |
136 | \r | |
137 | //clear the 3 SWC status bits\r | |
138 | Store(Ones, G1S3)\r | |
139 | Store(Ones, G1S2)\r | |
140 | Store(1, G1S)\r | |
141 | \r | |
142 | //set SWC GPE1_EN\r | |
143 | Store(1,G1E)\r | |
144 | \r | |
145 | //clear GPE0_STS\r | |
146 | Store(Ones, G0S)\r | |
147 | \r | |
148 | \r | |
149 | If(LEqual(Arg0,3)) // If S3 Suspend\r | |
150 | {\r | |
151 | //\r | |
152 | // Disable Digital Thermal Sensor function when doing S3 suspend\r | |
153 | //\r | |
154 | If(CondRefOf(DTSE))\r | |
155 | {\r | |
156 | If(LGreaterEqual(DTSE, 0x01))\r | |
157 | {\r | |
158 | Store(30, DTSF) // DISABLE_UPDATE_DTS_EVERY_SMI\r | |
159 | Store(0xD0, SSMP) // DTS SW SMI\r | |
160 | }\r | |
161 | }\r | |
162 | }\r | |
163 | }\r | |
164 | \r | |
165 | // Wake. This hook is called when the OS is about to wake from a\r | |
166 | // sleep state. The argument passed is the numeric value of the\r | |
167 | // sleep state the system is waking from.\r | |
168 | Method(_WAK,1,Serialized)\r | |
169 | {\r | |
170 | P8XH(1,0xAB) // Beginning of _WAK.\r | |
171 | \r | |
172 | Notify(\_SB.PWRB,0x02)\r | |
173 | \r | |
174 | If(NEXP)\r | |
175 | {\r | |
176 | // Reinitialize the Native PCI Express after resume\r | |
177 | If(And(OSCC,0x02))\r | |
178 | {\r | |
179 | \_SB.PCI0.NHPG()\r | |
180 | }\r | |
181 | \r | |
182 | If(And(OSCC,0x04)) // PME control granted?\r | |
183 | {\r | |
184 | \_SB.PCI0.NPME()\r | |
185 | }\r | |
186 | }\r | |
187 | \r | |
188 | If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume\r | |
189 | {\r | |
190 | \r | |
191 | \r | |
192 | // If CMP is enabled, we may need to restore the C-State and/or\r | |
193 | // P-State configuration, as it may have been saved before the\r | |
194 | // configuration was finalized based on OS/driver support.\r | |
195 | //\r | |
196 | // CFGD[24] = Two or more cores enabled\r | |
197 | //\r | |
198 | If(And(CFGD,0x01000000))\r | |
199 | {\r | |
200 | //\r | |
201 | // If CMP and the OSYS is WinXP SP1, we will enable C1-SMI if\r | |
202 | // C-States are enabled.\r | |
203 | //\r | |
204 | // CFGD[7:4] = C4, C3, C2, C1 Capable/Enabled\r | |
205 | //\r | |
206 | //\r | |
207 | }\r | |
208 | \r | |
209 | // Windows XP SP2 does not properly restore the P-State\r | |
210 | // upon resume from S4 or S3 with degrade modes enabled.\r | |
211 | // Use the existing _PPC methods to cycle the available\r | |
212 | // P-States such that the processor ends up running at\r | |
213 | // the proper P-State.\r | |
214 | //\r | |
215 | // Note: For S4, another possible W/A is to always boot\r | |
216 | // the system in LFM.\r | |
217 | //\r | |
218 | If(LEqual(OSYS,2002))\r | |
219 | {\r | |
220 | If(And(CFGD,0x01))\r | |
221 | {\r | |
222 | If(LGreater(\_PR.CPU0._PPC,0))\r | |
223 | {\r | |
224 | Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)\r | |
225 | PNOT()\r | |
226 | Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)\r | |
227 | PNOT()\r | |
228 | }\r | |
229 | Else\r | |
230 | {\r | |
231 | Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)\r | |
232 | PNOT()\r | |
233 | Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)\r | |
234 | PNOT()\r | |
235 | }\r | |
236 | }\r | |
237 | }\r | |
238 | }\r | |
239 | Return(Package() {0,0})\r | |
240 | }\r | |
241 | \r | |
242 | // Power Notification:\r | |
243 | // Perform all needed OS notifications during a\r | |
244 | // Power Switch.\r | |
245 | //\r | |
246 | // Arguments:\r | |
247 | // None\r | |
248 | //\r | |
249 | // Return Value:\r | |
250 | // None\r | |
251 | \r | |
252 | Method(PNOT,0,Serialized)\r | |
253 | {\r | |
254 | // If MP enabled and driver support is present, notify all\r | |
255 | // processors.\r | |
256 | \r | |
257 | If(MPEN)\r | |
258 | {\r | |
259 | If(And(PDC0,0x0008))\r | |
260 | {\r | |
261 | Notify(\_PR.CPU0,0x80) // Eval CPU0 _PPC.\r | |
262 | \r | |
263 | If(And(PDC0,0x0010))\r | |
264 | {\r | |
265 | Sleep(100)\r | |
266 | Notify(\_PR.CPU0,0x81) // Eval _CST.\r | |
267 | }\r | |
268 | }\r | |
269 | \r | |
270 | If(And(PDC1,0x0008))\r | |
271 | {\r | |
272 | Notify(\_PR.CPU1,0x80) // Eval CPU1 _PPC.\r | |
273 | \r | |
274 | If(And(PDC1,0x0010))\r | |
275 | {\r | |
276 | Sleep(100)\r | |
277 | Notify(\_PR.CPU1,0x81) // Eval _CST.\r | |
278 | }\r | |
279 | }\r | |
280 | \r | |
281 | If(And(PDC2,0x0008))\r | |
282 | {\r | |
283 | Notify(\_PR.CPU2,0x80) // Eval CPU2 _PPC.\r | |
284 | \r | |
285 | If(And(PDC2,0x0010))\r | |
286 | {\r | |
287 | Sleep(100)\r | |
288 | Notify(\_PR.CPU2,0x81) // Eval _CST.\r | |
289 | }\r | |
290 | }\r | |
291 | \r | |
292 | If(And(PDC3,0x0008))\r | |
293 | {\r | |
294 | Notify(\_PR.CPU3,0x80) // Eval CPU3 _PPC.\r | |
295 | \r | |
296 | If(And(PDC3,0x0010))\r | |
297 | {\r | |
298 | Sleep(100)\r | |
299 | Notify(\_PR.CPU3,0x81) // Eval _CST.\r | |
300 | }\r | |
301 | }\r | |
302 | }\r | |
303 | Else\r | |
304 | {\r | |
305 | Notify(\_PR.CPU0,0x80) // Eval _PPC.\r | |
306 | Sleep(100)\r | |
307 | Notify(\_PR.CPU0,0x81) // Eval _CST\r | |
308 | }\r | |
309 | }\r | |
310 | \r | |
311 | //\r | |
312 | // System Bus\r | |
313 | //\r | |
314 | Scope(\_SB)\r | |
315 | {\r | |
316 | Name(CRTT, 110) // Processor critical temperature\r | |
317 | Name(ACTT, 77) // Active temperature limit for processor participant\r | |
318 | Name(GCR0, 70) // Critical temperature for Generic participant 0 in degree celsius\r | |
319 | Name(GCR1, 70) // Critical temperature for Generic participant 1 in degree celsius\r | |
320 | Name(GCR2, 70) // Critical temperature for Generic participant 2 in degree celsius\r | |
321 | Name(GCR3, 70) // Critical temperature for Generic participant 3 in degree celsius\r | |
322 | Name(GCR4, 70) // Critical temperature for Generic participant 4 in degree celsius\r | |
323 | Name(GCR5, 70) // Critical temperature for Generic participant 5 in degree celsius\r | |
324 | Name(GCR6, 70) // Critical temperature for Generic participant 6 in degree celsius\r | |
325 | Name(PST0, 60) // Passive temperature limit for Generic Participant 0 in degree celsius\r | |
326 | Name(PST1, 60) // Passive temperature limit for Generic Participant 1 in degree celsius\r | |
327 | Name(PST2, 60) // Passive temperature limit for Generic Participant 2 in degree celsius\r | |
328 | Name(PST3, 60) // Passive temperature limit for Generic Participant 3 in degree celsius\r | |
329 | Name(PST4, 60) // Passive temperature limit for Generic Participant 4 in degree celsius\r | |
330 | Name(PST5, 60) // Passive temperature limit for Generic Participant 5 in degree celsius\r | |
331 | Name(PST6, 60) // Passive temperature limit for Generic Participant 6 in degree celsius\r | |
332 | Name(LPMV, 3)\r | |
333 | Name(PDBG, 0) // DPTF Super debug option\r | |
334 | Name(PDPM, 1) // DPTF DPPM enable\r | |
335 | Name(PDBP, 1) // DPTF DBPT enable (dynamic battery protection technology)\r | |
336 | Name(DLPO, Package()\r | |
337 | {\r | |
338 | 0x1, // Revision\r | |
339 | 0x1, // LPO Enable\r | |
340 | 0x1, // LPO StartPState\r | |
341 | 25, // LPO StepSize\r | |
342 | 0x1, //\r | |
343 | 0x1, //\r | |
344 | })\r | |
345 | Name(BRQD, 0x00) // This is used to determine if DPTF display participant requested Brightness level change\r | |
346 | // or it is from Graphics driver. Value of 1 is for DPTF else it is 0\r | |
347 | \r | |
348 | Method(_INI,0)\r | |
349 | {\r | |
350 | // NVS has stale DTS data. Get and update the values\r | |
351 | // with current temperatures. Note that this will also\r | |
352 | // re-arm any AP Thermal Interrupts.\r | |
353 | // Read temperature settings from global NVS\r | |
354 | Store(DPCT, CRTT)\r | |
355 | Store(Subtract(DPPT, 8), ACTT) // Active Trip point = Passive trip point - 8\r | |
356 | Store(DGC0, GCR0)\r | |
357 | Store(DGC0, GCR1)\r | |
358 | Store(DGC1, GCR2)\r | |
359 | Store(DGC1, GCR3)\r | |
360 | Store(DGC1, GCR4)\r | |
361 | Store(DGC2, GCR5)\r | |
362 | Store(DGC2, GCR6)\r | |
363 | Store(DGP0, PST0)\r | |
364 | Store(DGP0, PST1)\r | |
365 | Store(DGP1, PST2)\r | |
366 | Store(DGP1, PST3)\r | |
367 | Store(DGP1, PST4)\r | |
368 | Store(DGP2, PST5)\r | |
369 | Store(DGP2, PST6)\r | |
370 | // Read Current low power mode setting from global NVS\r | |
371 | Store(DLPM, LPMV)\r | |
372 | \r | |
373 | \r | |
374 | // Update DPTF Super Debug option\r | |
375 | Store(DDBG, PDBG)\r | |
376 | \r | |
377 | \r | |
378 | // Update DPTF LPO Options\r | |
379 | Store(LPOE, Index(DLPO,1))\r | |
380 | Store(LPPS, Index(DLPO,2))\r | |
381 | Store(LPST, Index(DLPO,3))\r | |
382 | Store(LPPC, Index(DLPO,4))\r | |
383 | Store(LPPF, Index(DLPO,5))\r | |
384 | Store(DPME, PDPM)\r | |
385 | }\r | |
386 | \r | |
387 | // Define a (Control Method) Power Button.\r | |
388 | Device(PWRB)\r | |
389 | {\r | |
390 | Name(_HID,EISAID("PNP0C0C"))\r | |
391 | \r | |
392 | // GPI_SUS0 = GPE16 = Waketime SCI. The PRW isn't working when\r | |
393 | // placed in any of the logical locations ( PS2K, PS2M),\r | |
394 | // so a Power Button Device was created specifically\r | |
395 | // for the WAKETIME_SCI PRW.\r | |
396 | \r | |
397 | Name(_PRW, Package() {16,4})\r | |
398 | }\r | |
399 | \r | |
400 | Device(SLPB)\r | |
401 | {\r | |
402 | Name(_HID, EISAID("PNP0C0E"))\r | |
403 | } // END SLPB\r | |
404 | \r | |
405 | Scope(PCI0)\r | |
406 | {\r | |
407 | Method(_INI,0)\r | |
408 | {\r | |
409 | // Determine the OS and store the value, where:\r | |
410 | //\r | |
411 | // OSYS = 2009 = Windows 7 and Windows Server 2008 R2.\r | |
412 | // OSYS = 2012 = Windows 8 and Windows Server 2012.\r | |
413 | //\r | |
414 | // Assume Windows 7 at a minimum.\r | |
415 | \r | |
416 | Store(2009,OSYS)\r | |
417 | \r | |
418 | // Check for a specific OS which supports _OSI.\r | |
419 | \r | |
420 | If(CondRefOf(\_OSI,Local0))\r | |
421 | {\r | |
422 | // Linux returns _OSI = TRUE for numerous Windows\r | |
423 | // strings so that it is fully compatible with\r | |
424 | // BIOSes available in the market today. There are\r | |
425 | // currently 2 known exceptions to this model:\r | |
426 | // 1) Video Repost - Linux supports S3 without\r | |
427 | // requireing a Driver, meaning a Video\r | |
428 | // Repost will be required.\r | |
429 | // 2) On-Screen Branding - a full CMT Logo\r | |
430 | // is limited to the WIN2K and WINXP\r | |
431 | // Operating Systems only.\r | |
432 | \r | |
433 | // Use OSYS for Windows Compatibility.\r | |
434 | If(\_OSI("Windows 2009")) // Windows 7 or Windows Server 2008 R2\r | |
435 | {\r | |
436 | Store(2009,OSYS)\r | |
437 | }\r | |
438 | If(\_OSI("Windows 2012")) // Windows 8 or Windows Server 2012\r | |
439 | {\r | |
440 | Store(2012,OSYS)\r | |
441 | }\r | |
442 | If(\_OSI("Windows 2013")) //Windows Blue\r | |
443 | {\r | |
444 | Store(2013,OSYS)\r | |
445 | }\r | |
446 | \r | |
447 | //\r | |
448 | // If CMP is enabled, enable SMM C-State\r | |
449 | // coordination. SMM C-State coordination\r | |
450 | // will be disabled in _PDC if driver support\r | |
451 | // for independent C-States deeper than C1\r | |
452 | // is indicated.\r | |
453 | }\r | |
454 | }\r | |
455 | \r | |
456 | Method(NHPG,0,Serialized)\r | |
457 | {\r | |
458 | \r | |
459 | }\r | |
460 | \r | |
461 | Method(NPME,0,Serialized)\r | |
462 | {\r | |
463 | \r | |
464 | }\r | |
465 | } // end Scope(PCI0)\r | |
466 | \r | |
467 | Device (GPED) //virtual GPIO device for ASL based AC/Battery/Expection notification\r | |
468 | {\r | |
469 | Name (_ADR, 0)\r | |
470 | Name (_HID, "INT0002")\r | |
471 | Name (_CID, "INT0002")\r | |
472 | Name (_DDN, "Virtual GPIO controller" )\r | |
473 | Name (_UID, 1)\r | |
474 | \r | |
475 | Method (_CRS, 0x0, Serialized)\r | |
476 | {\r | |
477 | Name (RBUF, ResourceTemplate ()\r | |
478 | {\r | |
479 | Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x9} // Was 9\r | |
480 | })\r | |
481 | Return (RBUF)\r | |
482 | }\r | |
483 | \r | |
484 | Method (_STA, 0x0, NotSerialized)\r | |
485 | {\r | |
486 | Return(0x0)\r | |
487 | }\r | |
488 | \r | |
489 | Method (_AEI, 0x0, Serialized)\r | |
490 | {\r | |
491 | Name(RBUF, ResourceTemplate()\r | |
492 | {\r | |
493 | GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullDown,,"\\_SB.GPED",) {2} //pin 2\r | |
494 | })\r | |
495 | Return(RBUF)\r | |
496 | }\r | |
497 | \r | |
498 | Method(_E02) // _Exx method will be called when interrupt is raised\r | |
499 | {\r | |
500 | If (LEqual (PWBS, 1))\r | |
501 | {\r | |
502 | Store (1, PWBS) //Clear PowerButton Status\r | |
503 | }\r | |
504 | If (LEqual (PMEB, 1))\r | |
505 | {\r | |
506 | Store (1, PMEB) //Clear PME_B0_STS\r | |
507 | }\r | |
508 | If (LEqual (\_SB.PCI0.SATA.PMES, 1))\r | |
509 | {\r | |
510 | Store (1, \_SB.PCI0.SATA.PMES)\r | |
511 | Notify (\_SB.PCI0.SATA, 0x02)\r | |
512 | }\r | |
513 | //\r | |
514 | // eMMC 4.41\r | |
515 | //\r | |
516 | If (LAnd(LEqual (\_SB.PCI0.EM41.PMES, 1), LEqual(PCIM, 1)))\r | |
517 | {\r | |
518 | Store (1, \_SB.PCI0.EM41.PMES)\r | |
519 | Notify (\_SB.PCI0.EM41, 0x02)\r | |
520 | }\r | |
521 | \r | |
522 | //\r | |
523 | // eMMC 4.5\r | |
524 | //\r | |
525 | If (LAnd(LEqual (\_SB.PCI0.EM45.PMES, 1), LEqual(PCIM, 1)))\r | |
526 | {\r | |
527 | Store (1, \_SB.PCI0.EM45.PMES)\r | |
528 | Notify (\_SB.PCI0.EM45, 0x02)\r | |
529 | }\r | |
530 | \r | |
531 | If (LEqual(HDAD, 0))\r | |
532 | {\r | |
533 | If (LEqual (\_SB.PCI0.HDEF.PMES, 1))\r | |
534 | {\r | |
535 | Store (1, \_SB.PCI0.HDEF.PMES)\r | |
536 | Notify (\_SB.PCI0.HDEF, 0x02)\r | |
537 | }\r | |
538 | }\r | |
539 | \r | |
540 | If (LEqual (\_SB.PCI0.EHC1.PMES, 1))\r | |
541 | {\r | |
542 | Store (1, \_SB.PCI0.EHC1.PMES)\r | |
543 | Notify (\_SB.PCI0.EHC1, 0x02)\r | |
544 | }\r | |
545 | If (LEqual (\_SB.PCI0.XHC1.PMES, 1))\r | |
546 | {\r | |
547 | Store (1, \_SB.PCI0.XHC1.PMES)\r | |
548 | Notify (\_SB.PCI0.XHC1, 0x02)\r | |
549 | }\r | |
550 | If (LEqual (\_SB.PCI0.SEC0.PMES, 1))\r | |
551 | {\r | |
552 | Or (\_SB.PCI0.SEC0.PMES, Zero, \_SB.PCI0.SEC0.PMES)\r | |
553 | Notify (\_SB.PCI0.SEC0, 0x02)\r | |
554 | }\r | |
555 | }\r | |
556 | } // Device (GPED)\r | |
557 | \r | |
558 | //--------------------\r | |
559 | // GPIO\r | |
560 | //--------------------\r | |
561 | Device (GPO0)\r | |
562 | {\r | |
563 | Name (_ADR, 0)\r | |
564 | Name (_HID, "INT33FC")\r | |
565 | Name (_CID, "INT33B2")\r | |
566 | Name (_DDN, "ValleyView2 General Purpose Input/Output (GPIO) controller" )\r | |
567 | Name (_UID, 1)\r | |
568 | Method (_CRS, 0x0, Serialized)\r | |
569 | {\r | |
570 | Name (RBUF, ResourceTemplate ()\r | |
571 | {\r | |
572 | Memory32Fixed (ReadWrite, 0x0FED0C000, 0x00001000)\r | |
573 | Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {49}\r | |
574 | \r | |
575 | })\r | |
576 | Return (RBUF)\r | |
577 | }\r | |
578 | \r | |
579 | Method (_STA, 0x0, NotSerialized)\r | |
580 | {\r | |
581 | //\r | |
582 | // GPO driver will report present if any of below New IO bus exist\r | |
583 | //\r | |
584 | If (LOr(LEqual(L11D, 0), LEqual(L12D, 0))) // LPIO1 PWM #1 or #2 exist\r | |
585 | { Return(0xF) }\r | |
586 | If (LOr(LEqual(L13D, 0), LEqual(L14D, 0))) // LPIO1 HS-UART #1 or #2 exist\r | |
587 | { Return(0xF) }\r | |
588 | If (LOr(LEqual(L15D, 0), LEqual(SD1D, 0))) // LPIO1 SPI or SCC SDIO #1 exist\r | |
589 | { Return(0xF) }\r | |
590 | If (LOr(LEqual(SD2D, 0), LEqual(SD3D, 0))) // SCC SDIO #2 or #3 exist\r | |
591 | { Return(0xF) }\r | |
592 | If (LOr(LEqual(L21D, 0), LEqual(L22D, 0))) // LPIO2 I2C #1 or #2 exist\r | |
593 | { Return(0xF) }\r | |
594 | If (LOr(LEqual(L23D, 0), LEqual(L24D, 0))) // LPIO2 I2C #3 or #4 exist\r | |
595 | { Return(0xF) }\r | |
596 | If (LOr(LEqual(L25D, 0), LEqual(L26D, 0))) // LPIO2 I2C #5 or #6 exist\r | |
597 | { Return(0xF) }\r | |
598 | If (LEqual(L27D, 0)) // LPIO2 I2C #7 exist\r | |
599 | { Return(0xF) }\r | |
600 | \r | |
601 | Return(0x0)\r | |
602 | }\r | |
603 | \r | |
604 | // Track status of GPIO OpRegion availability for this controller\r | |
605 | Name(AVBL, 0)\r | |
606 | Method(_REG,2)\r | |
607 | {\r | |
608 | If (Lequal(Arg0, 8))\r | |
609 | {\r | |
610 | Store(Arg1, ^AVBL)\r | |
611 | }\r | |
612 | }\r | |
613 | \r | |
614 | OperationRegion(GPOP, SystemIo, \GPBS, 0x50)\r | |
615 | Field(GPOP, ByteAcc, NoLock, Preserve) {\r | |
616 | Offset(0x28), // cfio_ioreg_SC_GP_LVL_63_32_ - [GPIO_BASE_ADDRESS] + 28h\r | |
617 | , 21,\r | |
618 | BTD3, 1, //This field is not used. Pin not defined in schematics. Closest is GPIO_S5_35 - COMBO_BT_WAKEUP\r | |
619 | Offset(0x48), // cfio_ioreg_SC_GP_LVL_95_64_ - [GPIO_BASE_ADDRESS] + 48h\r | |
620 | , 30,\r | |
621 | SHD3, 1 //GPIO_S0_SC_95 - SENS_HUB_RST_N\r | |
622 | }\r | |
623 | \r | |
624 | \r | |
625 | \r | |
626 | } // Device (GPO0)\r | |
627 | \r | |
628 | Device (GPO1)\r | |
629 | {\r | |
630 | Name (_ADR, 0)\r | |
631 | Name (_HID, "INT33FC")\r | |
632 | Name (_CID, "INT33B2")\r | |
633 | Name (_DDN, "ValleyView2 GPNCORE controller" )\r | |
634 | Name (_UID, 2)\r | |
635 | Method (_CRS, 0x0, Serialized)\r | |
636 | {\r | |
637 | Name (RBUF, ResourceTemplate ()\r | |
638 | {\r | |
639 | Memory32Fixed (ReadWrite, 0x0FED0D000, 0x00001000)\r | |
640 | Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {48}\r | |
641 | })\r | |
642 | Return (RBUF)\r | |
643 | }\r | |
644 | \r | |
645 | Method (_STA, 0x0, NotSerialized)\r | |
646 | {\r | |
647 | Return(\_SB.GPO0._STA)\r | |
648 | }\r | |
649 | } // Device (GPO1)\r | |
650 | \r | |
651 | Device (GPO2)\r | |
652 | {\r | |
653 | Name (_ADR, 0)\r | |
654 | Name (_HID, "INT33FC")\r | |
655 | Name (_CID, "INT33B2")\r | |
656 | Name (_DDN, "ValleyView2 GPSUS controller" )\r | |
657 | Name (_UID, 3)\r | |
658 | Method (_CRS, 0x0, Serialized)\r | |
659 | {\r | |
660 | Name (RBUF, ResourceTemplate ()\r | |
661 | {\r | |
662 | Memory32Fixed (ReadWrite, 0x0FED0E000, 0x00001000)\r | |
663 | Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {50}\r | |
664 | })\r | |
665 | Return (RBUF)\r | |
666 | }\r | |
667 | \r | |
668 | Method (_STA, 0x0, NotSerialized)\r | |
669 | {\r | |
670 | Return(^^GPO0._STA)\r | |
671 | }\r | |
672 | \r | |
673 | // Track status of GPIO OpRegion availability for this controller\r | |
674 | Name(AVBL, 0)\r | |
675 | Method(_REG,2)\r | |
676 | {\r | |
677 | If (Lequal(Arg0, 8))\r | |
678 | {\r | |
679 | Store(Arg1, ^AVBL)\r | |
680 | }\r | |
681 | }\r | |
682 | //Manipulate GPIO line using GPIO operation regions.\r | |
683 | Name (GMOD, ResourceTemplate () //One method of creating a Connection for OpRegion accesses in Field definitions\r | |
684 | {\r | |
685 | //is creating a named object that refers to the connection attributes\r | |
686 | GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2") {21} //sus 21+128 BT+WLAN_ENABLE\r | |
687 | })\r | |
688 | \r | |
689 | OperationRegion(GPOP, SystemIo, \GPBS, 0x100)\r | |
690 | Field(GPOP, ByteAcc, NoLock, Preserve) {\r | |
691 | Offset(0x88), // cfio_ioreg_SUS_GP_LVL_31_0_ - [GPIO_BASE_ADDRESS] + 88h\r | |
692 | , 20,\r | |
693 | WFD3, 1\r | |
694 | }\r | |
695 | \r | |
696 | \r | |
697 | } // Device (GPO2)\r | |
698 | include ("PchScc.asl")\r | |
699 | include ("PchLpss.asl")\r | |
700 | \r | |
701 | Scope(I2C7)\r | |
702 | {\r | |
703 | \r | |
704 | } //End Scope(I2C7)\r | |
705 | \r | |
3cbfba02 DW |
706 | } // end Scope(\_SB)\r |
707 | \r | |
708 | Name(PICM, 0) // Global Name, returns current Interrupt controller mode; updated from _PIC control method\r | |
709 | \r |