[mirror_edk2.git] / Vlv2DeviceRefCodePkg / AcpiTablesPCAT / RhProxy.asl

/** @file\r
  SSDT for RhProxy Driver.\r
\r
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
DefinitionBlock ("RHPX.aml", "SSDT", 1, "MSFT", "RHPROXY", 1)\r
{\r
    Scope (\_SB)\r
    {\r
        //\r
        // Test peripheral device node for MinnowBoardMax\r
        //\r
        Device(RHPX)\r
        {\r
            Name(_HID, "MSFT8000")\r
            Name(_CID, "MSFT8000")\r
            Name(_UID, 1)\r
\r
            Name(_CRS, ResourceTemplate() \r
            {  \r
                // Index 0 \r
                SPISerialBus(            // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI\r
                    1,                     // Device selection\r
                    PolarityLow,           // Device selection polarity\r
                    FourWireMode,          // wiremode\r
                    8,                     // databit len\r
                    ControllerInitiated,   // slave mode\r
                    8000000,               // Connection speed\r
                    ClockPolarityLow,      // Clock polarity\r
                    ClockPhaseSecond,      // clock phase\r
                    "\\_SB.SPI1",          // ResourceSource: SPI bus controller name\r
                    0,                     // ResourceSourceIndex\r
                    ResourceConsumer,      // Resource usage\r
                    JSPI,                  // DescriptorName: creates name for offset of resource descriptor\r
                    )                      // Vendor Data  \r
    \r
                // Index 1     \r
                I2CSerialBus(            // Pin 13, 15 of JP1, for SIO_I2C5 (signal)\r
                    0xFF,                  // SlaveAddress: bus address (TBD)\r
                    ,                      // SlaveMode: default to ControllerInitiated\r
                    400000,                // ConnectionSpeed: in Hz\r
                    ,                      // Addressing Mode: default to 7 bit\r
                    "\\_SB.I2C6",          // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))\r
                    ,\r
                    ,\r
                    JI2C,                  // Descriptor Name: creates name for offset of resource descriptor\r
                    )                      // VendorData\r
    \r
                // Index 2\r
                UARTSerialBus(           // Pin 17, 19 of JP1, for SIO_UART2\r
                    115200,                // InitialBaudRate: in bits ber second\r
                    ,                      // BitsPerByte: default to 8 bits\r
                    ,                      // StopBits: Defaults to one bit\r
                    0xfc,                  // LinesInUse: 8 1-bit flags to declare line enabled\r
                    ,                      // IsBigEndian: default to LittleEndian\r
                    ,                      // Parity: Defaults to no parity\r
                    ,                      // FlowControl: Defaults to no flow control\r
                    32,                    // ReceiveBufferSize\r
                    32,                    // TransmitBufferSize\r
                    "\\_SB.URT2",          // ResourceSource: UART bus controller name\r
                    ,\r
                    ,\r
                    UAR2,                  // DescriptorName: creates name for offset of resource descriptor\r
                    )                      \r
    \r
                // Index 3\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0}  // Pin 21 of JP1 (GPIO_S5[00])\r
                // Index 4\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0} \r
    \r
                // Index 5\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1}  // Pin 23 of JP1 (GPIO_S5[01])\r
                // Index 6\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}\r
    \r
                // Index 7\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2}  // Pin 25 of JP1 (GPIO_S5[02])\r
                // Index 8\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2} \r
    \r
                // Index 9\r
                UARTSerialBus(           // Pin 6, 8, 10, 12 of JP1, for SIO_UART1\r
                    115200,                // InitialBaudRate: in bits ber second\r
                    ,                      // BitsPerByte: default to 8 bits\r
                    ,                      // StopBits: Defaults to one bit\r
                    0xfc,                  // LinesInUse: 8 1-bit flags to declare line enabled\r
                    ,                      // IsBigEndian: default to LittleEndian\r
                    ,                      // Parity: Defaults to no parity\r
                    FlowControlHardware,   // FlowControl: Defaults to no flow control\r
                    32,                    // ReceiveBufferSize\r
                    32,                    // TransmitBufferSize\r
                    "\\_SB.URT1",          // ResourceSource: UART bus controller name\r
                    ,\r
                    ,\r
                    UAR1,              // DescriptorName: creates name for offset of resource descriptor\r
                    )  \r
    \r
                // Index 10\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62}  // Pin 14 of JP1 (GPIO_SC[62])\r
                // Index 11\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62} \r
\r
                // Index 12\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63}  // Pin 16 of JP1 (GPIO_SC[63])\r
                // Index 13\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63} \r
    \r
                // Index 14\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65}  // Pin 18 of JP1 (GPIO_SC[65])\r
                // Index 15\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65} \r
    \r
                // Index 16\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64}  // Pin 20 of JP1 (GPIO_SC[64])\r
                // Index 17\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64} \r
    \r
                // Index 18\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94}  // Pin 22 of JP1 (GPIO_SC[94])\r
                // Index 19\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94} \r
    \r
                // Index 20\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95}  // Pin 24 of JP1 (GPIO_SC[95])\r
                // Index 21\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95} \r
    \r
                // Index 22\r
                GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54}  // Pin 26 of JP1 (GPIO_SC[54])\r
                // Index 23\r
                GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}\r
            })\r
    \r
            Name(_DSD, Package() \r
            {\r
                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),\r
                Package() \r
                {\r
                    // SPI Mapping\r
                    Package(2) { "bus-SPI-SPI0", Package() { 0 }},\r
\r
                    // TODO: Intel will need to provide the right value for SPI0 properties\r
                    Package(2) { "SPI0-MinClockInHz", 100000 },\r
                    Package(2) { "SPI0-MaxClockInHz", 15000000 },\r
                    // SupportedDataBitLengths takes a list of support data bit length\r
                    // Example : Package(2) { "SPI0-SupportedDataBitLengths", Package() { 8, 7, 16 }},\r
                    Package(2) { "SPI0-SupportedDataBitLengths", Package() { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }},\r
                    // I2C Mapping\r
                    Package(2) { "bus-I2C-I2C5", Package() { 1 }},\r
                    // UART Mapping\r
                    Package(2) { "bus-UART-UART2", Package() { 2 }},\r
                    Package(2) { "bus-UART-UART1", Package() { 9 }},\r
                }\r
            })\r
        }\r
    }\r
}
Commit	Line	Data
b2499fe6 DW	1	/** @file\r
	2	SSDT for RhProxy Driver.\r
	3	\r
	4	Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
7ede8060	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
b2499fe6 DW	6	\r
	7	**/\r
	8	\r
	9	DefinitionBlock ("RHPX.aml", "SSDT", 1, "MSFT", "RHPROXY", 1)\r
	10	{\r
	11	Scope (\_SB)\r
	12	{\r
	13	//\r
	14	// Test peripheral device node for MinnowBoardMax\r
	15	//\r
	16	Device(RHPX)\r
	17	{\r
	18	Name(_HID, "MSFT8000")\r
	19	Name(_CID, "MSFT8000")\r
	20	Name(_UID, 1)\r
	21	\r
	22	Name(_CRS, ResourceTemplate() \r
	23	{ \r
	24	// Index 0 \r
	25	SPISerialBus( // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI\r
	26	1, // Device selection\r
	27	PolarityLow, // Device selection polarity\r
	28	FourWireMode, // wiremode\r
	29	8, // databit len\r
	30	ControllerInitiated, // slave mode\r
	31	8000000, // Connection speed\r
	32	ClockPolarityLow, // Clock polarity\r
	33	ClockPhaseSecond, // clock phase\r
	34	"\\_SB.SPI1", // ResourceSource: SPI bus controller name\r
	35	0, // ResourceSourceIndex\r
	36	ResourceConsumer, // Resource usage\r
	37	JSPI, // DescriptorName: creates name for offset of resource descriptor\r
	38	) // Vendor Data \r
	39	\r
	40	// Index 1 \r
	41	I2CSerialBus( // Pin 13, 15 of JP1, for SIO_I2C5 (signal)\r
	42	0xFF, // SlaveAddress: bus address (TBD)\r
	43	, // SlaveMode: default to ControllerInitiated\r
	44	400000, // ConnectionSpeed: in Hz\r
	45	, // Addressing Mode: default to 7 bit\r
	46	"\\_SB.I2C6", // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))\r
	47	,\r
	48	,\r
	49	JI2C, // Descriptor Name: creates name for offset of resource descriptor\r
	50	) // VendorData\r
	51	\r
	52	// Index 2\r
	53	UARTSerialBus( // Pin 17, 19 of JP1, for SIO_UART2\r
	54	115200, // InitialBaudRate: in bits ber second\r
	55	, // BitsPerByte: default to 8 bits\r
	56	, // StopBits: Defaults to one bit\r
	57	0xfc, // LinesInUse: 8 1-bit flags to declare line enabled\r
	58	, // IsBigEndian: default to LittleEndian\r
	59	, // Parity: Defaults to no parity\r
	60	, // FlowControl: Defaults to no flow control\r
	61	32, // ReceiveBufferSize\r
	62	32, // TransmitBufferSize\r
	63	"\\_SB.URT2", // ResourceSource: UART bus controller name\r
	64	,\r
	65	,\r
	66	UAR2, // DescriptorName: creates name for offset of resource descriptor\r
	67	) \r
	68	\r
	69	// Index 3\r
70	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0} // Pin 21 of JP1 (GPIO_S5[00])\r
71	// Index 4\r
72	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0} \r
73	\r
74	// Index 5\r
75	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1} // Pin 23 of JP1 (GPIO_S5[01])\r
76	// Index 6\r
77	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}\r
78	\r
79	// Index 7\r
80	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2} // Pin 25 of JP1 (GPIO_S5[02])\r
81	// Index 8\r
82	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2} \r
83	\r
84	// Index 9\r
85	UARTSerialBus( // Pin 6, 8, 10, 12 of JP1, for SIO_UART1\r
86	115200, // InitialBaudRate: in bits ber second\r
87	, // BitsPerByte: default to 8 bits\r
88	, // StopBits: Defaults to one bit\r
89	0xfc, // LinesInUse: 8 1-bit flags to declare line enabled\r
90	, // IsBigEndian: default to LittleEndian\r
91	, // Parity: Defaults to no parity\r
92	FlowControlHardware, // FlowControl: Defaults to no flow control\r
93	32, // ReceiveBufferSize\r
94	32, // TransmitBufferSize\r
95	"\\_SB.URT1", // ResourceSource: UART bus controller name\r
96	,\r
97	,\r
98	UAR1, // DescriptorName: creates name for offset of resource descriptor\r
99	) \r
100	\r
101	// Index 10\r
102	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62} // Pin 14 of JP1 (GPIO_SC[62])\r
103	// Index 11\r
104	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62} \r
105	\r
106	// Index 12\r
107	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63} // Pin 16 of JP1 (GPIO_SC[63])\r
108	// Index 13\r
109	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63} \r
110	\r
111	// Index 14\r
112	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65} // Pin 18 of JP1 (GPIO_SC[65])\r
113	// Index 15\r
114	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65} \r
115	\r
116	// Index 16\r
117	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64} // Pin 20 of JP1 (GPIO_SC[64])\r
118	// Index 17\r
119	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64} \r
120	\r
121	// Index 18\r
122	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94} // Pin 22 of JP1 (GPIO_SC[94])\r
123	// Index 19\r
124	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94} \r
125	\r
126	// Index 20\r
127	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95} // Pin 24 of JP1 (GPIO_SC[95])\r
128	// Index 21\r
129	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95} \r
130	\r
131	// Index 22\r
132	GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54} // Pin 26 of JP1 (GPIO_SC[54])\r
133	// Index 23\r
134	GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}\r
135	})\r
136	\r
137	Name(_DSD, Package() \r
138	{\r
139	ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),\r
140	Package() \r
141	{\r
142	// SPI Mapping\r
143	Package(2) { "bus-SPI-SPI0", Package() { 0 }},\r
144	\r
145	// TODO: Intel will need to provide the right value for SPI0 properties\r
49a228ca DW	146	Package(2) { "SPI0-MinClockInHz", 100000 },\r
49a228ca DW	147	Package(2) { "SPI0-MaxClockInHz", 15000000 },\r
b2499fe6 DW	148	// SupportedDataBitLengths takes a list of support data bit length\r
b2499fe6 DW	149	// Example : Package(2) { "SPI0-SupportedDataBitLengths", Package() { 8, 7, 16 }},\r
49a228ca DW	150	Package(2) { "SPI0-SupportedDataBitLengths", Package() { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }},\r
49a228ca DW	151	// I2C Mapping\r
b2499fe6 DW	152	Package(2) { "bus-I2C-I2C5", Package() { 1 }},\r
	153	// UART Mapping\r
	154	Package(2) { "bus-UART-UART2", Package() { 2 }},\r
	155	Package(2) { "bus-UART-UART1", Package() { 9 }},\r
	156	}\r
	157	})\r
	158	}\r
	159	}\r
	160	}