projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /*++\r |
| 2 | \r | |
| 3 | Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r | |
| 4 | \r | |
| 7ede8060 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
6 | \r |
| 7 | \r | |
| 8 | \r | |
| 9 | Module Name:\r | |
| 10 | \r | |
| 11 | PlatformMemoryRange.h\r | |
| 12 | \r | |
| 13 | Abstract:\r | |
| 14 | \r | |
| 15 | Platform Memory Range PPI as defined in EFI 2.0\r | |
| 16 | \r | |
| 17 | PPI for reserving special purpose memory ranges.\r | |
| 18 | \r | |
| 19 | --*/\r | |
| 20 | //\r | |
| 21 | //\r | |
| 22 | #ifndef _PEI_PLATFORM_MEMORY_RANGE_H_\r | |
| 23 | #define _PEI_PLATFORM_MEMORY_RANGE_H_\r | |
| 24 | \r | |
| 25 | #define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \\r | |
| 26 | { \\r | |
| 27 | 0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \\r | |
| 28 | }\r | |
| 29 | \r | |
| 30 | typedef struct _PEI_PLATFORM_MEMORY_RANGE_PPI PEI_PLATFORM_MEMORY_RANGE_PPI ;\r | |
| 31 | \r | |
| 32 | #define PEI_MEMORY_RANGE_OPTION_ROM UINT32\r | |
| 33 | \r | |
| 34 | #define PEI_MR_OPTION_ROM_ALL 0xFFFFFFFF\r | |
| 35 | #define PEI_MR_OPTION_ROM_NONE 0x00000000\r | |
| 36 | #define PEI_MR_OPTION_ROM_C0000_16K 0x00000001\r | |
| 37 | #define PEI_MR_OPTION_ROM_C4000_16K 0x00000002\r | |
| 38 | #define PEI_MR_OPTION_ROM_C8000_16K 0x00000004\r | |
| 39 | #define PEI_MR_OPTION_ROM_CC000_16K 0x00000008\r | |
| 40 | #define PEI_MR_OPTION_ROM_D0000_16K 0x00000010\r | |
| 41 | #define PEI_MR_OPTION_ROM_D4000_16K 0x00000020\r | |
| 42 | #define PEI_MR_OPTION_ROM_D8000_16K 0x00000040\r | |
| 43 | #define PEI_MR_OPTION_ROM_DC000_16K 0x00000080\r | |
| 44 | #define PEI_MR_OPTION_ROM_E0000_16K 0x00000100\r | |
| 45 | #define PEI_MR_OPTION_ROM_E4000_16K 0x00000200\r | |
| 46 | #define PEI_MR_OPTION_ROM_E8000_16K 0x00000400\r | |
| 47 | #define PEI_MR_OPTION_ROM_EC000_16K 0x00000800\r | |
| 48 | #define PEI_MR_OPTION_ROM_F0000_16K 0x00001000\r | |
| 49 | #define PEI_MR_OPTION_ROM_F4000_16K 0x00002000\r | |
| 50 | #define PEI_MR_OPTION_ROM_F8000_16K 0x00004000\r | |
| 51 | #define PEI_MR_OPTION_ROM_FC000_16K 0x00008000\r | |
| 52 | \r | |
| 53 | //\r | |
| 54 | // SMRAM Memory Range\r | |
| 55 | //\r | |
| 56 | #define PEI_MEMORY_RANGE_SMRAM UINT32\r | |
| 57 | #define PEI_MR_SMRAM_ALL 0xFFFFFFFF\r | |
| 58 | #define PEI_MR_SMRAM_NONE 0x00000000\r | |
| 59 | #define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000\r | |
| 60 | #define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000\r | |
| 61 | #define PEI_MR_SMRAM_ABSEG_MASK 0x00010000\r | |
| 62 | #define PEI_MR_SMRAM_HSEG_MASK 0x00020000\r | |
| 63 | #define PEI_MR_SMRAM_TSEG_MASK 0x00040000\r | |
| 64 | //\r | |
| 65 | // If adding additional entries, SMRAM Size\r | |
| 66 | // is a multiple of 128KB.\r | |
| 67 | //\r | |
| 68 | #define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF\r | |
| 69 | #define PEI_MR_SMRAM_SIZE_128K_MASK 0x00000001\r | |
| 70 | #define PEI_MR_SMRAM_SIZE_256K_MASK 0x00000002\r | |
| 71 | #define PEI_MR_SMRAM_SIZE_512K_MASK 0x00000004\r | |
| 72 | #define PEI_MR_SMRAM_SIZE_1024K_MASK 0x00000008\r | |
| 73 | #define PEI_MR_SMRAM_SIZE_2048K_MASK 0x00000010\r | |
| 74 | #define PEI_MR_SMRAM_SIZE_4096K_MASK 0x00000020\r | |
| 75 | #define PEI_MR_SMRAM_SIZE_8192K_MASK 0x00000040\r | |
| 76 | \r | |
| 77 | #define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001\r | |
| 78 | #define PEI_MR_SMRAM_HSEG_128K_CACHE 0x80020001\r | |
| 79 | #define PEI_MR_SMRAM_HSEG_128K_NOCACHE 0x00020001\r | |
| 80 | #define PEI_MR_SMRAM_TSEG_128K_CACHE 0x80040001\r | |
| 81 | #define PEI_MR_SMRAM_TSEG_128K_NOCACHE 0x00040001\r | |
| 82 | #define PEI_MR_SMRAM_TSEG_256K_CACHE 0x80040002\r | |
| 83 | #define PEI_MR_SMRAM_TSEG_256K_NOCACHE 0x00040002\r | |
| 84 | #define PEI_MR_SMRAM_TSEG_512K_CACHE 0x80040004\r | |
| 85 | #define PEI_MR_SMRAM_TSEG_512K_NOCACHE 0x00040004\r | |
| 86 | #define PEI_MR_SMRAM_TSEG_1024K_CACHE 0x80040008\r | |
| 87 | #define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008\r | |
| 88 | \r | |
| 89 | //\r | |
| 90 | // Graphics Memory Range\r | |
| 91 | //\r | |
| 92 | #define PEI_MEMORY_RANGE_GRAPHICS_MEMORY UINT32\r | |
| 93 | #define PEI_MR_GRAPHICS_MEMORY_ALL 0xFFFFFFFF\r | |
| 94 | #define PEI_MR_GRAPHICS_MEMORY_NONE 0x00000000\r | |
| 95 | #define PEI_MR_GRAPHICS_MEMORY_CACHEABLE 0x80000000\r | |
| 96 | //\r | |
| 97 | // If adding additional entries, Graphics Memory Size\r | |
| 98 | // is a multiple of 512KB.\r | |
| 99 | //\r | |
| 100 | #define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK 0x0000FFFF\r | |
| 101 | #define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001\r | |
| 102 | #define PEI_MR_GRAPHICS_MEMORY_512K_CACHE 0x80000001\r | |
| 103 | #define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE 0x00000002\r | |
| 104 | #define PEI_MR_GRAPHICS_MEMORY_1M_CACHE 0x80000002\r | |
| 105 | #define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE 0x00000008\r | |
| 106 | #define PEI_MR_GRAPHICS_MEMORY_4M_CACHE 0x80000008\r | |
| 107 | #define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE 0x00000010\r | |
| 108 | #define PEI_MR_GRAPHICS_MEMORY_8M_CACHE 0x80000010\r | |
| 109 | #define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE 0x00000020\r | |
| 110 | #define PEI_MR_GRAPHICS_MEMORY_16M_CACHE 0x80000020\r | |
| 111 | #define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE 0x00000040\r | |
| 112 | #define PEI_MR_GRAPHICS_MEMORY_32M_CACHE 0x80000040\r | |
| 113 | #define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE 0x00000060\r | |
| 114 | #define PEI_MR_GRAPHICS_MEMORY_48M_CACHE 0x80000060\r | |
| 115 | #define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE 0x00000080\r | |
| 116 | #define PEI_MR_GRAPHICS_MEMORY_64M_CACHE 0x80000080\r | |
| 117 | #define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100\r | |
| 118 | #define PEI_MR_GRAPHICS_MEMORY_128M_CACHE 0x80000100\r | |
| 119 | #define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200\r | |
| 120 | #define PEI_MR_GRAPHICS_MEMORY_256M_CACHE 0x80000200\r | |
| 121 | //\r | |
| 122 | // Pci Memory Hole\r | |
| 123 | //\r | |
| 124 | #define PEI_MEMORY_RANGE_PCI_MEMORY UINT32\r | |
| 125 | #define PEI_MR_PCI_MEMORY_SIZE_512M_MASK 0x00000001\r | |
| 126 | \r | |
| 127 | typedef\r | |
| 128 | EFI_STATUS\r | |
| 129 | (EFIAPI *PEI_CHOOSE_RANGES) (\r | |
| 130 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 131 | IN PEI_PLATFORM_MEMORY_RANGE_PPI * This,\r | |
| 132 | IN OUT PEI_MEMORY_RANGE_OPTION_ROM * OptionRomMask,\r | |
| 133 | IN OUT PEI_MEMORY_RANGE_SMRAM * SmramMask,\r | |
| 134 | IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY * GraphicsMemoryMask,\r | |
| 135 | IN OUT PEI_MEMORY_RANGE_PCI_MEMORY * PciMemoryMask\r | |
| 136 | );\r | |
| 137 | \r | |
| 138 | struct _PEI_PLATFORM_MEMORY_RANGE_PPI {\r | |
| 139 | PEI_CHOOSE_RANGES ChooseRanges;\r | |
| 140 | };\r | |
| 141 | \r | |
| 142 | extern EFI_GUID gPeiPlatformMemoryRangePpiGuid;\r | |
| 143 | \r | |
| 144 | #endif\r |