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1 | /**\r |
2 | \r | |
3 | Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved\r | |
4 | \r | |
7ede8060 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
3cbfba02 DW |
6 | \r |
7 | \r | |
8 | \r | |
9 | @file\r | |
10 | PchRegs.h\r | |
11 | \r | |
12 | @brief\r | |
13 | Register names for VLV SC.\r | |
14 | \r | |
15 | Conventions:\r | |
16 | \r | |
17 | - Prefixes:\r | |
18 | Definitions beginning with "R_" are registers\r | |
19 | Definitions beginning with "B_" are bits within registers\r | |
20 | Definitions beginning with "V_" are meaningful values of bits within the registers\r | |
21 | Definitions beginning with "S_" are register sizes\r | |
22 | Definitions beginning with "N_" are the bit position\r | |
23 | - In general, PCH registers are denoted by "_PCH_" in register names\r | |
24 | - Registers / bits that are different between PCH generations are denoted by\r | |
25 | "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r | |
26 | - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r | |
27 | at the end of the register/bit names\r | |
28 | - Registers / bits of new devices introduced in a PCH generation will be just named\r | |
29 | as "_PCH_" without <generation_name> inserted.\r | |
30 | \r | |
31 | **/\r | |
32 | #ifndef _PCH_REGS_H_\r | |
33 | #define _PCH_REGS_H_\r | |
34 | \r | |
35 | ///\r | |
36 | /// Bit Definitions. BUGBUG: drive these definitions to code base. Should not need\r | |
37 | /// to be part of chipset modules\r | |
38 | ///\r | |
39 | #ifndef BIT0\r | |
40 | #define BIT0 0x0001\r | |
41 | #define BIT1 0x0002\r | |
42 | #define BIT2 0x0004\r | |
43 | #define BIT3 0x0008\r | |
44 | #define BIT4 0x0010\r | |
45 | #define BIT5 0x0020\r | |
46 | #define BIT6 0x0040\r | |
47 | #define BIT7 0x0080\r | |
48 | #define BIT8 0x0100\r | |
49 | #define BIT9 0x0200\r | |
50 | #define BIT10 0x0400\r | |
51 | #define BIT11 0x0800\r | |
52 | #define BIT12 0x1000\r | |
53 | #define BIT13 0x2000\r | |
54 | #define BIT14 0x4000\r | |
55 | #define BIT15 0x8000\r | |
56 | #define BIT16 0x00010000\r | |
57 | #define BIT17 0x00020000\r | |
58 | #define BIT18 0x00040000\r | |
59 | #define BIT19 0x00080000\r | |
60 | #define BIT20 0x00100000\r | |
61 | #define BIT21 0x00200000\r | |
62 | #define BIT22 0x00400000\r | |
63 | #define BIT23 0x00800000\r | |
64 | #define BIT24 0x01000000\r | |
65 | #define BIT25 0x02000000\r | |
66 | #define BIT26 0x04000000\r | |
67 | #define BIT27 0x08000000\r | |
68 | #define BIT28 0x10000000\r | |
69 | #define BIT29 0x20000000\r | |
70 | #define BIT30 0x40000000\r | |
71 | #define BIT31 0x80000000\r | |
72 | #define BIT32 0x100000000\r | |
73 | #define BIT33 0x200000000\r | |
74 | #define BIT34 0x400000000\r | |
75 | #define BIT35 0x800000000\r | |
76 | #define BIT36 0x1000000000\r | |
77 | #define BIT37 0x2000000000\r | |
78 | #define BIT38 0x4000000000\r | |
79 | #define BIT39 0x8000000000\r | |
80 | #define BIT40 0x10000000000\r | |
81 | #define BIT41 0x20000000000\r | |
82 | #define BIT42 0x40000000000\r | |
83 | #define BIT43 0x80000000000\r | |
84 | #define BIT44 0x100000000000\r | |
85 | #define BIT45 0x200000000000\r | |
86 | #define BIT46 0x400000000000\r | |
87 | #define BIT47 0x800000000000\r | |
88 | #define BIT48 0x1000000000000\r | |
89 | #define BIT49 0x2000000000000\r | |
90 | #define BIT50 0x4000000000000\r | |
91 | #define BIT51 0x8000000000000\r | |
92 | #define BIT52 0x10000000000000\r | |
93 | #define BIT53 0x20000000000000\r | |
94 | #define BIT54 0x40000000000000\r | |
95 | #define BIT55 0x80000000000000\r | |
96 | #define BIT56 0x100000000000000\r | |
97 | #define BIT57 0x200000000000000\r | |
98 | #define BIT58 0x400000000000000\r | |
99 | #define BIT59 0x800000000000000\r | |
100 | #define BIT60 0x1000000000000000\r | |
101 | #define BIT61 0x2000000000000000\r | |
102 | #define BIT62 0x4000000000000000\r | |
103 | #define BIT63 0x8000000000000000\r | |
104 | #endif\r | |
105 | ///\r | |
106 | /// The default PCH PCI bus number\r | |
107 | ///\r | |
108 | #define DEFAULT_PCI_BUS_NUMBER_PCH 0\r | |
109 | \r | |
110 | ///\r | |
111 | /// Default Vendor ID and Subsystem ID\r | |
112 | ///\r | |
113 | #define V_PCH_INTEL_VENDOR_ID 0x8086\r | |
114 | #define V_PCH_DEFAULT_SID 0x7270\r | |
115 | #define V_PCH_DEFAULT_SVID_SID (V_PCH_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID << 16))\r | |
116 | \r | |
117 | ///\r | |
118 | /// Include device register definitions\r | |
119 | ///\r | |
120 | #include "PchRegs/PchRegsHda.h"\r | |
121 | #include "PchRegs/PchRegsLpss.h"\r | |
122 | #include "PchRegs/PchRegsPcie.h"\r | |
123 | #include "PchRegs/PchRegsPcu.h"\r | |
124 | #include "PchRegs/PchRegsRcrb.h"\r | |
125 | #include "PchRegs/PchRegsSata.h"\r | |
126 | #include "PchRegs/PchRegsScc.h"\r | |
127 | #include "PchRegs/PchRegsSmbus.h"\r | |
128 | #include "PchRegs/PchRegsSpi.h"\r | |
129 | #include "PchRegs/PchRegsUsb.h"\r | |
130 | //#include "PchRegs/PchRegsLpe.h"\r | |
131 | \r | |
132 | ///\r | |
133 | /// Device IDS that are PCH Server specific\r | |
134 | ///\r | |
135 | #define IS_PCH_DEVICE_ID(DeviceId) \\r | |
136 | ( \\r | |
137 | (DeviceId == V_PCH_LPC_DEVICE_ID_0) || \\r | |
138 | (DeviceId == V_PCH_LPC_DEVICE_ID_1) || \\r | |
139 | (DeviceId == V_PCH_LPC_DEVICE_ID_2) || \\r | |
140 | (DeviceId == V_PCH_LPC_DEVICE_ID_3) \\r | |
141 | )\r | |
142 | \r | |
143 | #define IS_PCH_VLV_LPC_DEVICE_ID(DeviceId) \\r | |
144 | ( \\r | |
145 | IS_PCH_DEVICE_ID (DeviceId) \\r | |
146 | )\r | |
147 | \r | |
148 | #define IS_PCH_VLV_SATA_DEVICE_ID(DeviceId) \\r | |
149 | ( \\r | |
150 | IS_PCH_VLV_SATA_AHCI_DEVICE_ID (DeviceId) || \\r | |
151 | IS_PCH_VLV_SATA_MODE_DEVICE_ID (DeviceId) || \\r | |
152 | IS_PCH_VLV_SATA_RAID_DEVICE_ID (DeviceId) \\r | |
153 | )\r | |
154 | \r | |
155 | #define IS_PCH_VLV_SATA_AHCI_DEVICE_ID(DeviceId) \\r | |
156 | ( \\r | |
157 | (DeviceId == V_PCH_SATA_DEVICE_ID_D_AHCI) || \\r | |
158 | (DeviceId == V_PCH_SATA_DEVICE_ID_M_AHCI) \\r | |
159 | )\r | |
160 | \r | |
161 | #define IS_PCH_VLV_SATA_RAID_DEVICE_ID(DeviceId) \\r | |
162 | ( \\r | |
163 | (DeviceId == V_PCH_SATA_DEVICE_ID_D_RAID) || \\r | |
164 | (DeviceId == V_PCH_SATA_DEVICE_ID_M_RAID) \\r | |
165 | )\r | |
166 | \r | |
167 | #define IS_PCH_VLV_SATA_MODE_DEVICE_ID(DeviceId) \\r | |
168 | ( \\r | |
169 | (DeviceId == V_PCH_SATA_DEVICE_ID_D_IDE) || \\r | |
170 | (DeviceId == V_PCH_SATA_DEVICE_ID_M_IDE) \\r | |
171 | )\r | |
172 | #define IS_PCH_VLV_USB_DEVICE_ID(DeviceId) \\r | |
173 | ( \\r | |
174 | (DeviceId == V_PCH_USB_DEVICE_ID_0) || \\r | |
175 | (DeviceId == V_PCH_USB_DEVICE_ID_1) \\r | |
176 | )\r | |
177 | #define IS_PCH_VLV_PCIE_DEVICE_ID(DeviceId) \\r | |
178 | ( \\r | |
179 | (DeviceId == V_PCH_PCIE_DEVICE_ID_0) || \\r | |
180 | (DeviceId == V_PCH_PCIE_DEVICE_ID_1) || \\r | |
181 | (DeviceId == V_PCH_PCIE_DEVICE_ID_2) || \\r | |
182 | (DeviceId == V_PCH_PCIE_DEVICE_ID_3) || \\r | |
183 | (DeviceId == V_PCH_PCIE_DEVICE_ID_4) || \\r | |
184 | (DeviceId == V_PCH_PCIE_DEVICE_ID_5) || \\r | |
185 | (DeviceId == V_PCH_PCIE_DEVICE_ID_6) || \\r | |
186 | (DeviceId == V_PCH_PCIE_DEVICE_ID_7) \\r | |
187 | )\r | |
188 | \r | |
189 | ///\r | |
190 | /// Any device ID that is Valleyview SC\r | |
191 | ///\r | |
192 | #define IS_PCH_VLV_DEVICE_ID(DeviceId) \\r | |
193 | ( \\r | |
194 | IS_PCH_VLV_LPC_DEVICE_ID (DeviceId) || \\r | |
195 | IS_PCH_VLV_SATA_DEVICE_ID (DeviceId) || \\r | |
196 | IS_PCH_VLV_USB_DEVICE_ID (DeviceId) || \\r | |
197 | IS_PCH_VLV_PCIE_DEVICE_ID (DeviceId) || \\r | |
198 | (DeviceId) == V_PCH_SMBUS_DEVICE_ID || \\r | |
199 | (DeviceId) == V_PCH_HDA_DEVICE_ID_0 || \\r | |
200 | (DeviceId) == V_PCH_HDA_DEVICE_ID_1 \\r | |
201 | )\r | |
202 | \r | |
203 | #define IS_SUPPORTED_DEVICE_ID(DeviceId) IS_PCH_VLV_DEVICE_ID (DeviceId)\r | |
204 | \r | |
205 | #endif\r |