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3cbfba02 DW |
1 | ## @file Vlv2DeviceRefCodePkg.dec\r |
2 | #\r | |
f4e7aa05 | 3 | # Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved\r |
3cbfba02 DW |
4 | #\r |
5 | # This program and the accompanying materials are licensed and made available under\r | |
6 | # the terms and conditions of the BSD License that accompanies this distribution.\r | |
7 | # The full text of the license may be found at\r | |
8 | # http://opensource.org/licenses/bsd-license.php.\r | |
9 | #\r | |
10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | #\r | |
13 | #\r | |
14 | ##\r | |
15 | \r | |
16 | [Defines]\r | |
17 | DEC_SPECIFICATION = 0x00010005\r | |
18 | PACKAGE_NAME = Vlv2DeviceRefCodePkg\r | |
19 | PACKAGE_GUID = E4FA0DCA-91A3-4957-9344-C10BAA0BFE5F\r | |
20 | PACKAGE_VERSION = 0.1\r | |
21 | \r | |
22 | [Ppis]\r | |
23 | gVlvPolicyPpiGuid = { 0x7D84B2C2, 0x22A1, 0x4372, {0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3}}\r | |
24 | gVlvMmioPolicyPpiGuid = { 0xE767BF7F, 0x4DB6, 0x5B34, {0x10, 0x11, 0x4F, 0xBE, 0x4C, 0xA7, 0xAF, 0xD2}}\r | |
25 | gPeiSmbusPolicyPpiGuid = { 0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c}}\r | |
26 | gSeCfTPMPpiGuid = { 0x10e26df1, 0x8775, 0x4ee1, {0xb5, 0x0a, 0x3a, 0xe8, 0x28, 0x93, 0x70, 0x3a}}\r | |
27 | gPchUsbPolicyPpiGuid = { 0xc02b0573, 0x2b4e, 0x4a31, {0xa3, 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c}}\r | |
28 | gPchInitPpiGuid = { 0x09ea894a, 0xbe0d, 0x4230, {0xa0, 0x03, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x95}}\r | |
29 | gPchPlatformPolicyPpiGuid = { 0x15344673, 0xD365, 0x4BE2, {0x85, 0x13, 0x14, 0x97, 0xCC, 0x07, 0x61, 0x1D}}\r | |
30 | gPeiSpiPpiGuid = { 0xA38C6898, 0x2B5C, 0x4FF6, {0x93, 0x26, 0x2E, 0x63, 0x21, 0x2E, 0x56, 0xC2}}\r | |
31 | gVlvPeiInitPpiGuid = { 0x09ea8911, 0xbe0d, 0x4230, {0xa0, 0x03, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x11}}\r | |
32 | gSeCUmaPpiGuid = { 0xcbd86677, 0x362f, 0x4c04, {0x94, 0x59, 0xa7, 0x41, 0x32, 0x6e, 0x05, 0xcf}}\r | |
33 | gPeiSeCPlatformPolicyPpiGuid = { 0x7ae3ceb7, 0x2ee2, 0x48fa, {0xaa, 0x49, 0x35, 0x10, 0xbc, 0x83, 0xca, 0xbf}}\r | |
34 | gPeiHeciPpiGuid = { 0xEE0EA811, 0xFBD9, 0x4777, {0xB9, 0x5A, 0xBA, 0x4F, 0x71, 0x10, 0x1F, 0x74}}\r | |
35 | gPeiSdhcPpiGuid = { 0xf4ef9d7a, 0x98c5, 0x4c1a, {0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0x0c}}\r | |
36 | gPeiBlockIoPpiGuid = { 0xbc5fa650, 0xedbb, 0x4d0d, {0xb3, 0xa3, 0xd9, 0x89, 0x07, 0xf8, 0x47, 0xdf}}\r | |
37 | gSeCfTPMPolicyPpiGuid = { 0x4fd1ba49, 0x8f90, 0x471a, {0xa2, 0xc9, 0x17, 0x3c, 0x7a, 0x73, 0x2f, 0xd0}}\r | |
38 | gEfiPeiReadOnlyVariable2PpiGuid = { 0x2ab86ef5, 0xecb5, 0x4134, {0xb5, 0x56, 0x38, 0x54, 0xca, 0x1f, 0xe1, 0xb4}}\r | |
39 | gPchPeiInitPpiGuid = { 0xACB93B08, 0x5CDC, 0x4A8F, {0x93, 0xD4, 0x6, 0xE3, 0x42, 0xDF, 0x18, 0x2E}}\r | |
f4e7aa05 TH |
40 | gPttPassThruPpiGuid = { 0xc5068bac, 0xa7dc, 0x42f1, {0xae, 0x80, 0xca, 0xa2, 0x4b, 0xb4, 0x90, 0x4b}}\r |
41 | \r | |
3cbfba02 DW |
42 | [Protocols]\r |
43 | gEfiGlobalNvsAreaProtocolGuid = { 0x074e1e48, 0x8132, 0x47a1, {0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc}}\r | |
44 | gPpmPlatformPolicyProtocolGuid = { 0xddabfeac, 0xef63, 0x452c, {0x8f, 0x39, 0xed, 0x7f, 0xae, 0xd8, 0x26, 0x5e}}\r | |
45 | gEfiSpiProtocolGuid = { 0x1156efc6, 0xea32, 0x4396, {0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13}}\r | |
46 | gMemInfoProtocolGuid = { 0x6f20f7c8, 0xe5ef, 0x4f21, {0x8d, 0x19, 0xed, 0xc5, 0xf0, 0xc4, 0x96, 0xae}}\r | |
47 | gEfiSdHostIoProtocolGuid = { 0xb63f8ec7, 0xa9c9, 0x4472, {0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51}}\r | |
48 | gEfiSpiProtocolGuid = { 0x1156efc6, 0xea32, 0x4396, {0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13}}\r | |
49 | gEfiSmmSpiProtocolGuid = { 0xD9072C35, 0xEB8F, 0x43AD, {0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85}}\r | |
50 | gEfiSmmIchnDispatchExProtocolGuid = { 0x3920405B, 0xC897, 0x44DA, {0x88, 0xF3, 0x4C, 0x49, 0x8A, 0x6F, 0xF7, 0x36}}\r | |
51 | gEfiPchS3SupportProtocolGuid = { 0xE287D20B, 0xD897, 0x4E1E, {0xA5, 0xD9, 0x97, 0x77, 0x63, 0x93, 0x6A, 0x04}}\r | |
52 | gPchResetProtocolGuid = { 0xDB63592C, 0xB8CC, 0x44C8, {0x91, 0x8C, 0x51, 0xF5, 0x34, 0x59, 0x8A, 0x5A}}\r | |
53 | gPchResetCallbackProtocolGuid = { 0x3A3300AB, 0xC929, 0x487D, {0xAB, 0x34, 0x15, 0x9B, 0xC1, 0x35, 0x62, 0xC0}}\r | |
54 | gDxePchPlatformPolicyProtocolGuid = { 0x4b0165a9, 0x61d6, 0x4e23, {0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5}}\r | |
55 | gEfiPchInfoProtocolGuid = { 0xD31F0400, 0x7D16, 0x4316, {0xBF, 0x88, 0x60, 0x65, 0x88, 0x3B, 0x40, 0x2B}}\r | |
56 | gEfiPchExtendedResetProtocolGuid = { 0xF0BBFCA0, 0x684E, 0x48B3, {0xBA, 0xE2, 0x6C, 0x84, 0xB8, 0x9E, 0x53, 0x39}}\r | |
57 | gEfiActiveBiosProtocolGuid = { 0xEBBE2D1B, 0x1647, 0x4BDA, {0xAB, 0x9A, 0x78, 0x63, 0xE3, 0x96, 0xD4, 0x1A}}\r | |
58 | gDxeIchPlatformPolicyProtocolGuid = { 0xf617b358, 0x12cf, 0x414a, {0xa0, 0x69, 0x60, 0x67, 0x7b, 0xda, 0x13, 0xb3}}\r | |
59 | gEfiIchInfoProtocolGuid = { 0xd31f0400, 0x7d16, 0x4316, {0xbf, 0x88, 0x60, 0x65, 0x88, 0x3b, 0x40, 0x2b}}\r | |
60 | gEfiSmmIoTrapDispatchProtocolGuid = { 0x58dc368d, 0x7bfa, 0x4e77, {0xab, 0xbc, 0x0e, 0x29, 0x41, 0x8d, 0xf9, 0x30}}\r | |
61 | gEfiSmmSmbusProtocolGuid = { 0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}}\r | |
62 | gDxeVlvPlatformPolicyGuid = { 0x5bab88ba, 0xe0e2, 0x4674, {0xb6, 0xad, 0xb8, 0x12, 0xf6, 0x88, 0x1c, 0xd6}}\r | |
63 | gIgdOpRegionProtocolGuid = { 0xcdc5dddf, 0xe79d, 0x41ec, {0xa9, 0xb0, 0x65, 0x65, 0x49, 0x0d, 0xb9, 0xd3}}\r | |
64 | gEfiHeciProtocolGuid = { 0xcfb33810, 0x6e87, 0x4284, {0xb2, 0x03, 0xa6, 0x6a, 0xbe, 0x07, 0xf6, 0xe8}}\r | |
65 | gPlatformSeCHookProtocolGuid = { 0xbc52476e, 0xf67e, 0x4301, {0xb2, 0x62, 0x36, 0x9c, 0x48, 0x78, 0xaa, 0xc2}}\r | |
66 | gEfiSeCRcInfoProtocolGuid = { 0x11fbfdfb, 0x10d2, 0x43e6, {0xb5, 0xb1, 0xb4, 0x38, 0x6e, 0xdc, 0xcb, 0x9a}}\r | |
67 | gEfiTdtProtocolGuid = { 0x0bf70067, 0xd53b, 0x42df, {0xb7, 0x70, 0xe9, 0x2c, 0x91, 0xc6, 0x14, 0x11}}\r | |
68 | gDxePlatformSeCPolicyGuid = { 0xf8bff014, 0x18fb, 0x4ef9, {0xb1, 0x0c, 0xae, 0x22, 0x73, 0x8d, 0xbe, 0xed}}\r | |
69 | gLpssDummyProtocolGuid = { 0xaf4cc162, 0xd41c, 0x455a, {0xab, 0x45, 0x6d, 0xbc, 0xc1, 0xcd, 0x32, 0xf3}}\r | |
70 | gEfiEmmcCardInfoProtocolGuid = { 0x1ebe5ab9, 0x2129, 0x49e7, {0x84, 0xd7, 0xee, 0xb9, 0xfc, 0xe5, 0xde, 0xdd}}\r | |
71 | gEfiTdtOperationProtocolGuid = {0xfd301ba4, 0x5e62, 0x4679,{ 0xa0, 0x6f, 0xe0, 0x9a, 0xab, 0xdd, 0x2a, 0x91}}\r | |
72 | gEfiConfigFileNameGuid = { 0x98B8D59B, 0xE8BA, 0x48EE, { 0x98, 0xDD, 0xC2, 0x95, 0x39, 0x2F, 0x1E, 0xDB }}\r | |
73 | gEfiDFUResultGuid = { 0x14a7c46f, 0xbc02, 0x4047, { 0x9f, 0x18, 0xa5, 0xd7, 0x25, 0xd8, 0xbd, 0x19 }}\r | |
f4e7aa05 TH |
74 | gPttPassThruProtocolGuid = { 0x73e2576, 0xf6c1, 0x4b91, { 0x92, 0xa9, 0xd4, 0x67, 0x5d, 0xda, 0x34, 0xb1 } }\r |
75 | \r | |
3cbfba02 DW |
76 | [Guids]\r |
77 | gEfiCPTokenSpaceGuid = { 0x918211ce, 0xa1d2, 0x43a0, {0xa0, 0x4e, 0x75, 0xb5, 0xbf, 0x44, 0x50, 0x0E}}\r | |
78 | gEfiSmbusArpMapGuid = { 0x707BE83E, 0x0BF6, 0x40A5, {0xBE, 0x64, 0x34, 0xC0, 0x3A, 0xA0, 0xB8, 0xE2}}\r | |
79 | gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, {0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31}}\r | |
80 | gEfiVLVTokenSpaceGuid = { 0xca452c68, 0xdf0c, 0x45c9, {0x82, 0xfb, 0xea, 0xe4, 0x2b, 0x31, 0x29, 0x46}}\r | |
81 | gSataControllerDriverGuid = { 0xbb929da9, 0x68f7, 0x4035, {0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55}}\r | |
82 | gDxePchPolicyUpdateProtocolGuid = { 0x1a819e49, 0xd8ee, 0x48cb, {0x9a, 0x9c, 0x0a, 0xa0, 0xd2, 0x81, 0x0a, 0x38}}\r | |
83 | gPowerManagementAcpiTableStorageGuid = { 0x161be597, 0xe9c5, 0x49db, {0xae, 0x50, 0xc4, 0x62, 0xab, 0x54, 0xee, 0xda}}\r | |
84 | gEfiSetupVariableGuid = { 0xec87d643, 0xeba4, 0x4bb5, {0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9}}\r | |
85 | gBmpImageGuid = { 0x878AC2CC, 0x5343, 0x46F2, {0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA}}\r | |
86 | gPchInitVariableGuid = { 0xe6c2f70a, 0xb604, 0x4877, {0x85, 0xba, 0xde, 0xec, 0x89, 0xe1, 0x17, 0xeb}}\r | |
87 | gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, {0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31}}\r | |
88 | gVlvRefCodePkgTokenSpaceGuid = { 0x85768E4A, 0x6CDC, 0x444E, {0x93, 0xDF, 0x93, 0x66, 0x85, 0xB5, 0xDF, 0xCC}}\r | |
89 | gSeCPlatformReadyToBootGuid = { 0x03fdf171, 0x1d67, 0x4ace, {0xa9, 0x04, 0x3e, 0x36, 0xd3, 0x38, 0xfa, 0x74}}\r | |
90 | gAmtReadyToBootGuid = { 0x40b09b5a, 0xf0ef, 0x4627, {0x93, 0xd5, 0x27, 0xf0, 0x4b, 0x75, 0x4d, 0x05}}\r | |
91 | #\r | |
92 | # According to UEFI 2.3.1 Errata C, 3.2 Globally Defined Variables.\r | |
93 | # To prevent name collisions with possible future globally defined variables,\r | |
94 | # other internal firmware data variables that are not defined in Table.10 must be saved with a unique VendorGuid other than EFI_GLOBAL_VARIABLE.\r | |
95 | #\r | |
96 | gEfiVlv2VariableGuid = { 0x10ba6bbe, 0xa97e, 0x41c3, {0x9a, 0x07, 0x60, 0x7a, 0xd9, 0xbd, 0x60, 0xe5}}\r | |
97 | \r | |
98 | [Includes.common]\r | |
99 | .\r | |
100 | ValleyView2Soc/NorthCluster/Include\r | |
101 | ValleyView2Soc/SouthCluster/Include\r | |
102 | ValleyView2Soc/CPU/Include\r | |
103 | Include\r | |
104 | \r | |
105 | [PcdsFixedAtBuild]\r | |
106 | gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040|UINT16|0x10000207\r | |
107 | \r | |
108 | [PcdsDynamic, PcdsDynamicEx]\r | |
109 | gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040|UINT16|0x10000207\r | |
110 | gEfiVLVTokenSpaceGuid.PcdEmmcManufacturerId|0|UINT8|0x10000208\r | |
111 | gEfiVLVTokenSpaceGuid.PcdProductSerialNumber|0|UINT32|0x10000209\r | |
112 | gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable|TRUE|BOOLEAN|0x1000020A\r | |
113 | gEfiVLVTokenSpaceGuid.PcdFTPMErrorOccur|FALSE|BOOLEAN|0x1000020B\r | |
114 | gEfiVLVTokenSpaceGuid.PcdFTPMErrorSkip|FALSE|BOOLEAN|0x1000020C\r | |
115 | gEfiVLVTokenSpaceGuid.PcdFTPMCommand|0|UINT32|0x1000020D\r | |
116 | gEfiVLVTokenSpaceGuid.PcdFTPMResponse|0|UINT32|0x1000020E\r | |
117 | gEfiVLVTokenSpaceGuid.PcdFTPMNotRespond|FALSE|BOOLEAN|0x1000020F\r | |
118 | gEfiVLVTokenSpaceGuid.PcdFTPMStatus|0|UINT32|0x10000210\r | |
581c6c62 SL |
119 | gEfiVLVTokenSpaceGuid.PcdCpuLockBoxDataAddress|0x0|UINT64|0x10000211\r |
120 | gEfiVLVTokenSpaceGuid.PcdCpuSmramCpuDataAddress|0x0|UINT64|0x10000212\r | |
121 | gEfiVLVTokenSpaceGuid.PcdCpuLockBoxSize|0x0|UINT64|0x10000213\r | |
3cbfba02 DW |
122 | \r |
123 | [PcdsFeatureFlag]\r | |
124 | gVlvRefCodePkgTokenSpaceGuid.PcdCeAtaSupport|FALSE|BOOLEAN|0x12\r | |
125 | gVlvRefCodePkgTokenSpaceGuid.PcdMmcSdMultiBlockSupport|TRUE|BOOLEAN|0x13\r | |
126 | \r | |
9d6cdba3 DW |
127 | [PcdsPatchableInModule]\r |
128 | \r | |
129 | ## Memory Down or DIMM slot.<BR><BR>\r | |
130 | # 0 - DIMM<BR>\r | |
131 | # 1 - Memory Down<BR>\r | |
132 | # @Prompt Enable Memory Down\r | |
133 | # @ValidList 0x80000001 | 0, 1\r | |
134 | gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|1|UINT8|0x20000000\r | |
135 | \r | |
136 | ## Memory Parameter Patchable.<BR><BR>\r | |
137 | # 0 - Fixed Parameter for MinnowBoard Max<BR>\r | |
138 | # 1 - Patchable Parameter for Customization<BR>\r | |
139 | # @Prompt Memory Parameter Patchable.\r | |
140 | # @ValidList 0x80000001 | 0, 1 \r | |
141 | gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|FALSE|BOOLEAN|0x20000010\r | |
142 | \r | |
143 | ## The speed of DRAM.<BR><BR>\r | |
144 | # 0 - 800 MHz<BR>\r | |
145 | # 1 - 1066 MHz<BR>\r | |
146 | # 2 - 1333 MHz<BR>\r | |
147 | # 3 - 1600 MHz<BR>\r | |
148 | # @Prompt DRAM Speed\r | |
149 | # @ValidList 0x80000001 | 0, 1, 2, 3\r | |
150 | gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|1|UINT8|0x20000001\r | |
151 | \r | |
152 | ## DRAM Type.<BR><BR>\r | |
153 | # 0 - DDR3<BR>\r | |
154 | # 1 - DDR3L<BR>\r | |
155 | # 2 - DDR3U<BR>\r | |
156 | # 3 - DDR3All<BR>\r | |
157 | # 4 - LPDDR2<BR>\r | |
158 | # 5 - LPDDR3<BR>\r | |
159 | # 6 - DDR4<BR>\r | |
160 | # @Prompt DRAM Type\r | |
161 | # @ValidList 0x80000001 | 0, 1, 2, 3, 4, 5, 6\r | |
162 | gVlvRefCodePkgTokenSpaceGuid.PcdDramType|1|UINT8|0x20000002\r | |
163 | \r | |
164 | ## Please populate DIMM slot 0 if only one DIMM is supported.<BR><BR>\r | |
165 | # 0 - Disable<BR>\r | |
166 | # 1 - Enable<BR>\r | |
167 | # @Prompt DIMM 0 Enable \r | |
168 | # @ValidList 0x80000001 | 0, 1\r | |
169 | gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|1|UINT8|0x20000003\r | |
170 | \r | |
171 | ## DIMM 1 has to be identical to DIMM 0.<BR><BR>\r | |
172 | # 0 - Disable<BR>\r | |
173 | # 1 - Enable<BR>\r | |
174 | # @Prompt DIMM 1 Enable Type\r | |
175 | # @ValidList 0x80000001 | 0, 1\r | |
176 | gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0|UINT8|0x20000004\r | |
177 | \r | |
178 | ## DRAM device data width.<BR><BR>\r | |
179 | # 0 - x8<BR>\r | |
180 | # 1 - x16<BR>\r | |
181 | # 2 - x32<BR>\r | |
182 | # @Prompt DIMM_DWIDTH\r | |
183 | # @ValidList 0x80000001 | 0, 1, 2\r | |
184 | gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|1|UINT8|0x20000005\r | |
185 | \r | |
186 | ## DRAM device data density.<BR><BR>\r | |
187 | # 0 - 1 Gbit<BR>\r | |
188 | # 1 - 2 Gbit<BR>\r | |
189 | # 2 - 4 Gbit<BR>\r | |
190 | # 3 - 8 Gbit<BR>\r | |
191 | # @Prompt DIMM_Density\r | |
192 | # @ValidList 0x80000001 | 0, 1, 2, 3\r | |
193 | gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|2|UINT8|0x20000006\r | |
194 | \r | |
195 | ## DRAM device data bus width.<BR><BR>\r | |
196 | # 0 - 8 bits<BR>\r | |
197 | # 1 - 16 bits<BR>\r | |
198 | # 2 - 32 bits<BR>\r | |
199 | # 3 - 64 bits<BR>\r | |
200 | # @Prompt DIMM_BusWidth\r | |
201 | # @ValidList 0x80000001 | 0, 1, 2, 3\r | |
202 | gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|3|UINT8|0x20000007\r | |
203 | \r | |
204 | ## Ranks Per DIMM or Sides Per DIMM.<BR><BR>\r | |
205 | # 0 - 1 Rank<BR>\r | |
206 | # 1 - 2 Ranks<BR>\r | |
207 | # @Prompt DIMM_Sides\r | |
208 | # @ValidList 0x80000001 | 0, 1\r | |
209 | gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0|UINT8|0x20000008\r | |
210 | \r | |
211 | ## tCL.<BR><BR>\r | |
212 | # @Prompt tCL\r | |
213 | gVlvRefCodePkgTokenSpaceGuid.PcdTcl|11|UINT8|0x20000009\r | |
214 | \r | |
215 | ## tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc.<BR><BR> \r | |
216 | # @Prompt tRP_tRCD \r | |
217 | gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|11|UINT8|0x2000000A\r | |
218 | \r | |
219 | ## tWR in DRAM clk.<BR><BR> \r | |
220 | # @Prompt tWR \r | |
221 | gVlvRefCodePkgTokenSpaceGuid.PcdTwr|12|UINT8|0x2000000B\r | |
222 | \r | |
223 | ## tWTR in DRAM clk.<BR><BR> \r | |
224 | # @Prompt tWTR \r | |
225 | gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|6|UINT8|0x2000000C\r | |
226 | \r | |
227 | ## tRRD in DRAM clk.<BR><BR> \r | |
228 | # @Prompt tRRD \r | |
229 | gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|6|UINT8|0x2000000D\r | |
230 | \r | |
231 | ## tRTP in DRAM clk.<BR><BR> \r | |
232 | # @Prompt tRTP \r | |
233 | gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|6|UINT8|0x2000000E\r | |
234 | \r | |
235 | ## tFAW in DRAM clk.<BR><BR> \r | |
236 | # @Prompt tFAW \r | |
237 | gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|32|UINT8|0x2000000F\r |