[mirror_edk2.git] / Vlv2TbltDevicePkg / FspSupport / Library / SecFspPlatformSecLibVlv2 / UartInit.c

/** @file\r
  This PEIM will parse the hoblist from fsp and report them into pei core.\r
  This file contains the main entrypoint of the PEIM.\r
\r
  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
#include <PiPei.h>\r
#include <Library/IoLib.h>\r
#include <Library/SerialPortLib.h>\r
\r
#define PCI_IDX        0xCF8\r
#define PCI_DAT        0xCFC\r
\r
#define PCI_LPC_BASE    (0x8000F800)\r
#define PCI_LPC_REG(x)  (PCI_LPC_BASE + (x))\r
\r
#define PMC_BASE_ADDRESS                  0xFED03000    // PMC Memory Base Address\r
#define R_PCH_LPC_PMC_BASE                        0x44  // PBASE, 32bit, 512 Bytes\r
#define B_PCH_LPC_PMC_BASE_EN                     BIT1  // Enable Bit\r
#define R_PCH_PMC_GEN_PMCON_1                     0x20  // General PM Configuration 1\r
#define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR           BIT14 // SUS Well Power Failure\r
#define B_PCH_PMC_GEN_PMCON_PWROK_FLR             BIT16 // PWROK Failure\r
\r
#define R_PCH_LPC_UART_CTRL                       0x80  // UART Control\r
#define B_PCH_LPC_UART_CTRL_COM1_EN               BIT0  // COM1 Enable\r
\r
#define ILB_BASE_ADDRESS                  0xFED08000    // ILB Memory Base Address\r
#define R_PCH_ILB_IRQE                            0x88  // IRQ Enable Control\r
\r
#define IO_BASE_ADDRESS                   0xFED0C000    // IO Memory Base Address\r
\r
#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3             BIT3  // UART IRQ3 Enable\r
#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ4             BIT4  // UART IRQ4 Enable\r
#define PCIEX_BASE_ADDRESS                        0xE0000000\r
#define PCI_EXPRESS_BASE_ADDRESS                  PCIEX_BASE_ADDRESS\r
#define PciD31F0RegBase                           PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)\r
#define SB_RCBA                                   0xfed1c000\r
\r
typedef enum {\r
  PchA0         = 0,\r
  PchA1         = 1,\r
  PchB0         = 2,\r
  PchB1         = 3,\r
  PchB2         = 4,\r
  PchB3         = 5,\r
  PchC0         = 6,\r
  PchSteppingMax\r
} PCH_STEPPING;\r
\r
#define MmPciAddress( Segment, Bus, Device, Function, Register ) \\r
  ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \\r
    (UINTN)(Bus << 20) + \\r
    (UINTN)(Device << 15) + \\r
    (UINTN)(Function << 12) + \\r
    (UINTN)(Register) \\r
  )\r
\r
#define DEFAULT_PCI_BUS_NUMBER_PCH  0\r
#define PCI_DEVICE_NUMBER_PCH_LPC                 31\r
#define PCI_FUNCTION_NUMBER_PCH_LPC               0\r
\r
#define R_PCH_LPC_RID_CC                          0x08  // Revision ID & Class Code\r
\r
#define V_PCH_LPC_RID_0                           0x01  // A0 Stepping (17 x 17)\r
#define V_PCH_LPC_RID_1                           0x02  // A0 Stepping (25 x 27)\r
#define V_PCH_LPC_RID_2                           0x03  // A1 Stepping (17 x 17)\r
#define V_PCH_LPC_RID_3                           0x04  // A1 Stepping (25 x 27)\r
#define V_PCH_LPC_RID_4                           0x05  // B0 Stepping (17 x 17)\r
#define V_PCH_LPC_RID_5                           0x06  // B0 Stepping (25 x 27)\r
#define V_PCH_LPC_RID_6                           0x07  // B1 Stepping (17 x 17)\r
#define V_PCH_LPC_RID_7                           0x08  // B1 Stepping (25 x 27)\r
#define V_PCH_LPC_RID_8                           0x09  // B2 Stepping (17 x 17)\r
#define V_PCH_LPC_RID_9                           0x0A  // B2 Stepping (25 x 27)\r
#define V_PCH_LPC_RID_A                           0x0B  // B3 Stepping (17 x 17)\r
#define V_PCH_LPC_RID_B                           0x0C  // B3 Stepping (25 x 27)\r
#define V_PCH_LPC_RID_C                           0x0D  // C0 Stepping (17 x 17)\r
#define V_PCH_LPC_RID_D                           0x0E  // C0 Stepping (25 x 27)\r
\r
/**\r
  Return Pch stepping type\r
\r
  @param[in] None\r
\r
  @retval PCH_STEPPING            Pch stepping type\r
\r
**/\r
PCH_STEPPING\r
EFIAPI\r
PchStepping (\r
  VOID\r
  )\r
{\r
  UINT8 RevId;\r
\r
  RevId = MmioRead8 (\r
          MmPciAddress (0,\r
            DEFAULT_PCI_BUS_NUMBER_PCH,\r
            PCI_DEVICE_NUMBER_PCH_LPC,\r
            PCI_FUNCTION_NUMBER_PCH_LPC,\r
            R_PCH_LPC_RID_CC)\r
          );\r
\r
  switch (RevId) {\r
    case V_PCH_LPC_RID_0:\r
    case V_PCH_LPC_RID_1:\r
      return PchA0;\r
      break;\r
\r
    case V_PCH_LPC_RID_2:\r
    case V_PCH_LPC_RID_3:\r
      return PchA1;\r
      break;\r
\r
    case V_PCH_LPC_RID_4:\r
    case V_PCH_LPC_RID_5:\r
      return PchB0;\r
      break;\r
\r
    case V_PCH_LPC_RID_6:\r
    case V_PCH_LPC_RID_7:\r
      return PchB1;\r
      break;\r
\r
    case V_PCH_LPC_RID_8:\r
    case V_PCH_LPC_RID_9:\r
      return PchB2;\r
      break;\r
\r
    case V_PCH_LPC_RID_A:\r
    case V_PCH_LPC_RID_B:\r
      return PchB3;\r
      break;\r
\r
    case V_PCH_LPC_RID_C:\r
    case V_PCH_LPC_RID_D:\r
      return PchC0;\r
      break;\r
\r
    default:\r
      return PchSteppingMax;\r
      break;\r
\r
  }\r
}\r
\r
/**\r
  Enable legacy decoding on ICH6\r
\r
 @param[in] none\r
\r
 @retval EFI_SUCCESS     Always returns success.\r
\r
**/\r
VOID\r
EnableInternalUart(\r
  VOID\r
  )\r
{\r
\r
  //\r
  // Program and enable PMC Base.\r
  //\r
  IoWrite32 (PCI_IDX,  PCI_LPC_REG(R_PCH_LPC_PMC_BASE));\r
  IoWrite32 (PCI_DAT,  (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));\r
\r
  //\r
  // Enable COM1 for debug message output.\r
  //\r
  MmioAndThenOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, (UINT32) (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR + B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);\r
\r
  //\r
  // Silicon Steppings\r
  //\r
  if (PchStepping()>= PchB0)\r
    MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ4);\r
  else\r
    MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);\r
  MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));\r
  MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L\r
  MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));\r
  MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L\r
  MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) B_PCH_LPC_UART_CTRL_COM1_EN);\r
\r
  SerialPortInitialize ();\r
  SerialPortWrite ((UINT8 *)"EnableInternalUart!\r\n", sizeof("EnableInternalUart!\r\n") - 1);\r
\r
  return  ;\r
}\r
Commit	Line	Data
3cbfba02 DW	1	/** @file\r
	2	This PEIM will parse the hoblist from fsp and report them into pei core.\r
	3	This file contains the main entrypoint of the PEIM.\r
	4	\r
	5	Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php.\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	\r
	17	#include <PiPei.h>\r
6ecc5d5c WD	18	#include <Library/IoLib.h>\r
6ecc5d5c WD	19	#include <Library/SerialPortLib.h>\r
3cbfba02 DW	20	\r
	21	#define PCI_IDX 0xCF8\r
	22	#define PCI_DAT 0xCFC\r
	23	\r
	24	#define PCI_LPC_BASE (0x8000F800)\r
	25	#define PCI_LPC_REG(x) (PCI_LPC_BASE + (x))\r
	26	\r
	27	#define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base Address\r
	28	#define R_PCH_LPC_PMC_BASE 0x44 // PBASE, 32bit, 512 Bytes\r
	29	#define B_PCH_LPC_PMC_BASE_EN BIT1 // Enable Bit\r
	30	#define R_PCH_PMC_GEN_PMCON_1 0x20 // General PM Configuration 1\r
	31	#define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR BIT14 // SUS Well Power Failure\r
	32	#define B_PCH_PMC_GEN_PMCON_PWROK_FLR BIT16 // PWROK Failure\r
	33	\r
	34	#define R_PCH_LPC_UART_CTRL 0x80 // UART Control\r
	35	#define B_PCH_LPC_UART_CTRL_COM1_EN BIT0 // COM1 Enable\r
	36	\r
	37	#define ILB_BASE_ADDRESS 0xFED08000 // ILB Memory Base Address\r
	38	#define R_PCH_ILB_IRQE 0x88 // IRQ Enable Control\r
	39	\r
	40	#define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address\r
	41	\r
	42	#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable\r
	43	#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ4 BIT4 // UART IRQ4 Enable\r
	44	#define PCIEX_BASE_ADDRESS 0xE0000000\r
	45	#define PCI_EXPRESS_BASE_ADDRESS PCIEX_BASE_ADDRESS\r
	46	#define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)\r
	47	#define SB_RCBA 0xfed1c000\r
	48	\r
	49	typedef enum {\r
	50	PchA0 = 0,\r
	51	PchA1 = 1,\r
	52	PchB0 = 2,\r
	53	PchB1 = 3,\r
	54	PchB2 = 4,\r
	55	PchB3 = 5,\r
	56	PchC0 = 6,\r
	57	PchSteppingMax\r
	58	} PCH_STEPPING;\r
	59	\r
	60	#define MmPciAddress( Segment, Bus, Device, Function, Register ) \\r
	61	( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \\r
	62	(UINTN)(Bus << 20) + \\r
	63	(UINTN)(Device << 15) + \\r
	64	(UINTN)(Function << 12) + \\r
	65	(UINTN)(Register) \\r
	66	)\r
	67	\r
	68	#define DEFAULT_PCI_BUS_NUMBER_PCH 0\r
	69	#define PCI_DEVICE_NUMBER_PCH_LPC 31\r
	70	#define PCI_FUNCTION_NUMBER_PCH_LPC 0\r
	71	\r
	72	#define R_PCH_LPC_RID_CC 0x08 // Revision ID & Class Code\r
	73	\r
	74	#define V_PCH_LPC_RID_0 0x01 // A0 Stepping (17 x 17)\r
	75	#define V_PCH_LPC_RID_1 0x02 // A0 Stepping (25 x 27)\r
	76	#define V_PCH_LPC_RID_2 0x03 // A1 Stepping (17 x 17)\r
	77	#define V_PCH_LPC_RID_3 0x04 // A1 Stepping (25 x 27)\r
	78	#define V_PCH_LPC_RID_4 0x05 // B0 Stepping (17 x 17)\r
	79	#define V_PCH_LPC_RID_5 0x06 // B0 Stepping (25 x 27)\r
	80	#define V_PCH_LPC_RID_6 0x07 // B1 Stepping (17 x 17)\r
	81	#define V_PCH_LPC_RID_7 0x08 // B1 Stepping (25 x 27)\r
	82	#define V_PCH_LPC_RID_8 0x09 // B2 Stepping (17 x 17)\r
	83	#define V_PCH_LPC_RID_9 0x0A // B2 Stepping (25 x 27)\r
84	#define V_PCH_LPC_RID_A 0x0B // B3 Stepping (17 x 17)\r
85	#define V_PCH_LPC_RID_B 0x0C // B3 Stepping (25 x 27)\r
86	#define V_PCH_LPC_RID_C 0x0D // C0 Stepping (17 x 17)\r
87	#define V_PCH_LPC_RID_D 0x0E // C0 Stepping (25 x 27)\r
88	\r
89	/**\r
90	Return Pch stepping type\r
91	\r
92	@param[in] None\r
93	\r
94	@retval PCH_STEPPING Pch stepping type\r
95	\r
96	**/\r
97	PCH_STEPPING\r
98	EFIAPI\r
99	PchStepping (\r
100	VOID\r
101	)\r
102	{\r
103	UINT8 RevId;\r
104	\r
105	RevId = MmioRead8 (\r
106	MmPciAddress (0,\r
107	DEFAULT_PCI_BUS_NUMBER_PCH,\r
108	PCI_DEVICE_NUMBER_PCH_LPC,\r
109	PCI_FUNCTION_NUMBER_PCH_LPC,\r
110	R_PCH_LPC_RID_CC)\r
111	);\r
112	\r
113	switch (RevId) {\r
114	case V_PCH_LPC_RID_0:\r
115	case V_PCH_LPC_RID_1:\r
116	return PchA0;\r
117	break;\r
118	\r
119	case V_PCH_LPC_RID_2:\r
120	case V_PCH_LPC_RID_3:\r
121	return PchA1;\r
122	break;\r
123	\r
124	case V_PCH_LPC_RID_4:\r
125	case V_PCH_LPC_RID_5:\r
126	return PchB0;\r
127	break;\r
128	\r
129	case V_PCH_LPC_RID_6:\r
130	case V_PCH_LPC_RID_7:\r
131	return PchB1;\r
132	break;\r
133	\r
134	case V_PCH_LPC_RID_8:\r
135	case V_PCH_LPC_RID_9:\r
136	return PchB2;\r
137	break;\r
138	\r
139	case V_PCH_LPC_RID_A:\r
140	case V_PCH_LPC_RID_B:\r
141	return PchB3;\r
142	break;\r
143	\r
144	case V_PCH_LPC_RID_C:\r
145	case V_PCH_LPC_RID_D:\r
146	return PchC0;\r
147	break;\r
148	\r
149	default:\r
150	return PchSteppingMax;\r
151	break;\r
152	\r
153	}\r
154	}\r
155	\r
156	/**\r
157	Enable legacy decoding on ICH6\r
158	\r
159	@param[in] none\r
160	\r
161	@retval EFI_SUCCESS Always returns success.\r
162	\r
163	**/\r
164	VOID\r
165	EnableInternalUart(\r
166	VOID\r
167	)\r
168	{\r
169	\r
170	//\r
171	// Program and enable PMC Base.\r
172	//\r
173	IoWrite32 (PCI_IDX, PCI_LPC_REG(R_PCH_LPC_PMC_BASE));\r
174	IoWrite32 (PCI_DAT, (PMC_BASE_ADDRESS \| B_PCH_LPC_PMC_BASE_EN));\r
175	\r
176	//\r
177	// Enable COM1 for debug message output.\r
178	//\r
179	MmioAndThenOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, (UINT32) (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR + B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);\r
180	\r
181	//\r
182	// Silicon Steppings\r
183	//\r
184	if (PchStepping()>= PchB0)\r
185	MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ4);\r
186	else\r
187	MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);\r
188	MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));\r
189	MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L\r
190	MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));\r
191	MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L\r
192	MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) B_PCH_LPC_UART_CTRL_COM1_EN);\r
193	\r
194	SerialPortInitialize ();\r
6ecc5d5c	195	SerialPortWrite ((UINT8 *)"EnableInternalUart!\r\n", sizeof("EnableInternalUart!\r\n") - 1);\r
3cbfba02 DW	196	\r
	197	return ;\r
	198	}\r