]> git.proxmox.com Git - mirror_edk2.git/blame - Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h
projects / mirror_edk2.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Vlv2TbltDevicePkg: Replace BSD License with BSD+Patent License
[mirror_edk2.git] / Vlv2TbltDevicePkg / Include / Guid / PlatformInfo.h
CommitLineData
3cbfba02
DW		 1/*++\r
2\r
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
4 \r\r
9dc8036d
MK		 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
6\r
3cbfba02
DW		 7 \r\r
8\r
9\r
10\r
11Module Name:\r
12\r
13 PlatformInfo.h\r
14\r
15Abstract:\r
16\r
17 GUID used for Platform Info Data entries in the HOB list.\r
18\r
19--*/\r
20\r
21#ifndef _PLATFORM_INFO_GUID_H_\r
22#define _PLATFORM_INFO_GUID_H_\r
23\r
24#ifndef ECP_FLAG\r
25#include <PiPei.h>\r
26\r
27#include <Library/HobLib.h>\r
28#include <Library/IoLib.h>\r
29#include <Library/DebugLib.h>\r
30#include <Library/SmbusLib.h>\r
31#include <IndustryStandard/SmBus.h>\r
32#endif\r
33\r
34#define PLATFORM_INFO_REVISION = 1 // Revision id for current platform information struct.\r
35\r
36//\r
37// Start::BayLake Board Defines\r
38//\r
39#define BOARD_REVISION_DEFAULT = 0xff\r
40#define UNKNOWN_FABID 0x0F\r
41#define FAB_ID_MASK 0x0F\r
42#define BOARD_ID_2 0x01\r
43#define BOARD_ID_1 0x40\r
44#define BOARD_ID_0 0x04\r
45\r
46#define BOARD_ID_DT_CRB 0x0\r
47#define BOARD_ID_DT_VLVR 0x1\r
48#define BOARD_ID_SVP_VLV 0xC\r
49#define BOARD_ID_SVP_EV_VLV 0xD\r
50//\r
51// End::BayLake Board Defines\r
52//\r
53\r
54//\r
55// Start::Alpine Valley Board Defines\r
56//\r
57#define DC_ID_DDR3L 0x00\r
58#define DC_ID_DDR3 0x04\r
59#define DC_ID_LPDDR3 0x02\r
60#define DC_ID_LPDDR2 0x06\r
61#define DC_ID_DDR4 0x01\r
62#define DC_ID_DDR3L_ECC 0x05\r
63#define DC_ID_NO_MEM 0x07\r
64//\r
65// End::Alpine Valley Board Defines\r
66//\r
67\r
68#define MAX_FAB_ID_RETRY_COUNT 100\r
69#define MAX_FAB_ID_CHECK_COUNT 3\r
70\r
71#define PLATFORM_INFO_HOB_REVISION 0x1\r
72\r
73#define EFI_PLATFORM_INFO_GUID \\r
74 { \\r
75 0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \\r
76 }\r
77\r
78extern EFI_GUID gEfiPlatformInfoGuid;\r
79\r
80typedef enum {\r
81 FlavorUnknown = 0,\r
82\r
83 //\r
84 // Mobile\r
85 //\r
86 FlavorMobile = 1,\r
87\r
88 //\r
89 // Desktop\r
90 //\r
91 FlavorDesktop = 2,\r
92\r
93 //\r
94 // Tablet\r
95 //\r
96 FlavorTablet = 3\r
97} PLATFORM_FLAVOR;\r
98\r
99#pragma pack(1)\r
100\r
101typedef struct {\r
102 UINT16 PciResourceIoBase;\r
103 UINT16 PciResourceIoLimit;\r
104 UINT32 PciResourceMem32Base;\r
105 UINT32 PciResourceMem32Limit;\r
106 UINT64 PciResourceMem64Base;\r
107 UINT64 PciResourceMem64Limit;\r
108 UINT64 PciExpressBase;\r
109 UINT32 PciExpressSize;\r
110 UINT8 PciHostAddressWidth;\r
111 UINT8 PciResourceMinSecBus;\r
112} EFI_PLATFORM_PCI_DATA;\r
113\r
114typedef struct {\r
115 UINT8 CpuAddressWidth;\r
116 UINT32 CpuFamilyStepping;\r
117} EFI_PLATFORM_CPU_DATA;\r
118\r
119typedef struct {\r
120 UINT8 SysIoApicEnable;\r
121 UINT8 SysSioExist;\r
122} EFI_PLATFORM_SYS_DATA;\r
123\r
124typedef struct {\r
125 UINT32 MemTolm;\r
126 UINT32 MemMaxTolm;\r
127 UINT32 MemTsegSize;\r
128 UINT32 MemTsegBase;\r
129 UINT32 MemIedSize;\r
130 UINT32 MemIgdSize;\r
131 UINT32 MemIgdBase;\r
132 UINT32 MemIgdGttSize;\r
133 UINT32 MemIgdGttBase;\r
134 UINT64 MemMir0;\r
135 UINT64 MemMir1;\r
136 UINT32 MemConfigSize;\r
137 UINT16 MmioSize;\r
138 UINT8 DdrFreq;\r
139 UINT8 DdrType; \r
140 UINT32 MemSize;\r
141 BOOLEAN EccSupport;\r
142 UINT8 Reserved[3];\r
143 UINT16 DimmSize[2];\r
144} EFI_PLATFORM_MEM_DATA;\r
145\r
146\r
147typedef struct {\r
148 UINT32 IgdOpRegionAddress; // IGD OpRegion Starting Address\r
149 UINT8 IgdBootType; // IGD Boot Display Device\r
150 UINT8 IgdPanelType; // IGD Panel Type CMOs option\r
151 UINT8 IgdTvFormat; // IGD TV Format CMOS option\r
152 UINT8 IgdTvMinor; // IGD TV Minor Format CMOS option\r
153 UINT8 IgdPanelScaling; // IGD Panel Scaling\r
154 UINT8 IgdBlcConfig; // IGD BLC Configuration\r
155 UINT8 IgdBiaConfig; // IGD BIA Configuration\r
156 UINT8 IgdSscConfig; // IGD SSC Configuration\r
157 UINT8 IgdDvmtMemSize; // IGD DVMT Memory Size\r
158 UINT8 IgdFunc1Enable; // IGD Function 1 Enable\r
159 UINT8 IgdHpllVco; // HPLL VCO\r
160 UINT8 IgdSciSmiMode; // GMCH SMI/SCI mode (0=SCI)\r
161 UINT8 IgdPAVP; // IGD PAVP data\r
162} EFI_PLATFORM_IGD_DATA;\r
163\r
164typedef enum {\r
165 BOARD_ID_AV_SVP = 0x0, // Alpine Valley Board\r
166 BOARD_ID_BL_RVP = 0x2, // BayLake Board (RVP)\r
167 BOARD_ID_BL_FFRD8 = 0x3, // FFRD8 b'0011\r
168 BOARD_ID_BL_FFRD = 0x4, // BayLake Board (FFRD)\r
169 BOARD_ID_BL_RVP_DDR3L = 0x5, // BayLake Board (RVP DDR3L)\r
170 BOARD_ID_BL_STHI = 0x7, // PPV- STHI Board\r
171 BOARD_ID_BB_RVP = 0x20, // Bayley Bay Board\r
172 BOARD_ID_BS_RVP = 0x30, // Bakersport Board\r
173 BOARD_ID_CVH = 0x90, // Crestview Hills\r
8b7a63e7
TH		 174 BOARD_ID_MINNOW2 = 0xA0, // MinnowBorad Max\r
175 BOARD_ID_MINNOW2_TURBOT = 0xB0 // MinnowBoard Turbot\r
3cbfba02
DW		 176\r
177} BOARD_ID_LIST;\r
178\r
179typedef enum {\r
180 FAB1 = 0,\r
181 FAB2 = 1,\r
182 FAB3 = 2\r
183} FAB_ID_LIST;\r
184\r
185typedef enum {\r
186 PR0 = 0, // FFRD PR0\r
187 PR05 = 1, // FFRD PR0.3 and PR 0.5\r
188 PR1 = 2, // FFRD PR1\r
189 PR11 = 3 // FFRD PR1.1\r
190} FFRD_ID_LIST;\r
191\r
192\r
193//\r
194// VLV2 GPIO GROUP OFFSET\r
195//\r
196#define GPIO_SCORE_OFFSET 0x0000\r
197#define GPIO_NCORE_OFFSET 0x1000\r
198#define GPIO_SSUS_OFFSET 0x2000\r
199\r
200//\r
201// GPIO Initialization Data Structure for BayLake.\r
202// SC = SCORE, SS= SSUS\r
203// Note: NC doesn't support GPIO functionality in IO access mode, only support in MMIO access mode.\r
204//\r
205\r
206//\r
207// IO space\r
208//\r
209typedef struct{\r
210 UINT32 Use_Sel_SC0;\r
211 UINT32 Use_Sel_SC1;\r
212 UINT32 Use_Sel_SC2;\r
213 UINT32 Use_Sel_SS;\r
214\r
215 UINT32 Io_Sel_SC0;\r
216 UINT32 Io_Sel_SC1;\r
217 UINT32 Io_Sel_SC2;\r
218 UINT32 Io_Sel_SS;\r
219\r
220 UINT32 GP_Lvl_SC0;\r
221 UINT32 GP_Lvl_SC1;\r
222 UINT32 GP_Lvl_SC2;\r
223 UINT32 GP_Lvl_SS;\r
224\r
225 UINT32 TPE_SC0;\r
226 UINT32 TPE_SS;\r
227\r
228 UINT32 TNE_SC0;\r
229 UINT32 TNE_SS;\r
230\r
231 UINT32 TS_SC0;\r
232 UINT32 TS_SS;\r
233\r
234 UINT32 WE_SS;\r
235} CFIO_INIT_STRUCT;\r
236\r
237\r
238\r
239//\r
240// CFIO PAD configuration Registers\r
241//\r
242//\r
243// Memory space\r
244//\r
245typedef union {\r
246 UINT32 dw;\r
247 struct {\r
248 UINT32 Func_Pin_Mux:3; // 0:2 Function of CFIO selection\r
249 UINT32 ipslew:2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width\r
250 UINT32 inslew:2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate\r
251 UINT32 Pull_assign:2; // 7:8 Pull assignment\r
252 UINT32 Pull_strength:2; // 9:10 Pull strength\r
253 UINT32 Bypass_flop:1; // 11 Bypass flop\r
254 UINT32 Filter_en:1; // 12 Filter Enable\r
255 UINT32 Hist_ctrl:2; // 13:14 hysteresis control\r
256 UINT32 Hist_enb:1; // 15 Hysteresis enable, active low\r
257 UINT32 Delay_line:6; // 16:21 Delay line values - Delay values for input or output\r
258 UINT32 Reserved:3; // 22:24 Reserved\r
259 UINT32 TPE:1; // 25 Trigger Positive Edge Enable\r
260 UINT32 TNE:1; // 26 Trigger Negative Edge Enable\r
261 UINT32 Reserved2:3; // 27:29 Reserved\r
262 UINT32 i1p5sel:1; // 30\r
263 UINT32 IODEN:1; // 31 : Open Drain enable. Active high\r
264 } r;\r
265} PAD_CONF0;\r
266\r
267typedef union{\r
268 UINT32 dw;\r
269 struct {\r
270 UINT32 instr:16; // 0:15 Pad (N) strength.\r
271 UINT32 ipstr:16; // 16:31 Pad (P) strength.\r
272 }r;\r
273} PAD_CONF1;\r
274\r
275typedef union{\r
276 UINT32 dw;\r
277 struct {\r
278 UINT32 pad_val:1; // 0 These registers are implemented as dual read/write with dedicated storage each.\r
279 UINT32 ioutenb:1; // 1 output enable\r
280 UINT32 iinenb:1; // 2 input enable\r
281 UINT32 Reserved:29; // 3:31 Reserved\r
282 }r;\r
283} PAD_VAL;\r
284\r
285typedef union{\r
286 UINT32 GPI;\r
287 struct {\r
288 UINT32 ihbpen:1; // 0 Pad high by pass enable\r
289 UINT32 ihbpinen:1; // 1 Pad high by pass input\r
290 UINT32 instaticen:1; // 2 TBD\r
291 UINT32 ipstaticen:1; // 3 TBD\r
292 UINT32 Overide_strap_pin :1; // 4 DFX indicates if it wants to override the strap pin value on this pad, if exists.\r
293 UINT32 Overide_strap_pin_val:1; // 5 In case DFX need to override strap pin value and it exist for the specific pad, this value will be used.\r
294 UINT32 TestMode_Pin_Mux:3; // 6:9 DFX Pin Muxing\r
295 }r;\r
296} PAD_DFT;\r
297\r
298//\r
299// GPIO_USAGE value need to matche the PAD_VAL input/output enable bits.\r
300//\r
301typedef enum {\r
302 Native = 0xFF, // Native, no need to set PAD_VALUE\r
303 GPI = 2, // GPI, input only in PAD_VALUE\r
304 GPO = 4, // GPO, output only in PAD_VALUE\r
305 GPIO = 0, // GPIO, input & output\r
306 TRISTS = 6, // Tri-State\r
307 GPIO_NONE\r
308} GPIO_USAGE;\r
309\r
310typedef enum {\r
311 LO = 0,\r
312 HI = 1,\r
313 NA = 0xFF\r
314} GPO_D4;\r
315\r
316typedef enum {\r
317 F0 = 0,\r
318 F1 = 1,\r
319 F2 = 2,\r
320 F3 = 3,\r
321 F4 = 4,\r
322 F5 = 5,\r
323 F6 = 6,\r
324 F7 = 7\r
325} GPIO_FUNC_NUM;\r
326\r
327//\r
328// Mapping to CONF0 bit 27:24\r
329// Note: Assume "Direct Irq En" is not set, unless specially notified.\r
330//\r
331typedef enum {\r
332 TRIG_ = 0,\r
333 TRIG_Edge_High = /*BIT3 |*/ BIT1, // Positive Edge (Rasing)\r
334 TRIG_Edge_Low = /*BIT3 |*/ BIT2, // Negative Edge (Falling)\r
335 TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1, // Both Edge\r
336 TRIG_Level_High= /*BIT3 |*/ BIT1 | BIT0, // Level High\r
337 TRIG_Level_Low = /*BIT3 |*/ BIT2 | BIT0, // Level Low\r
338} INT_TYPE;\r
339\r
340typedef enum {\r
341 P_20K_H, // Pull Up 20K\r
342 P_20K_L, // Pull Down 20K\r
343 P_10K_H, // Pull Up 10K\r
344 P_10K_L, // Pull Down 10K\r
345 P_2K_H, // Pull Up 2K\r
346 P_2K_L, // Pull Down 2K\r
347 P_NONE // Pull None\r
348} PULL_TYPE;\r
349\r
350#ifdef EFI_DEBUG\r
351 #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}\r
352#else\r
353 #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) { usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}\r
354#endif\r
355\r
356//\r
357// GPIO CONF & PAD Initialization Data Structure for BayLake GPIOs bits.\r
358// NC = NCORE, SC = SCORE, SS= SSUS\r
359//\r
360typedef struct {\r
361\r
362#ifdef EFI_DEBUG\r
363 char pad_name[32];// GPIO Pin Name for debug purpose\r
364#endif\r
365\r
366 GPIO_USAGE usage; // GPIO pin used as Native mode or GPI/GPO/GPIO mode\r
367 GPO_D4 gpod4; // GPO default value\r
368 GPIO_FUNC_NUM func; // Function Number (F0~F7)\r
369 INT_TYPE int_type; // Edge or Level trigger, low or high active\r
370 PULL_TYPE pull; // Pull Up or Down\r
371 UINT8 offset; // Equal with (PCONF0 register offset >> 4 bits)\r
372} GPIO_CONF_PAD_INIT;\r
373\r
374//\r
375//typedef UINT64 BOARD_FEATURES\r
376//\r
377typedef struct _EFI_PLATFORM_INFO_HOB {\r
378 UINT16 PlatformType; // Platform Type\r
379 UINT8 BoardId; // Board ID\r
380 UINT8 BoardRev; // Board Revision\r
381 PLATFORM_FLAVOR PlatformFlavor; // Platform Flavor\r
382 UINT8 DDRDaughterCardCh0Id;// DDR daughter card channel 0 id\r
383 UINT8 DDRDaughterCardCh1Id;// DDR daughter card channel 1 id\r
384 UINT8 ECOId; // ECO applied on platform\r
385 UINT16 IohSku;\r
386 UINT8 IohRevision;\r
387 UINT16 IchSku;\r
388 UINT8 IchRevision;\r
389 EFI_PLATFORM_PCI_DATA PciData;\r
390 EFI_PLATFORM_CPU_DATA CpuData;\r
391 EFI_PLATFORM_MEM_DATA MemData;\r
392 EFI_PLATFORM_SYS_DATA SysData;\r
393 EFI_PLATFORM_IGD_DATA IgdData;\r
394 UINT8 RevisonId; // Structure Revision ID\r
395 EFI_PHYSICAL_ADDRESS PlatformCfioData;\r
396 EFI_PHYSICAL_ADDRESS PlatformGpioData_NC;\r
397 EFI_PHYSICAL_ADDRESS PlatformGpioData_SC;\r
398 EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS;\r
399 EFI_PHYSICAL_ADDRESS PlatformGpioData_NC_TRI;\r
400 EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_TRI;\r
401 EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_TRI;\r
402 EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1;\r
403 EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_PR1_1;\r
404 EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1_1;\r
405\r
406 UINT8 CfioEnabled;\r
407 UINT32 SsidSvid;\r
408 UINT16 AudioSubsystemDeviceId;\r
409 UINT64 AcpiOemId;\r
410 UINT64 AcpiOemTableId;\r
411 UINT16 MemCfgID;\r
412} EFI_PLATFORM_INFO_HOB;\r
413\r
414#pragma pack()\r
415\r
416EFI_STATUS\r
417GetPlatformInfoHob (\r
418 IN CONST EFI_PEI_SERVICES **PeiServices,\r
419 OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob\r
420 );\r
421\r
422\r
423EFI_STATUS\r
424InstallPlatformClocksNotify (\r
425 IN CONST EFI_PEI_SERVICES **PeiServices\r
426 );\r
427\r
428EFI_STATUS\r
429InstallPlatformSysCtrlGPIONotify (\r
430 IN CONST EFI_PEI_SERVICES **PeiServices\r
431 );\r
432\r
433#endif\r
EFI Development Kit II mirror for PVE