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1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | \r | |
14 | \r | |
15 | Module Name:\r | |
16 | \r | |
17 | CpuIA32.h\r | |
18 | \r | |
19 | Abstract:\r | |
20 | \r | |
21 | --*/\r | |
22 | \r | |
23 | #ifndef _CPU_IA32_H\r | |
24 | #define _CPU_IA32_H\r | |
25 | \r | |
26 | typedef struct {\r | |
27 | UINT32 RegEax;\r | |
28 | UINT32 RegEbx;\r | |
29 | UINT32 RegEcx;\r | |
30 | UINT32 RegEdx;\r | |
31 | } EFI_CPUID_REGISTER;\r | |
32 | \r | |
33 | typedef struct {\r | |
34 | UINT32 HeaderVersion;\r | |
35 | UINT32 UpdateRevision;\r | |
36 | UINT32 Date;\r | |
37 | UINT32 ProcessorId;\r | |
38 | UINT32 Checksum;\r | |
39 | UINT32 LoaderRevision;\r | |
40 | UINT32 ProcessorFlags;\r | |
41 | UINT32 DataSize;\r | |
42 | UINT32 TotalSize;\r | |
43 | UINT8 Reserved[12];\r | |
44 | } EFI_CPU_MICROCODE_HEADER;\r | |
45 | \r | |
46 | typedef struct {\r | |
47 | UINT32 ExtendedSignatureCount;\r | |
48 | UINT32 ExtendedTableChecksum;\r | |
49 | UINT8 Reserved[12];\r | |
50 | } EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r | |
51 | \r | |
52 | typedef struct {\r | |
53 | UINT32 ProcessorSignature;\r | |
54 | UINT32 ProcessorFlag;\r | |
55 | UINT32 ProcessorChecksum;\r | |
56 | } EFI_CPU_MICROCODE_EXTENDED_TABLE;\r | |
57 | \r | |
58 | typedef struct {\r | |
59 | UINT32 Stepping : 4;\r | |
60 | UINT32 Model : 4;\r | |
61 | UINT32 Family : 4;\r | |
62 | UINT32 Type : 2;\r | |
63 | UINT32 Reserved1 : 2;\r | |
64 | UINT32 ExtendedModel : 4;\r | |
65 | UINT32 ExtendedFamily : 8;\r | |
66 | UINT32 Reserved2 : 4;\r | |
67 | } EFI_CPU_VERSION;\r | |
68 | \r | |
69 | #define EFI_CPUID_SIGNATURE 0x0\r | |
70 | #define EFI_CPUID_VERSION_INFO 0x1\r | |
71 | #define EFI_CPUID_CACHE_INFO 0x2\r | |
72 | #define EFI_CPUID_SERIAL_NUMBER 0x3\r | |
73 | #define EFI_CPUID_EXTENDED_FUNCTION 0x80000000\r | |
74 | #define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001\r | |
75 | #define EFI_CPUID_BRAND_STRING1 0x80000002\r | |
76 | #define EFI_CPUID_BRAND_STRING2 0x80000003\r | |
77 | #define EFI_CPUID_BRAND_STRING3 0x80000004\r | |
78 | \r | |
79 | #define EFI_MSR_IA32_PLATFORM_ID 0x17\r | |
80 | #define EFI_MSR_IA32_APIC_BASE 0x1B\r | |
81 | #define EFI_MSR_EBC_HARD_POWERON 0x2A\r | |
82 | #define EFI_MSR_EBC_SOFT_POWERON 0x2B\r | |
83 | #define BINIT_DRIVER_DISABLE 0x40\r | |
84 | #define INTERNAL_MCERR_DISABLE 0x20\r | |
85 | #define INITIATOR_MCERR_DISABLE 0x10\r | |
86 | #define EFI_MSR_EBC_FREQUENCY_ID 0x2C\r | |
87 | #define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79\r | |
88 | #define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B\r | |
89 | #define EFI_MSR_PSB_CLOCK_STATUS 0xCD\r | |
90 | #define EFI_APIC_GLOBAL_ENABLE 0x800\r | |
91 | #define EFI_MSR_IA32_MISC_ENABLE 0x1A0\r | |
92 | #define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000\r | |
93 | #define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008\r | |
94 | #define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004\r | |
95 | #define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002\r | |
96 | #define FAST_STRING_ENABLE_BIT 0x00000001\r | |
97 | \r | |
98 | #define EFI_CACHE_VARIABLE_MTRR_BASE 0x200\r | |
99 | #define EFI_CACHE_VARIABLE_MTRR_END 0x20F\r | |
100 | #define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF\r | |
101 | #define EFI_CACHE_MTRR_VALID 0x800\r | |
102 | #define EFI_CACHE_FIXED_MTRR_VALID 0x400\r | |
103 | #define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000\r | |
104 | #define EFI_MSR_VALID_MASK 0xFFFFFFFFF\r | |
105 | #define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000\r | |
106 | #define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF\r | |
107 | \r | |
108 | #define EFI_IA32_MTRR_FIX64K_00000 0x250\r | |
109 | #define EFI_IA32_MTRR_FIX16K_80000 0x258\r | |
110 | #define EFI_IA32_MTRR_FIX16K_A0000 0x259\r | |
111 | #define EFI_IA32_MTRR_FIX4K_C0000 0x268\r | |
112 | #define EFI_IA32_MTRR_FIX4K_C8000 0x269\r | |
113 | #define EFI_IA32_MTRR_FIX4K_D0000 0x26A\r | |
114 | #define EFI_IA32_MTRR_FIX4K_D8000 0x26B\r | |
115 | #define EFI_IA32_MTRR_FIX4K_E0000 0x26C\r | |
116 | #define EFI_IA32_MTRR_FIX4K_E8000 0x26D\r | |
117 | #define EFI_IA32_MTRR_FIX4K_F0000 0x26E\r | |
118 | #define EFI_IA32_MTRR_FIX4K_F8000 0x26F\r | |
119 | \r | |
120 | #define EFI_IA32_MCG_CAP 0x179\r | |
121 | #define EFI_IA32_MCG_CTL 0x17B\r | |
122 | #define EFI_IA32_MC0_CTL 0x400\r | |
123 | #define EFI_IA32_MC0_STATUS 0x401\r | |
124 | \r | |
125 | #define EFI_IA32_PERF_STATUS 0x198\r | |
126 | #define EFI_IA32_PERF_CTL 0x199\r | |
127 | \r | |
128 | #define EFI_CACHE_UNCACHEABLE 0\r | |
129 | #define EFI_CACHE_WRITECOMBINING 1\r | |
130 | #define EFI_CACHE_WRITETHROUGH 4\r | |
131 | #define EFI_CACHE_WRITEPROTECTED 5\r | |
132 | #define EFI_CACHE_WRITEBACK 6\r | |
133 | \r | |
134 | //\r | |
135 | // Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number\r | |
136 | //\r | |
137 | #define EfiMakeCpuVersion(f, m, s) \\r | |
138 | (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))\r | |
139 | \r | |
140 | /**\r | |
141 | Halt the Cpu\r | |
142 | \r | |
143 | @param[in] None\r | |
144 | \r | |
145 | @retval None\r | |
146 | \r | |
147 | **/\r | |
148 | VOID\r | |
149 | EFIAPI\r | |
150 | EfiHalt (\r | |
151 | VOID\r | |
152 | );\r | |
153 | \r | |
154 | /**\r | |
155 | Write back and invalidate the Cpu cache\r | |
156 | \r | |
157 | @param[in] None\r | |
158 | \r | |
159 | @retval None\r | |
160 | \r | |
161 | **/\r | |
162 | VOID\r | |
163 | EFIAPI\r | |
164 | EfiWbinvd (\r | |
165 | VOID\r | |
166 | );\r | |
167 | \r | |
168 | /**\r | |
169 | Invalidate the Cpu cache\r | |
170 | \r | |
171 | @param[in] None\r | |
172 | \r | |
173 | @retval None\r | |
174 | \r | |
175 | **/\r | |
176 | VOID\r | |
177 | EFIAPI\r | |
178 | EfiInvd (\r | |
179 | VOID\r | |
180 | );\r | |
181 | \r | |
182 | /**\r | |
2e182e30 | 183 | Get the Cpu info by execute the CPUID instruction\r |
3cbfba02 DW |
184 | \r |
185 | @param[in] RegisterInEax The input value to put into register EAX\r | |
186 | @param[in] Regs The Output value\r | |
187 | \r | |
188 | @retval None\r | |
189 | \r | |
190 | **/\r | |
191 | VOID\r | |
192 | EFIAPI\r | |
193 | EfiCpuid (\r | |
194 | IN UINT32 RegisterInEax,\r | |
195 | OUT EFI_CPUID_REGISTER *Regs\r | |
196 | );\r | |
197 | \r | |
198 | /**\r | |
199 | When RegisterInEax != 4, the functionality is the same as EfiCpuid.\r | |
200 | When RegisterInEax == 4, the function return the deterministic cache\r | |
201 | parameters by excuting the CPUID instruction.\r | |
202 | \r | |
203 | @param[in] RegisterInEax The input value to put into register EAX.\r | |
204 | @param[in] CacheLevel The deterministic cache level.\r | |
205 | @param[in] Regs The Output value.\r | |
206 | \r | |
207 | @retval None\r | |
208 | \r | |
209 | **/\r | |
210 | VOID\r | |
211 | EFIAPI\r | |
212 | EfiCpuidExt (\r | |
213 | IN UINT32 RegisterInEax,\r | |
214 | IN UINT32 CacheLevel,\r | |
215 | OUT EFI_CPUID_REGISTER *Regs\r | |
216 | );\r | |
217 | \r | |
218 | /**\r | |
219 | Read Cpu MSR\r | |
220 | \r | |
221 | @param[in] Index The index value to select the register\r | |
222 | \r | |
223 | @retval Return the read data\r | |
224 | \r | |
225 | **/\r | |
226 | UINT64\r | |
227 | EFIAPI\r | |
228 | EfiReadMsr (\r | |
229 | IN UINT32 Index\r | |
230 | );\r | |
231 | \r | |
232 | /**\r | |
233 | Write Cpu MSR\r | |
234 | \r | |
235 | @param[in] Index The index value to select the register\r | |
236 | @param[in] Value The value to write to the selected register\r | |
237 | \r | |
238 | @retval None\r | |
239 | \r | |
240 | **/\r | |
241 | VOID\r | |
242 | EFIAPI\r | |
243 | EfiWriteMsr (\r | |
244 | IN UINT32 Index,\r | |
245 | IN UINT64 Value\r | |
246 | );\r | |
247 | \r | |
248 | /**\r | |
249 | Read Time stamp\r | |
250 | \r | |
251 | @param[in] None\r | |
252 | \r | |
253 | @retval Return the read data\r | |
254 | \r | |
255 | **/\r | |
256 | UINT64\r | |
257 | EFIAPI\r | |
258 | EfiReadTsc (\r | |
259 | VOID\r | |
260 | );\r | |
261 | \r | |
262 | /**\r | |
263 | Writing back and invalidate the cache,then diable it\r | |
264 | \r | |
265 | @param[in] None\r | |
266 | \r | |
267 | @retval None\r | |
268 | \r | |
269 | **/\r | |
270 | VOID\r | |
271 | EFIAPI\r | |
272 | EfiDisableCache (\r | |
273 | VOID\r | |
274 | );\r | |
275 | \r | |
276 | /**\r | |
277 | Invalidate the cache,then Enable it\r | |
278 | \r | |
279 | @param[in] None\r | |
280 | \r | |
281 | @retval None\r | |
282 | \r | |
283 | **/\r | |
284 | VOID\r | |
285 | EFIAPI\r | |
286 | EfiEnableCache (\r | |
287 | VOID\r | |
288 | );\r | |
289 | \r | |
290 | /**\r | |
291 | Get Eflags\r | |
292 | \r | |
293 | @param[in] None\r | |
294 | \r | |
295 | @retval Return the Eflags value\r | |
296 | \r | |
297 | **/\r | |
298 | UINT32\r | |
299 | EFIAPI\r | |
300 | EfiGetEflags (\r | |
301 | VOID\r | |
302 | );\r | |
303 | \r | |
304 | /**\r | |
305 | Disable Interrupts\r | |
306 | \r | |
307 | @param[in] None\r | |
308 | \r | |
309 | @retval None\r | |
310 | \r | |
311 | **/\r | |
312 | VOID\r | |
313 | EFIAPI\r | |
314 | EfiDisableInterrupts (\r | |
315 | VOID\r | |
316 | );\r | |
317 | \r | |
318 | /**\r | |
319 | Enable Interrupts\r | |
320 | \r | |
321 | @param[in] None\r | |
322 | \r | |
323 | @retval None\r | |
324 | \r | |
325 | **/\r | |
326 | VOID\r | |
327 | EFIAPI\r | |
328 | EfiEnableInterrupts (\r | |
329 | VOID\r | |
330 | );\r | |
331 | \r | |
332 | /**\r | |
333 | Extract CPU detail version infomation\r | |
334 | \r | |
335 | @param[in] FamilyId FamilyId, including ExtendedFamilyId\r | |
336 | @param[in] Model Model, including ExtendedModel\r | |
337 | @param[in] SteppingId SteppingId\r | |
338 | @param[in] Processor Processor\r | |
339 | \r | |
340 | **/\r | |
341 | VOID\r | |
342 | EFIAPI\r | |
343 | EfiCpuVersion (\r | |
344 | IN UINT16 *FamilyId, OPTIONAL\r | |
345 | IN UINT8 *Model, OPTIONAL\r | |
346 | IN UINT8 *SteppingId, OPTIONAL\r | |
347 | IN UINT8 *Processor OPTIONAL\r | |
348 | );\r | |
349 | \r | |
350 | #endif\r |