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Vlv2TbltDevicePkg: Replace BSD License with BSD+Patent License
[mirror_edk2.git] / Vlv2TbltDevicePkg / Include / Library / CpuIA32.h
CommitLineData
3cbfba02
DW		 1/*++\r
2\r
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
4 \r\r
9dc8036d
MK		 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
6\r
3cbfba02
DW		 7 \r\r
8\r
9\r
10Module Name:\r
11\r
12 CpuIA32.h\r
13\r
14Abstract:\r
15\r
16--*/\r
17\r
18#ifndef _CPU_IA32_H\r
19#define _CPU_IA32_H\r
20\r
21typedef struct {\r
22 UINT32 RegEax;\r
23 UINT32 RegEbx;\r
24 UINT32 RegEcx;\r
25 UINT32 RegEdx;\r
26} EFI_CPUID_REGISTER;\r
27\r
28typedef struct {\r
29 UINT32 HeaderVersion;\r
30 UINT32 UpdateRevision;\r
31 UINT32 Date;\r
32 UINT32 ProcessorId;\r
33 UINT32 Checksum;\r
34 UINT32 LoaderRevision;\r
35 UINT32 ProcessorFlags;\r
36 UINT32 DataSize;\r
37 UINT32 TotalSize;\r
38 UINT8 Reserved[12];\r
39} EFI_CPU_MICROCODE_HEADER;\r
40\r
41typedef struct {\r
42 UINT32 ExtendedSignatureCount;\r
43 UINT32 ExtendedTableChecksum;\r
44 UINT8 Reserved[12];\r
45} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r
46\r
47typedef struct {\r
48 UINT32 ProcessorSignature;\r
49 UINT32 ProcessorFlag;\r
50 UINT32 ProcessorChecksum;\r
51} EFI_CPU_MICROCODE_EXTENDED_TABLE;\r
52\r
53typedef struct {\r
54 UINT32 Stepping : 4;\r
55 UINT32 Model : 4;\r
56 UINT32 Family : 4;\r
57 UINT32 Type : 2;\r
58 UINT32 Reserved1 : 2;\r
59 UINT32 ExtendedModel : 4;\r
60 UINT32 ExtendedFamily : 8;\r
61 UINT32 Reserved2 : 4;\r
62} EFI_CPU_VERSION;\r
63\r
64#define EFI_CPUID_SIGNATURE 0x0\r
65#define EFI_CPUID_VERSION_INFO 0x1\r
66#define EFI_CPUID_CACHE_INFO 0x2\r
67#define EFI_CPUID_SERIAL_NUMBER 0x3\r
68#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000\r
69#define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001\r
70#define EFI_CPUID_BRAND_STRING1 0x80000002\r
71#define EFI_CPUID_BRAND_STRING2 0x80000003\r
72#define EFI_CPUID_BRAND_STRING3 0x80000004\r
73\r
74#define EFI_MSR_IA32_PLATFORM_ID 0x17\r
75#define EFI_MSR_IA32_APIC_BASE 0x1B\r
76#define EFI_MSR_EBC_HARD_POWERON 0x2A\r
77#define EFI_MSR_EBC_SOFT_POWERON 0x2B\r
78#define BINIT_DRIVER_DISABLE 0x40\r
79#define INTERNAL_MCERR_DISABLE 0x20\r
80#define INITIATOR_MCERR_DISABLE 0x10\r
81#define EFI_MSR_EBC_FREQUENCY_ID 0x2C\r
82#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79\r
83#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B\r
84#define EFI_MSR_PSB_CLOCK_STATUS 0xCD\r
85#define EFI_APIC_GLOBAL_ENABLE 0x800\r
86#define EFI_MSR_IA32_MISC_ENABLE 0x1A0\r
87#define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000\r
88#define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008\r
89#define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004\r
90#define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002\r
91#define FAST_STRING_ENABLE_BIT 0x00000001\r
92\r
93#define EFI_CACHE_VARIABLE_MTRR_BASE 0x200\r
94#define EFI_CACHE_VARIABLE_MTRR_END 0x20F\r
95#define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF\r
96#define EFI_CACHE_MTRR_VALID 0x800\r
97#define EFI_CACHE_FIXED_MTRR_VALID 0x400\r
98#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000\r
99#define EFI_MSR_VALID_MASK 0xFFFFFFFFF\r
100#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000\r
101#define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF\r
102\r
103#define EFI_IA32_MTRR_FIX64K_00000 0x250\r
104#define EFI_IA32_MTRR_FIX16K_80000 0x258\r
105#define EFI_IA32_MTRR_FIX16K_A0000 0x259\r
106#define EFI_IA32_MTRR_FIX4K_C0000 0x268\r
107#define EFI_IA32_MTRR_FIX4K_C8000 0x269\r
108#define EFI_IA32_MTRR_FIX4K_D0000 0x26A\r
109#define EFI_IA32_MTRR_FIX4K_D8000 0x26B\r
110#define EFI_IA32_MTRR_FIX4K_E0000 0x26C\r
111#define EFI_IA32_MTRR_FIX4K_E8000 0x26D\r
112#define EFI_IA32_MTRR_FIX4K_F0000 0x26E\r
113#define EFI_IA32_MTRR_FIX4K_F8000 0x26F\r
114\r
115#define EFI_IA32_MCG_CAP 0x179\r
116#define EFI_IA32_MCG_CTL 0x17B\r
117#define EFI_IA32_MC0_CTL 0x400\r
118#define EFI_IA32_MC0_STATUS 0x401\r
119\r
120#define EFI_IA32_PERF_STATUS 0x198\r
121#define EFI_IA32_PERF_CTL 0x199\r
122\r
123#define EFI_CACHE_UNCACHEABLE 0\r
124#define EFI_CACHE_WRITECOMBINING 1\r
125#define EFI_CACHE_WRITETHROUGH 4\r
126#define EFI_CACHE_WRITEPROTECTED 5\r
127#define EFI_CACHE_WRITEBACK 6\r
128\r
129//\r
130// Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number\r
131//\r
132#define EfiMakeCpuVersion(f, m, s) \\r
133 (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))\r
134\r
135/**\r
136 Halt the Cpu\r
137\r
138 @param[in] None\r
139\r
140 @retval None\r
141\r
142**/\r
143VOID\r
144EFIAPI\r
145EfiHalt (\r
146 VOID\r
147 );\r
148\r
149/**\r
150 Write back and invalidate the Cpu cache\r
151\r
152 @param[in] None\r
153\r
154 @retval None\r
155\r
156**/\r
157VOID\r
158EFIAPI\r
159EfiWbinvd (\r
160 VOID\r
161 );\r
162\r
163/**\r
164 Invalidate the Cpu cache\r
165\r
166 @param[in] None\r
167\r
168 @retval None\r
169\r
170**/\r
171VOID\r
172EFIAPI\r
173EfiInvd (\r
174 VOID\r
175 );\r
176\r
177/**\r
2e182e30 178 Get the Cpu info by execute the CPUID instruction\r
3cbfba02
DW		 179\r
180 @param[in] RegisterInEax The input value to put into register EAX\r
181 @param[in] Regs The Output value\r
182\r
183 @retval None\r
184\r
185**/\r
186VOID\r
187EFIAPI\r
188EfiCpuid (\r
189 IN UINT32 RegisterInEax,\r
190 OUT EFI_CPUID_REGISTER *Regs\r
191 );\r
192\r
193/**\r
194 When RegisterInEax != 4, the functionality is the same as EfiCpuid.\r
195 When RegisterInEax == 4, the function return the deterministic cache\r
196 parameters by excuting the CPUID instruction.\r
197\r
198 @param[in] RegisterInEax The input value to put into register EAX.\r
199 @param[in] CacheLevel The deterministic cache level.\r
200 @param[in] Regs The Output value.\r
201\r
202 @retval None\r
203\r
204**/\r
205VOID\r
206EFIAPI\r
207EfiCpuidExt (\r
208 IN UINT32 RegisterInEax,\r
209 IN UINT32 CacheLevel,\r
210 OUT EFI_CPUID_REGISTER *Regs\r
211 );\r
212\r
213/**\r
214 Read Cpu MSR\r
215\r
216 @param[in] Index The index value to select the register\r
217\r
218 @retval Return the read data\r
219\r
220**/\r
221UINT64\r
222EFIAPI\r
223EfiReadMsr (\r
224 IN UINT32 Index\r
225 );\r
226\r
227/**\r
228 Write Cpu MSR\r
229\r
230 @param[in] Index The index value to select the register\r
231 @param[in] Value The value to write to the selected register\r
232\r
233 @retval None\r
234\r
235**/\r
236VOID\r
237EFIAPI\r
238EfiWriteMsr (\r
239 IN UINT32 Index,\r
240 IN UINT64 Value\r
241 );\r
242\r
243/**\r
244 Read Time stamp\r
245\r
246 @param[in] None\r
247\r
248 @retval Return the read data\r
249\r
250**/\r
251UINT64\r
252EFIAPI\r
253EfiReadTsc (\r
254 VOID\r
255 );\r
256\r
257/**\r
258 Writing back and invalidate the cache,then diable it\r
259\r
260 @param[in] None\r
261\r
262 @retval None\r
263\r
264**/\r
265VOID\r
266EFIAPI\r
267EfiDisableCache (\r
268 VOID\r
269 );\r
270\r
271/**\r
272 Invalidate the cache,then Enable it\r
273\r
274 @param[in] None\r
275\r
276 @retval None\r
277\r
278**/\r
279VOID\r
280EFIAPI\r
281EfiEnableCache (\r
282 VOID\r
283 );\r
284\r
285/**\r
286 Get Eflags\r
287\r
288 @param[in] None\r
289\r
290 @retval Return the Eflags value\r
291\r
292**/\r
293UINT32\r
294EFIAPI\r
295EfiGetEflags (\r
296 VOID\r
297 );\r
298\r
299/**\r
300 Disable Interrupts\r
301\r
302 @param[in] None\r
303\r
304 @retval None\r
305\r
306**/\r
307VOID\r
308EFIAPI\r
309EfiDisableInterrupts (\r
310 VOID\r
311 );\r
312\r
313/**\r
314 Enable Interrupts\r
315\r
316 @param[in] None\r
317\r
318 @retval None\r
319\r
320**/\r
321VOID\r
322EFIAPI\r
323EfiEnableInterrupts (\r
324 VOID\r
325 );\r
326\r
327/**\r
328 Extract CPU detail version infomation\r
329\r
330 @param[in] FamilyId FamilyId, including ExtendedFamilyId\r
331 @param[in] Model Model, including ExtendedModel\r
332 @param[in] SteppingId SteppingId\r
333 @param[in] Processor Processor\r
334\r
335**/\r
336VOID\r
337EFIAPI\r
338EfiCpuVersion (\r
339 IN UINT16 *FamilyId, OPTIONAL\r
340 IN UINT8 *Model, OPTIONAL\r
341 IN UINT8 *SteppingId, OPTIONAL\r
342 IN UINT8 *Processor OPTIONAL\r
343 );\r
344\r
345#endif\r
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