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1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef _SPIFlash_H_\r | |
16 | #define _SPIFlash_H_\r | |
17 | \r | |
18 | #include <Protocol/Spi.h>\r | |
19 | \r | |
20 | //EFI_STATUS SpiFlashLock(BOOLEAN Lock);\r | |
21 | //EFI_STATUS SpiFlashInit(void);\r | |
22 | \r | |
23 | typedef enum {\r | |
24 | EnumSpiFlashW25Q64,\r | |
25 | EnumSpiFlashAT25DF321A,\r | |
26 | EnumSpiFlashAT26DF321,\r | |
27 | EnumSpiFlashAT25DF641,\r | |
28 | EnumSpiFlashW25Q16,\r | |
29 | EnumSpiFlashW25Q32,\r | |
30 | EnumSpiFlashW25X32,\r | |
31 | EnumSpiFlashW25X64,\r | |
32 | EnumSpiFlashW25Q128,\r | |
33 | EnumSpiFlashMX25L16,\r | |
34 | EnumSpiFlashMX25L32,\r | |
35 | EnumSpiFlashMX25L64,\r | |
36 | EnumSpiFlashMX25L128,\r | |
37 | EnumSpiFlashMX25U6435F,\r | |
38 | EnumSpiFlashSST25VF016B,\r | |
39 | EnumSpiFlashSST25VF064C,\r | |
40 | EnumSpiFlashN25Q064,\r | |
41 | EnumSpiFlashM25PX16,\r | |
42 | EnumSpiFlashN25Q032,\r | |
43 | EnumSpiFlashM25PX32,\r | |
44 | EnumSpiFlashM25PX64,\r | |
45 | EnumSpiFlashN25Q128,\r | |
46 | EnumSpiFlashEN25Q16,\r | |
47 | EnumSpiFlashEN25Q32,\r | |
48 | EnumSpiFlashEN25Q64,\r | |
49 | EnumSpiFlashEN25Q128,\r | |
50 | EnumSpiFlashA25L016,\r | |
51 | EnumSpiFlashMax\r | |
52 | } SPI_FLASH_TYPES_SUPPORTED;\r | |
53 | \r | |
54 | //\r | |
55 | // Serial Flash VendorId and DeviceId\r | |
56 | //\r | |
57 | #define SF_VENDOR_ID_ATMEL 0x1F\r | |
58 | #define SF_DEVICE_ID0_AT26DF321 0x47\r | |
59 | #define SF_DEVICE_ID1_AT26DF321 0x00\r | |
60 | #define SF_DEVICE_ID0_AT25DF321A 0x47\r | |
61 | #define SF_DEVICE_ID1_AT25DF321A 0x01\r | |
62 | #define SF_DEVICE_ID0_AT25DF641 0x48\r | |
63 | #define SF_DEVICE_ID1_AT25DF641 0x00\r | |
64 | \r | |
65 | #define SF_VENDOR_ID_WINBOND 0xEF\r | |
66 | #define SF_DEVICE_ID0_W25XXX 0x30\r | |
67 | #define SF_DEVICE_ID1_W25X32 0x16\r | |
68 | #define SF_DEVICE_ID1_W25X64 0x17\r | |
6f2ef18e | 69 | #define SF_DEVICE_ID0_W25QXX 0x40\r |
3cbfba02 DW |
70 | #define SF_DEVICE_ID1_W25Q16 0x15\r |
71 | #define SF_DEVICE_ID1_W25Q32 0x16\r | |
72 | #define SF_DEVICE_ID1_W25Q64 0x17\r | |
73 | #define SF_DEVICE_ID1_W25Q128 0x18\r | |
74 | \r | |
75 | #define SF_VENDOR_ID_MACRONIX 0xC2\r | |
76 | #define SF_DEVICE_ID0_MX25LXX 0x20\r | |
77 | #define SF_DEVICE_ID1_MX25L16 0x15\r | |
78 | #define SF_DEVICE_ID1_MX25L32 0x16\r | |
79 | #define SF_DEVICE_ID1_MX25L64 0x17\r | |
80 | #define SF_DEVICE_ID1_MX25L128 0x18\r | |
81 | #define SF_DEVICE_ID0_MX25UXX 0x25\r | |
82 | #define SF_DEVICE_ID1_MX25U6435F 0x37\r | |
83 | \r | |
84 | #define SF_VENDOR_ID_NUMONYX 0x20\r | |
85 | #define SF_DEVICE_ID0_N25Q064 0xBB\r | |
86 | #define SF_DEVICE_ID1_N25Q064 0x17\r | |
87 | #define SF_DEVICE_ID0_M25PXXX 0x71\r | |
88 | #define SF_DEVICE_ID0_N25QXXX 0xBA\r | |
89 | #define SF_DEVICE_ID1_M25PX16 0x15\r | |
90 | #define SF_DEVICE_ID1_N25Q032 0x16\r | |
91 | #define SF_DEVICE_ID1_M25PX32 0x16\r | |
92 | #define SF_DEVICE_ID1_M25PX64 0x17\r | |
93 | #define SF_DEVICE_ID1_N25Q128 0x18\r | |
94 | \r | |
95 | #define SF_VENDOR_ID_SST 0xBF\r | |
96 | #define SF_DEVICE_ID0_SST25VF0XXX 0x25\r | |
97 | #define SF_DEVICE_ID1_SST25VF016B 0x41\r | |
98 | #define SF_DEVICE_ID1_SST25VF064C 0x4B\r | |
99 | \r | |
100 | #define SF_VENDOR_ID_EON 0x1C\r | |
101 | #define SF_DEVICE_ID0_EN25QXX 0x30\r | |
102 | #define SF_DEVICE_ID1_EN25Q16 0x15\r | |
103 | #define SF_DEVICE_ID1_EN25Q32 0x16\r | |
104 | #define SF_DEVICE_ID1_EN25Q64 0x17\r | |
105 | #define SF_DEVICE_ID1_EN25Q128 0x18\r | |
106 | \r | |
107 | #define SF_VENDOR_ID_AMIC 0x37\r | |
108 | #define SF_DEVICE_ID0_A25L016 0x30\r | |
109 | #define SF_DEVICE_ID1_A25L016 0x15\r | |
110 | \r | |
111 | #define ATMEL_AT26DF321_SIZE 0x00400000\r | |
112 | #define ATMEL_AT25DF321A_SIZE 0x00400000\r | |
113 | #define ATMEL_AT25DF641_SIZE 0x00800000\r | |
114 | #define WINBOND_W25X32_SIZE 0x00400000\r | |
115 | #define WINBOND_W25X64_SIZE 0x00800000\r | |
116 | #define WINBOND_W25Q16_SIZE 0x00200000\r | |
117 | #define WINBOND_W25Q32_SIZE 0x00400000\r | |
118 | #define WINBOND_W25Q64_SIZE 0x00800000\r | |
119 | #define WINBOND_W25Q128_SIZE 0x01000000\r | |
120 | #define SST_SST25VF016B_SIZE 0x00200000\r | |
121 | #define SST_SST25VF064C_SIZE 0x00800000\r | |
122 | #define MACRONIX_MX25L16_SIZE 0x00200000\r | |
123 | #define MACRONIX_MX25L32_SIZE 0x00400000\r | |
124 | #define MACRONIX_MX25L64_SIZE 0x00800000\r | |
125 | #define MACRONIX_MX25U64_SIZE 0x00800000\r | |
126 | #define MACRONIX_MX25L128_SIZE 0x01000000\r | |
127 | #define NUMONYX_M25PX16_SIZE 0x00400000\r | |
128 | #define NUMONYX_N25Q032_SIZE 0x00400000\r | |
129 | #define NUMONYX_M25PX32_SIZE 0x00400000\r | |
130 | #define NUMONYX_M25PX64_SIZE 0x00800000\r | |
131 | #define NUMONYX_N25Q064_SIZE 0x00800000\r | |
132 | #define NUMONYX_N25Q128_SIZE 0x01000000\r | |
133 | #define EON_EN25Q16_SIZE 0x00200000\r | |
134 | #define EON_EN25Q32_SIZE 0x00400000\r | |
135 | #define EON_EN25Q64_SIZE 0x00800000\r | |
136 | #define EON_EN25Q128_SIZE 0x01000000\r | |
137 | #define AMIC_A25L16_SIZE 0x00200000\r | |
138 | \r | |
139 | #define SF_VENDOR_ID_SST 0xBF\r | |
140 | #define SF_DEVICE_ID0_25LF080A 0x25\r | |
141 | #define SF_DEVICE_ID1_25LF080A 0x8E\r | |
142 | #define SF_DEVICE_ID0_25VF016B 0x25\r | |
143 | #define SF_DEVICE_ID1_25VF016B 0x41\r | |
144 | \r | |
145 | #define SF_VENDOR_ID_ATMEL 0x1F\r | |
146 | #define SF_DEVICE_ID0_AT26DF321 0x47\r | |
147 | #define SF_DEVICE_ID1_AT26DF321 0x00\r | |
148 | \r | |
149 | #define SF_VENDOR_ID_STM 0x20\r | |
150 | #define SF_DEVICE_ID0_M25P32 0x20\r | |
151 | #define SF_DEVICE_ID1_M25P32 0x16\r | |
152 | \r | |
153 | #define SF_VENDOR_ID_WINBOND 0xEF\r | |
154 | #define SF_DEVICE_ID0_W25XXX 0x30\r | |
6f2ef18e | 155 | \r |
3cbfba02 DW |
156 | #define SF_DEVICE_ID1_W25X80 0x14\r |
157 | #define SF_DEVICE_ID1_W25X16 0x15\r | |
158 | #define SF_DEVICE_ID1_W25X32 0x16\r | |
159 | #define SF_DEVICE_ID1_W25X64 0x17\r | |
160 | \r | |
161 | #define SF_VENDOR_ID_MX 0xC2\r | |
162 | #define SF_DEVICE_ID0_25L1605A 0x20\r | |
163 | #define SF_DEVICE_ID1_25L1605A 0x15\r | |
164 | \r | |
165 | #define SF_VENDOR_ID_NUMONYX 0x20\r | |
166 | #define SF_DEVICE_ID0_M25PX16 0x71\r | |
167 | #define SF_DEVICE_ID1_M25PX16 0x15\r | |
168 | \r | |
169 | #define SST_25LF080A_SIZE 0x00100000\r | |
170 | #define SST_25LF016B_SIZE 0x00200000\r | |
171 | #define ATMEL_AT26DF321_SIZE 0x00400000\r | |
172 | #define STM_M25P32_SIZE 0x00400000\r | |
173 | #define WINBOND_W25X80_SIZE 0x00100000\r | |
174 | #define WINBOND_W25X16_SIZE 0x00200000\r | |
175 | #define WINBOND_W25X32_SIZE 0x00400000\r | |
176 | #define WINBOND_W25X64_SIZE 0x00800000\r | |
177 | #define MX_25L1605A_SIZE 0x00200000\r | |
178 | \r | |
179 | //\r | |
180 | // Physical Sector Size on the Serial Flash device\r | |
181 | //\r | |
182 | #define SF_SECTOR_SIZE 0x1000\r | |
183 | #define SF_BLOCK_SIZE 0x8000\r | |
184 | \r | |
185 | //\r | |
186 | // Serial Flash Status Register definitions\r | |
187 | //\r | |
188 | #define SF_SR_BUSY 0x01 // Indicates if internal write operation is in progress\r | |
189 | #define SF_SR_WEL 0x02 // Indicates if device is memory write enabled\r | |
190 | #define SF_SR_BP0 0x04 // Block protection bit 0\r | |
191 | #define SF_SR_BP1 0x08 // Block protection bit 1\r | |
192 | #define SF_SR_BP2 0x10 // Block protection bit 2\r | |
193 | #define SF_SR_BP3 0x20 // Block protection bit 3\r | |
194 | #define SF_SR_WPE 0x3C // Enable write protection on all blocks\r | |
195 | #define SF_SR_AAI 0x40 // Auto Address Increment Programming status\r | |
196 | #define SF_SR_BPL 0x80 // Block protection lock-down\r | |
197 | \r | |
198 | //\r | |
199 | // Operation Instruction definitions for the Serial Flash Device\r | |
200 | //\r | |
201 | #define SF_INST_WRSR 0x01 // Write Status Register\r | |
202 | #define SF_INST_PROG 0x02 // Byte Program\r | |
203 | #define SF_INST_READ 0x03 // Read\r | |
204 | #define SF_INST_WRDI 0x04 // Write Disable\r | |
205 | #define SF_INST_RDSR 0x05 // Read Status Register\r | |
206 | #define SF_INST_WREN 0x06 // Write Enable\r | |
207 | #define SF_INST_HS_READ 0x0B // High-speed Read\r | |
208 | #define SF_INST_SERASE 0x20 // Sector Erase (4KB)\r | |
209 | #define SF_INST_BERASE 0x52 // Block Erase (32KB)\r | |
210 | #define SF_INST_64KB_ERASE 0xD8 // Block Erase (64KB)\r | |
211 | #define SF_INST_EWSR 0x50 // Enable Write Status Register\r | |
212 | #define SF_INST_READ_ID 0xAB // Read ID\r | |
213 | #define SF_INST_JEDEC_READ_ID 0x9F // JEDEC Read ID\r | |
214 | #define SF_INST_DOFR 0x3B // Dual Output Fast Read\r | |
215 | #define SF_INST_SFDP 0x5A // Serial Flash Discovery Parameters\r | |
216 | \r | |
217 | #define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size\r | |
218 | #define SECTOR_SIZE_64KB 0x10000 // Common 64kBytes sector size\r | |
219 | #define BLOCK_SIZE_64KB 0x00010000 // Common 64kBytes block size\r | |
220 | #define MAX_FWH_SIZE 0x00100000 // 8Mbit (Note that this can also be used for the 4Mbit )\r | |
221 | \r | |
222 | //\r | |
223 | // Prefix Opcode Index on the host SPI controller\r | |
224 | //\r | |
225 | typedef enum {\r | |
226 | SPI_WREN, // Prefix Opcode 0: Write Enable\r | |
227 | SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register\r | |
228 | } PREFIX_OPCODE_INDEX;\r | |
229 | \r | |
230 | //\r | |
231 | // Opcode Menu Index on the host SPI controller\r | |
232 | //\r | |
233 | typedef enum {\r | |
234 | SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address\r | |
235 | SPI_READ, // Opcode 1: READ, Read cycle with address\r | |
236 | SPI_RDSR, // Opcode 2: Read Status Register, No address\r | |
237 | SPI_WRDI_SFDP, // Opcode 3: Write Disable or Discovery Parameters, No address\r | |
238 | SPI_SERASE, // Opcode 4: Sector Erase (4KB), Write cycle with address\r | |
239 | SPI_BERASE, // Opcode 5: Block Erase (32KB), Write cycle with address\r | |
240 | SPI_PROG, // Opcode 6: Byte Program, Write cycle with address\r | |
241 | SPI_WRSR, // Opcode 7: Write Status Register, No address\r | |
242 | } SPI_OPCODE_INDEX;\r | |
243 | \r | |
244 | #endif\r |